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Root/trunk/spi25_statusreg.c

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1/*
2 * This file is part of the flashrom project.
3 * It handles everything related to status registers of the JEDEC family 25.
4 *
5 * Copyright (C) 2007, 2008, 2009, 2010 Carl-Daniel Hailfinger
6 * Copyright (C) 2008 coresystems GmbH
7 * Copyright (C) 2008 Ronald Hoogenboom <ronald@zonnet.nl>
8 * Copyright (C) 2012 Stefan Tauner
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; version 2 of the License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 */
23
24#include "flash.h"
25#include "chipdrivers.h"
26#include "spi.h"
27
28/* === Generic functions === */
29int spi_write_status_enable(struct flashctx *flash)
30{
31static const unsigned char cmd[JEDEC_EWSR_OUTSIZE] = { JEDEC_EWSR };
32int result;
33
34/* Send EWSR (Enable Write Status Register). */
35result = spi_send_command(flash, sizeof(cmd), JEDEC_EWSR_INSIZE, cmd, NULL);
36
37if (result)
38msg_cerr("%s failed\n", __func__);
39
40return result;
41}
42
43static int spi_write_status_register_flag(struct flashctx *flash, int status, const unsigned char enable_opcode)
44{
45int result;
46int i = 0;
47/*
48 * WRSR requires either EWSR or WREN depending on chip type.
49 * The code below relies on the fact hat EWSR and WREN have the same
50 * INSIZE and OUTSIZE.
51 */
52struct spi_command cmds[] = {
53{
54.writecnt= JEDEC_WREN_OUTSIZE,
55.writearr= (const unsigned char[]){ enable_opcode },
56.readcnt= 0,
57.readarr= NULL,
58}, {
59.writecnt= JEDEC_WRSR_OUTSIZE,
60.writearr= (const unsigned char[]){ JEDEC_WRSR, (unsigned char) status },
61.readcnt= 0,
62.readarr= NULL,
63}, {
64.writecnt= 0,
65.writearr= NULL,
66.readcnt= 0,
67.readarr= NULL,
68}};
69
70result = spi_send_multicommand(flash, cmds);
71if (result) {
72msg_cerr("%s failed during command execution\n", __func__);
73/* No point in waiting for the command to complete if execution
74 * failed.
75 */
76return result;
77}
78/* WRSR performs a self-timed erase before the changes take effect.
79 * This may take 50-85 ms in most cases, and some chips apparently
80 * allow running RDSR only once. Therefore pick an initial delay of
81 * 100 ms, then wait in 10 ms steps until a total of 5 s have elapsed.
82 */
83programmer_delay(100 * 1000);
84while (spi_read_status_register(flash) & SPI_SR_WIP) {
85if (++i > 490) {
86msg_cerr("Error: WIP bit after WRSR never cleared\n");
87return TIMEOUT_ERROR;
88}
89programmer_delay(10 * 1000);
90}
91return 0;
92}
93
94int spi_write_status_register(struct flashctx *flash, int status)
95{
96int feature_bits = flash->chip->feature_bits;
97int ret = 1;
98
99if (!(feature_bits & (FEATURE_WRSR_WREN | FEATURE_WRSR_EWSR))) {
100msg_cdbg("Missing status register write definition, assuming "
101 "EWSR is needed\n");
102feature_bits |= FEATURE_WRSR_EWSR;
103}
104if (feature_bits & FEATURE_WRSR_WREN)
105ret = spi_write_status_register_flag(flash, status, JEDEC_WREN);
106if (ret && (feature_bits & FEATURE_WRSR_EWSR))
107ret = spi_write_status_register_flag(flash, status, JEDEC_EWSR);
108return ret;
109}
110
111uint8_t spi_read_status_register(struct flashctx *flash)
112{
113static const unsigned char cmd[JEDEC_RDSR_OUTSIZE] = { JEDEC_RDSR };
114/* FIXME: No workarounds for driver/hardware bugs in generic code. */
115unsigned char readarr[2]; /* JEDEC_RDSR_INSIZE=1 but wbsio needs 2 */
116int ret;
117
118/* Read Status Register */
119ret = spi_send_command(flash, sizeof(cmd), sizeof(readarr), cmd, readarr);
120if (ret)
121msg_cerr("RDSR failed!\n");
122
123return readarr[0];
124}
125
126/* A generic block protection disable.
127 * Tests if a protection is enabled with the block protection mask (bp_mask) and returns success otherwise.
128 * Tests if the register bits are locked with the lock_mask (lock_mask).
129 * Tests if a hardware protection is active (i.e. low pin/high bit value) with the write protection mask
130 * (wp_mask) and bails out in that case.
131 * If there are register lock bits set we try to disable them by unsetting those bits of the previous register
132 * contents that are set in the lock_mask. We then check if removing the lock bits has worked and continue as if
133 * they never had been engaged:
134 * If the lock bits are out of the way try to disable engaged protections.
135 * To support uncommon global unprotects (e.g. on most AT2[56]xx1(A)) unprotect_mask can be used to force
136 * bits to 0 additionally to those set in bp_mask and lock_mask. Only bits set in unprotect_mask are potentially
137 * preserved when doing the final unprotect.
138 *
139 * To sum up:
140 * bp_mask: set those bits that correspond to the bits in the status register that indicate an active protection
141 * (which should be unset after this function returns).
142 * lock_mask: set the bits that correspond to the bits that lock changing the bits above.
143 * wp_mask: set the bits that correspond to bits indicating non-software revocable protections.
144 * unprotect_mask: set the bits that should be preserved if possible when unprotecting.
145 */
146static int spi_disable_blockprotect_generic(struct flashctx *flash, uint8_t bp_mask, uint8_t lock_mask, uint8_t wp_mask, uint8_t unprotect_mask)
147{
148uint8_t status;
149int result;
150
151status = spi_read_status_register(flash);
152if ((status & bp_mask) == 0) {
153msg_cdbg2("Block protection is disabled.\n");
154return 0;
155}
156
157msg_cdbg("Some block protection in effect, disabling... ");
158if ((status & lock_mask) != 0) {
159msg_cdbg("\n\tNeed to disable the register lock first... ");
160if (wp_mask != 0 && (status & wp_mask) == 0) {
161msg_cerr("Hardware protection is active, disabling write protection is impossible.\n");
162return 1;
163}
164/* All bits except the register lock bit (often called SPRL, SRWD, WPEN) are readonly. */
165result = spi_write_status_register(flash, status & ~lock_mask);
166if (result) {
167msg_cerr("spi_write_status_register failed.\n");
168return result;
169}
170status = spi_read_status_register(flash);
171if ((status & lock_mask) != 0) {
172msg_cerr("Unsetting lock bit(s) failed.\n");
173return 1;
174}
175msg_cdbg("done.\n");
176}
177/* Global unprotect. Make sure to mask the register lock bit as well. */
178result = spi_write_status_register(flash, status & ~(bp_mask | lock_mask) & unprotect_mask);
179if (result) {
180msg_cerr("spi_write_status_register failed.\n");
181return result;
182}
183status = spi_read_status_register(flash);
184if ((status & bp_mask) != 0) {
185msg_cerr("Block protection could not be disabled!\n");
186flash->chip->printlock(flash);
187return 1;
188}
189msg_cdbg("disabled.\n");
190return 0;
191}
192
193/* A common block protection disable that tries to unset the status register bits masked by 0x3C. */
194int spi_disable_blockprotect(struct flashctx *flash)
195{
196return spi_disable_blockprotect_generic(flash, 0x3C, 0, 0, 0xFF);
197}
198
199/* A common block protection disable that tries to unset the status register bits masked by 0x0C (BP0-1) and
200 * protected/locked by bit #7. Useful when bits 4-5 may be non-0). */
201int spi_disable_blockprotect_bp1_srwd(struct flashctx *flash)
202{
203return spi_disable_blockprotect_generic(flash, 0x0C, 1 << 7, 0, 0xFF);
204}
205
206/* A common block protection disable that tries to unset the status register bits masked by 0x1C (BP0-2) and
207 * protected/locked by bit #7. Useful when bit #5 is neither a protection bit nor reserved (and hence possibly
208 * non-0). */
209int spi_disable_blockprotect_bp2_srwd(struct flashctx *flash)
210{
211return spi_disable_blockprotect_generic(flash, 0x1C, 1 << 7, 0, 0xFF);
212}
213
214/* A common block protection disable that tries to unset the status register bits masked by 0x3C (BP0-3) and
215 * protected/locked by bit #7. */
216int spi_disable_blockprotect_bp3_srwd(struct flashctx *flash)
217{
218return spi_disable_blockprotect_generic(flash, 0x3C, 1 << 7, 0, 0xFF);
219}
220
221/* A common block protection disable that tries to unset the status register bits masked by 0x7C (BP0-4) and
222 * protected/locked by bit #7. */
223int spi_disable_blockprotect_bp4_srwd(struct flashctx *flash)
224{
225return spi_disable_blockprotect_generic(flash, 0x7C, 1 << 7, 0, 0xFF);
226}
227
228static void spi_prettyprint_status_register_hex(uint8_t status)
229{
230msg_cdbg("Chip status register is 0x%02x.\n", status);
231}
232
233/* Common highest bit: Status Register Write Disable (SRWD) or Status Register Protect (SRP). */
234static void spi_prettyprint_status_register_srwd(uint8_t status)
235{
236msg_cdbg("Chip status register: Status Register Write Disable (SRWD, SRP, ...) is %sset\n",
237 (status & (1 << 7)) ? "" : "not ");
238}
239
240/* Common highest bit: Block Protect Write Disable (BPL). */
241static void spi_prettyprint_status_register_bpl(uint8_t status)
242{
243msg_cdbg("Chip status register: Block Protect Write Disable (BPL) is %sset\n",
244 (status & (1 << 7)) ? "" : "not ");
245}
246
247/* Common lowest 2 bits: WEL and WIP. */
248static void spi_prettyprint_status_register_welwip(uint8_t status)
249{
250msg_cdbg("Chip status register: Write Enable Latch (WEL) is %sset\n",
251 (status & (1 << 1)) ? "" : "not ");
252msg_cdbg("Chip status register: Write In Progress (WIP/BUSY) is %sset\n",
253 (status & (1 << 0)) ? "" : "not ");
254}
255
256/* Common block protection (BP) bits. */
257static void spi_prettyprint_status_register_bp(uint8_t status, int bp)
258{
259switch (bp) {
260/* Fall through. */
261case 4:
262msg_cdbg("Chip status register: Block Protect 4 (BP4) is %sset\n",
263 (status & (1 << 6)) ? "" : "not ");
264case 3:
265msg_cdbg("Chip status register: Block Protect 3 (BP3) is %sset\n",
266 (status & (1 << 5)) ? "" : "not ");
267case 2:
268msg_cdbg("Chip status register: Block Protect 2 (BP2) is %sset\n",
269 (status & (1 << 4)) ? "" : "not ");
270case 1:
271msg_cdbg("Chip status register: Block Protect 1 (BP1) is %sset\n",
272 (status & (1 << 3)) ? "" : "not ");
273case 0:
274msg_cdbg("Chip status register: Block Protect 0 (BP0) is %sset\n",
275 (status & (1 << 2)) ? "" : "not ");
276}
277}
278
279/* Unnamed bits. */
280void spi_prettyprint_status_register_bit(uint8_t status, int bit)
281{
282msg_cdbg("Chip status register: Bit %i is %sset\n", bit, (status & (1 << bit)) ? "" : "not ");
283}
284
285int spi_prettyprint_status_register_plain(struct flashctx *flash)
286{
287uint8_t status = spi_read_status_register(flash);
288spi_prettyprint_status_register_hex(status);
289return 0;
290}
291
292/* Print the plain hex value and the welwip bits only. */
293int spi_prettyprint_status_register_default_welwip(struct flashctx *flash)
294{
295uint8_t status = spi_read_status_register(flash);
296spi_prettyprint_status_register_hex(status);
297
298spi_prettyprint_status_register_welwip(status);
299return 0;
300}
301
302/* Works for many chips of the
303 * AMIC A25L series
304 * and MX MX25L512
305 */
306int spi_prettyprint_status_register_bp1_srwd(struct flashctx *flash)
307{
308uint8_t status = spi_read_status_register(flash);
309spi_prettyprint_status_register_hex(status);
310
311spi_prettyprint_status_register_srwd(status);
312spi_prettyprint_status_register_bit(status, 6);
313spi_prettyprint_status_register_bit(status, 5);
314spi_prettyprint_status_register_bit(status, 4);
315spi_prettyprint_status_register_bp(status, 1);
316spi_prettyprint_status_register_welwip(status);
317return 0;
318}
319
320/* Works for many chips of the
321 * AMIC A25L series
322 * PMC Pm25LD series
323 */
324int spi_prettyprint_status_register_bp2_srwd(struct flashctx *flash)
325{
326uint8_t status = spi_read_status_register(flash);
327spi_prettyprint_status_register_hex(status);
328
329spi_prettyprint_status_register_srwd(status);
330spi_prettyprint_status_register_bit(status, 6);
331spi_prettyprint_status_register_bit(status, 5);
332spi_prettyprint_status_register_bp(status, 2);
333spi_prettyprint_status_register_welwip(status);
334return 0;
335}
336
337/* Works for many chips of the
338 * ST M25P series
339 * MX MX25L series
340 */
341int spi_prettyprint_status_register_bp3_srwd(struct flashctx *flash)
342{
343uint8_t status = spi_read_status_register(flash);
344spi_prettyprint_status_register_hex(status);
345
346spi_prettyprint_status_register_srwd(status);
347spi_prettyprint_status_register_bit(status, 6);
348spi_prettyprint_status_register_bp(status, 3);
349spi_prettyprint_status_register_welwip(status);
350return 0;
351}
352
353int spi_prettyprint_status_register_bp4_srwd(struct flashctx *flash)
354{
355uint8_t status = spi_read_status_register(flash);
356spi_prettyprint_status_register_hex(status);
357
358spi_prettyprint_status_register_srwd(status);
359spi_prettyprint_status_register_bp(status, 4);
360spi_prettyprint_status_register_welwip(status);
361return 0;
362}
363
364int spi_prettyprint_status_register_bp2_bpl(struct flashctx *flash)
365{
366uint8_t status = spi_read_status_register(flash);
367spi_prettyprint_status_register_hex(status);
368
369spi_prettyprint_status_register_bpl(status);
370spi_prettyprint_status_register_bit(status, 6);
371spi_prettyprint_status_register_bit(status, 5);
372spi_prettyprint_status_register_bp(status, 2);
373spi_prettyprint_status_register_welwip(status);
374return 0;
375}
376
377int spi_prettyprint_status_register_bp2_tb_bpl(struct flashctx *flash)
378{
379uint8_t status = spi_read_status_register(flash);
380spi_prettyprint_status_register_hex(status);
381
382spi_prettyprint_status_register_bpl(status);
383spi_prettyprint_status_register_bit(status, 6);
384msg_cdbg("Chip status register: Top/Bottom (TB) is %s\n", (status & (1 << 5)) ? "bottom" : "top");
385spi_prettyprint_status_register_bp(status, 2);
386spi_prettyprint_status_register_welwip(status);
387return 0;
388}
389
390/* === Amic ===
391 * FIXME: spi_disable_blockprotect is incorrect but works fine for chips using
392 * spi_prettyprint_status_register_bp1_srwd or
393 * spi_prettyprint_status_register_bp2_srwd.
394 * FIXME: spi_disable_blockprotect is incorrect and will fail for chips using
395 * spi_prettyprint_status_register_amic_a25l032 if those have locks controlled
396 * by the second status register.
397 */
398
399int spi_prettyprint_status_register_amic_a25l032(struct flashctx *flash)
400{
401uint8_t status = spi_read_status_register(flash);
402spi_prettyprint_status_register_hex(status);
403
404spi_prettyprint_status_register_srwd(status);
405msg_cdbg("Chip status register: Sector Protect Size (SEC) is %i KB\n", (status & (1 << 6)) ? 4 : 64);
406msg_cdbg("Chip status register: Top/Bottom (TB) is %s\n", (status & (1 << 5)) ? "bottom" : "top");
407spi_prettyprint_status_register_bp(status, 2);
408spi_prettyprint_status_register_welwip(status);
409msg_cdbg("Chip status register 2 is NOT decoded!\n");
410return 0;
411}
412
413/* === Atmel === */
414
415static void spi_prettyprint_status_register_atmel_at25_wpen(uint8_t status)
416{
417msg_cdbg("Chip status register: Write Protect Enable (WPEN) is %sset\n",
418 (status & (1 << 7)) ? "" : "not ");
419}
420
421static void spi_prettyprint_status_register_atmel_at25_srpl(uint8_t status)
422{
423msg_cdbg("Chip status register: Sector Protection Register Lock (SRPL) is %sset\n",
424 (status & (1 << 7)) ? "" : "not ");
425}
426
427static void spi_prettyprint_status_register_atmel_at25_epewpp(uint8_t status)
428{
429msg_cdbg("Chip status register: Erase/Program Error (EPE) is %sset\n",
430 (status & (1 << 5)) ? "" : "not ");
431msg_cdbg("Chip status register: WP# pin (WPP) is %sasserted\n",
432 (status & (1 << 4)) ? "not " : "");
433}
434
435static void spi_prettyprint_status_register_atmel_at25_swp(uint8_t status)
436{
437msg_cdbg("Chip status register: Software Protection Status (SWP): ");
438switch (status & (3 << 2)) {
439case 0x0 << 2:
440msg_cdbg("no sectors are protected\n");
441break;
442case 0x1 << 2:
443msg_cdbg("some sectors are protected\n");
444/* FIXME: Read individual Sector Protection Registers. */
445break;
446case 0x3 << 2:
447msg_cdbg("all sectors are protected\n");
448break;
449default:
450msg_cdbg("reserved for future use\n");
451break;
452}
453}
454
455int spi_prettyprint_status_register_at25df(struct flashctx *flash)
456{
457uint8_t status = spi_read_status_register(flash);
458spi_prettyprint_status_register_hex(status);
459
460spi_prettyprint_status_register_atmel_at25_srpl(status);
461spi_prettyprint_status_register_bit(status, 6);
462spi_prettyprint_status_register_atmel_at25_epewpp(status);
463spi_prettyprint_status_register_atmel_at25_swp(status);
464spi_prettyprint_status_register_welwip(status);
465return 0;
466}
467
468int spi_prettyprint_status_register_at25df_sec(struct flashctx *flash)
469{
470/* FIXME: We should check the security lockdown. */
471msg_cdbg("Ignoring security lockdown (if present)\n");
472msg_cdbg("Ignoring status register byte 2\n");
473return spi_prettyprint_status_register_at25df(flash);
474}
475
476/* used for AT25F512, AT25F1024(A), AT25F2048 */
477int spi_prettyprint_status_register_at25f(struct flashctx *flash)
478{
479uint8_t status;
480
481status = spi_read_status_register(flash);
482spi_prettyprint_status_register_hex(status);
483
484spi_prettyprint_status_register_atmel_at25_wpen(status);
485spi_prettyprint_status_register_bit(status, 6);
486spi_prettyprint_status_register_bit(status, 5);
487spi_prettyprint_status_register_bit(status, 4);
488spi_prettyprint_status_register_bp(status, 1);
489spi_prettyprint_status_register_welwip(status);
490return 0;
491}
492
493int spi_prettyprint_status_register_at25f512a(struct flashctx *flash)
494{
495uint8_t status;
496
497status = spi_read_status_register(flash);
498spi_prettyprint_status_register_hex(status);
499
500spi_prettyprint_status_register_atmel_at25_wpen(status);
501spi_prettyprint_status_register_bit(status, 6);
502spi_prettyprint_status_register_bit(status, 5);
503spi_prettyprint_status_register_bit(status, 4);
504spi_prettyprint_status_register_bit(status, 3);
505spi_prettyprint_status_register_bp(status, 0);
506spi_prettyprint_status_register_welwip(status);
507return 0;
508}
509
510int spi_prettyprint_status_register_at25f512b(struct flashctx *flash)
511{
512uint8_t status = spi_read_status_register(flash);
513spi_prettyprint_status_register_hex(status);
514
515spi_prettyprint_status_register_atmel_at25_srpl(status);
516spi_prettyprint_status_register_bit(status, 6);
517spi_prettyprint_status_register_atmel_at25_epewpp(status);
518spi_prettyprint_status_register_bit(status, 3);
519spi_prettyprint_status_register_bp(status, 0);
520spi_prettyprint_status_register_welwip(status);
521return 0;
522}
523
524int spi_prettyprint_status_register_at25f4096(struct flashctx *flash)
525{
526uint8_t status;
527
528status = spi_read_status_register(flash);
529spi_prettyprint_status_register_hex(status);
530
531spi_prettyprint_status_register_atmel_at25_wpen(status);
532spi_prettyprint_status_register_bit(status, 6);
533spi_prettyprint_status_register_bit(status, 5);
534spi_prettyprint_status_register_bp(status, 2);
535spi_prettyprint_status_register_welwip(status);
536return 0;
537}
538
539int spi_prettyprint_status_register_at25fs010(struct flashctx *flash)
540{
541uint8_t status = spi_read_status_register(flash);
542spi_prettyprint_status_register_hex(status);
543
544spi_prettyprint_status_register_atmel_at25_wpen(status);
545msg_cdbg("Chip status register: Bit 6 / Block Protect 4 (BP4) is "
546 "%sset\n", (status & (1 << 6)) ? "" : "not ");
547msg_cdbg("Chip status register: Bit 5 / Block Protect 3 (BP3) is "
548 "%sset\n", (status & (1 << 5)) ? "" : "not ");
549spi_prettyprint_status_register_bit(status, 4);
550msg_cdbg("Chip status register: Bit 3 / Block Protect 1 (BP1) is "
551 "%sset\n", (status & (1 << 3)) ? "" : "not ");
552msg_cdbg("Chip status register: Bit 2 / Block Protect 0 (BP0) is "
553 "%sset\n", (status & (1 << 2)) ? "" : "not ");
554/* FIXME: Pretty-print detailed sector protection status. */
555spi_prettyprint_status_register_welwip(status);
556return 0;
557}
558
559int spi_prettyprint_status_register_at25fs040(struct flashctx *flash)
560{
561uint8_t status = spi_read_status_register(flash);
562spi_prettyprint_status_register_hex(status);
563
564spi_prettyprint_status_register_atmel_at25_wpen(status);
565spi_prettyprint_status_register_bp(status, 4);
566/* FIXME: Pretty-print detailed sector protection status. */
567spi_prettyprint_status_register_welwip(status);
568return 0;
569}
570
571int spi_prettyprint_status_register_at26df081a(struct flashctx *flash)
572{
573uint8_t status = spi_read_status_register(flash);
574spi_prettyprint_status_register_hex(status);
575
576spi_prettyprint_status_register_atmel_at25_srpl(status);
577msg_cdbg("Chip status register: Sequential Program Mode Status (SPM) is %sset\n",
578 (status & (1 << 6)) ? "" : "not ");
579spi_prettyprint_status_register_atmel_at25_epewpp(status);
580spi_prettyprint_status_register_atmel_at25_swp(status);
581spi_prettyprint_status_register_welwip(status);
582return 0;
583}
584
585/* Some Atmel DataFlash chips support per sector protection bits and the write protection bits in the status
586 * register do indicate if none, some or all sectors are protected. It is possible to globally (un)lock all
587 * sectors at once by writing 0 not only the protection bits (2 and 3) but also completely unrelated bits (4 and
588 * 5) which normally are not touched.
589 * Affected are all known Atmel chips matched by AT2[56]D[FLQ]..1A? but the AT26DF041. */
590int spi_disable_blockprotect_at2x_global_unprotect(struct flashctx *flash)
591{
592return spi_disable_blockprotect_generic(flash, 0x0C, 1 << 7, 1 << 4, 0x00);
593}
594
595int spi_disable_blockprotect_at2x_global_unprotect_sec(struct flashctx *flash)
596{
597/* FIXME: We should check the security lockdown. */
598msg_cinfo("Ignoring security lockdown (if present)\n");
599return spi_disable_blockprotect_at2x_global_unprotect(flash);
600}
601
602int spi_disable_blockprotect_at25f(struct flashctx *flash)
603{
604return spi_disable_blockprotect_generic(flash, 0x0C, 1 << 7, 0, 0xFF);
605}
606
607int spi_disable_blockprotect_at25f512a(struct flashctx *flash)
608{
609return spi_disable_blockprotect_generic(flash, 0x04, 1 << 7, 0, 0xFF);
610}
611
612int spi_disable_blockprotect_at25f512b(struct flashctx *flash)
613{
614return spi_disable_blockprotect_generic(flash, 0x04, 1 << 7, 1 << 4, 0xFF);
615}
616
617int spi_disable_blockprotect_at25fs010(struct flashctx *flash)
618{
619return spi_disable_blockprotect_generic(flash, 0x6C, 1 << 7, 0, 0xFF);
620 }
621
622int spi_disable_blockprotect_at25fs040(struct flashctx *flash)
623{
624return spi_disable_blockprotect_generic(flash, 0x7C, 1 << 7, 0, 0xFF);
625}
626
627/* === Eon === */
628
629int spi_prettyprint_status_register_en25s_wp(struct flashctx *flash)
630{
631uint8_t status = spi_read_status_register(flash);
632spi_prettyprint_status_register_hex(status);
633
634spi_prettyprint_status_register_srwd(status);
635msg_cdbg("Chip status register: WP# disable (WPDIS) is %sabled\n", (status & (1 << 6)) ? "en " : "dis");
636spi_prettyprint_status_register_bp(status, 3);
637spi_prettyprint_status_register_welwip(status);
638return 0;
639}
640
641/* === Intel/Numonyx/Micron - Spansion === */
642
643int spi_disable_blockprotect_n25q(struct flashctx *flash)
644{
645return spi_disable_blockprotect_generic(flash, 0x5C, 1 << 7, 0, 0xFF);
646}
647
648int spi_prettyprint_status_register_n25q(struct flashctx *flash)
649{
650uint8_t status = spi_read_status_register(flash);
651spi_prettyprint_status_register_hex(status);
652
653spi_prettyprint_status_register_srwd(status);
654if (flash->chip->total_size <= 32 / 8 * 1024) /* N25Q16 and N25Q32: reserved */
655spi_prettyprint_status_register_bit(status, 6);
656else
657msg_cdbg("Chip status register: Block Protect 3 (BP3) is %sset\n",
658 (status & (1 << 6)) ? "" : "not ");
659msg_cdbg("Chip status register: Top/Bottom (TB) is %s\n", (status & (1 << 5)) ? "bottom" : "top");
660spi_prettyprint_status_register_bp(status, 2);
661spi_prettyprint_status_register_welwip(status);
662return 0;
663}
664
665/* Used by Intel/Numonyx S33 and Spansion S25FL-S chips */
666/* TODO: Clear P_FAIL and E_FAIL with Clear SR Fail Flags Command (30h) here? */
667int spi_disable_blockprotect_bp2_ep_srwd(struct flashctx *flash)
668{
669return spi_disable_blockprotect_bp2_srwd(flash);
670}
671
672/* Used by Intel/Numonyx S33 and Spansion S25FL-S chips */
673int spi_prettyprint_status_register_bp2_ep_srwd(struct flashctx *flash)
674{
675uint8_t status = spi_read_status_register(flash);
676spi_prettyprint_status_register_hex(status);
677
678spi_prettyprint_status_register_srwd(status);
679msg_cdbg("Chip status register: Program Fail Flag (P_FAIL) is %sset\n",
680 (status & (1 << 6)) ? "" : "not ");
681msg_cdbg("Chip status register: Erase Fail Flag (E_FAIL) is %sset\n",
682 (status & (1 << 5)) ? "" : "not ");
683spi_prettyprint_status_register_bp(status, 2);
684spi_prettyprint_status_register_welwip(status);
685return 0;
686}
687
688/* === SST === */
689
690static void spi_prettyprint_status_register_sst25_common(uint8_t status)
691{
692spi_prettyprint_status_register_hex(status);
693
694spi_prettyprint_status_register_bpl(status);
695msg_cdbg("Chip status register: Auto Address Increment Programming (AAI) is %sset\n",
696 (status & (1 << 6)) ? "" : "not ");
697spi_prettyprint_status_register_bp(status, 3);
698spi_prettyprint_status_register_welwip(status);
699}
700
701int spi_prettyprint_status_register_sst25(struct flashctx *flash)
702{
703uint8_t status = spi_read_status_register(flash);
704spi_prettyprint_status_register_sst25_common(status);
705return 0;
706}
707
708int spi_prettyprint_status_register_sst25vf016(struct flashctx *flash)
709{
710static const char *const bpt[] = {
711"none",
712"1F0000H-1FFFFFH",
713"1E0000H-1FFFFFH",
714"1C0000H-1FFFFFH",
715"180000H-1FFFFFH",
716"100000H-1FFFFFH",
717"all", "all"
718};
719uint8_t status = spi_read_status_register(flash);
720spi_prettyprint_status_register_sst25_common(status);
721msg_cdbg("Resulting block protection : %s\n", bpt[(status & 0x1c) >> 2]);
722return 0;
723}
724
725int spi_prettyprint_status_register_sst25vf040b(struct flashctx *flash)
726{
727static const char *const bpt[] = {
728"none",
729"0x70000-0x7ffff",
730"0x60000-0x7ffff",
731"0x40000-0x7ffff",
732"all blocks", "all blocks", "all blocks", "all blocks"
733};
734uint8_t status = spi_read_status_register(flash);
735spi_prettyprint_status_register_sst25_common(status);
736msg_cdbg("Resulting block protection : %s\n", bpt[(status & 0x1c) >> 2]);
737return 0;
738}

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