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1/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2007, 2008 Carl-Daniel Hailfinger
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 */
19
20#ifndef __SPI_H__
21#define __SPI_H__ 1
22
23/*
24 * Contains the generic SPI headers
25 */
26
27/* Read Electronic ID */
28#define JEDEC_RDID0x9f
29#define JEDEC_RDID_OUTSIZE0x01
30/* INSIZE may be 0x04 for some chips*/
31#define JEDEC_RDID_INSIZE0x03
32
33/* Some Atmel AT25F* models have bit 3 as don't care bit in commands */
34#define AT25F_RDID0x15/* 0x15 or 0x1d */
35#define AT25F_RDID_OUTSIZE0x01
36#define AT25F_RDID_INSIZE0x02
37
38/* Read Electronic Manufacturer Signature */
39#define JEDEC_REMS0x90
40#define JEDEC_REMS_OUTSIZE0x04
41#define JEDEC_REMS_INSIZE0x02
42
43/* Read Serial Flash Discoverable Parameters (SFDP) */
44#define JEDEC_SFDP0x5a
45#define JEDEC_SFDP_OUTSIZE0x05/* 8b op, 24b addr, 8b dummy */
46/* JEDEC_SFDP_INSIZE : any length */
47
48/* Read Electronic Signature */
49#define JEDEC_RES0xab
50#define JEDEC_RES_OUTSIZE0x04
51/* INSIZE may be 0x02 for some chips*/
52#define JEDEC_RES_INSIZE0x01
53
54/* Write Enable */
55#define JEDEC_WREN0x06
56#define JEDEC_WREN_OUTSIZE0x01
57#define JEDEC_WREN_INSIZE0x00
58
59/* Write Disable */
60#define JEDEC_WRDI0x04
61#define JEDEC_WRDI_OUTSIZE0x01
62#define JEDEC_WRDI_INSIZE0x00
63
64/* Chip Erase 0x60 is supported by Macronix/SST chips. */
65#define JEDEC_CE_600x60
66#define JEDEC_CE_60_OUTSIZE0x01
67#define JEDEC_CE_60_INSIZE0x00
68
69/* Chip Erase 0x62 is supported by Atmel AT25F chips. */
70#define JEDEC_CE_620x62
71#define JEDEC_CE_62_OUTSIZE0x01
72#define JEDEC_CE_62_INSIZE0x00
73
74/* Chip Erase 0xc7 is supported by SST/ST/EON/Macronix chips. */
75#define JEDEC_CE_C70xc7
76#define JEDEC_CE_C7_OUTSIZE0x01
77#define JEDEC_CE_C7_INSIZE0x00
78
79/* Block Erase 0x50 is supported by Atmel AT26DF chips. */
80#define JEDEC_BE_500x50
81#define JEDEC_BE_50_OUTSIZE0x04
82#define JEDEC_BE_50_INSIZE0x00
83
84/* Block Erase 0x52 is supported by SST and old Atmel chips. */
85#define JEDEC_BE_520x52
86#define JEDEC_BE_52_OUTSIZE0x04
87#define JEDEC_BE_52_INSIZE0x00
88
89/* Block Erase 0x81 is supported by Atmel AT26DF chips. */
90#define JEDEC_BE_810x81
91#define JEDEC_BE_81_OUTSIZE0x04
92#define JEDEC_BE_81_INSIZE0x00
93
94/* Block Erase 0xc4 is supported by Micron chips. */
95#define JEDEC_BE_C40xc4
96#define JEDEC_BE_C4_OUTSIZE0x04
97#define JEDEC_BE_C4_INSIZE0x00
98
99/* Block Erase 0xd8 is supported by EON/Macronix chips. */
100#define JEDEC_BE_D80xd8
101#define JEDEC_BE_D8_OUTSIZE0x04
102#define JEDEC_BE_D8_INSIZE0x00
103
104/* Block Erase 0xd7 is supported by PMC chips. */
105#define JEDEC_BE_D70xd7
106#define JEDEC_BE_D7_OUTSIZE0x04
107#define JEDEC_BE_D7_INSIZE0x00
108
109/* Sector Erase 0x20 is supported by Macronix/SST chips. */
110#define JEDEC_SE0x20
111#define JEDEC_SE_OUTSIZE0x04
112#define JEDEC_SE_INSIZE0x00
113
114/* Page Erase 0xDB */
115#define JEDEC_PE0xDB
116#define JEDEC_PE_OUTSIZE0x04
117#define JEDEC_PE_INSIZE0x00
118
119/* Read Status Register */
120#define JEDEC_RDSR0x05
121#define JEDEC_RDSR_OUTSIZE0x01
122#define JEDEC_RDSR_INSIZE0x01
123
124/* Status Register Bits */
125#define SPI_SR_WIP(0x01 << 0)
126#define SPI_SR_WEL(0x01 << 1)
127#define SPI_SR_AAI(0x01 << 6)
128
129/* Write Status Enable */
130#define JEDEC_EWSR0x50
131#define JEDEC_EWSR_OUTSIZE0x01
132#define JEDEC_EWSR_INSIZE0x00
133
134/* Write Status Register */
135#define JEDEC_WRSR0x01
136#define JEDEC_WRSR_OUTSIZE0x02
137#define JEDEC_WRSR_INSIZE0x00
138
139/* Read the memory */
140#define JEDEC_READ0x03
141#define JEDEC_READ_OUTSIZE0x04
142/* JEDEC_READ_INSIZE : any length */
143
144/* Write memory byte */
145#define JEDEC_BYTE_PROGRAM0x02
146#define JEDEC_BYTE_PROGRAM_OUTSIZE0x05
147#define JEDEC_BYTE_PROGRAM_INSIZE0x00
148
149/* Write AAI word (SST25VF080B) */
150#define JEDEC_AAI_WORD_PROGRAM0xad
151#define JEDEC_AAI_WORD_PROGRAM_OUTSIZE0x06
152#define JEDEC_AAI_WORD_PROGRAM_CONT_OUTSIZE0x03
153#define JEDEC_AAI_WORD_PROGRAM_INSIZE0x00
154
155/* Error codes */
156#define SPI_GENERIC_ERROR-1
157#define SPI_INVALID_OPCODE-2
158#define SPI_INVALID_ADDRESS-3
159#define SPI_INVALID_LENGTH-4
160#define SPI_FLASHROM_BUG-5
161#define SPI_PROGRAMMER_ERROR-6
162
163#endif/* !__SPI_H__ */

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