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Root/trunk/spi.c

1/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2007, 2008, 2009, 2010, 2011 Carl-Daniel Hailfinger
5 * Copyright (C) 2008 coresystems GmbH
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21/*
22 * Contains the generic SPI framework
23 */
24
25#include <strings.h>
26#include <string.h>
27#include "flash.h"
28#include "flashchips.h"
29#include "chipdrivers.h"
30#include "programmer.h"
31#include "spi.h"
32
33int spi_send_command(struct flashctx *flash, unsigned int writecnt,
34 unsigned int readcnt, const unsigned char *writearr,
35 unsigned char *readarr)
36{
37return flash->mst->spi.command(flash, writecnt, readcnt, writearr,
38 readarr);
39}
40
41int spi_send_multicommand(struct flashctx *flash, struct spi_command *cmds)
42{
43return flash->mst->spi.multicommand(flash, cmds);
44}
45
46int default_spi_send_command(struct flashctx *flash, unsigned int writecnt,
47 unsigned int readcnt,
48 const unsigned char *writearr,
49 unsigned char *readarr)
50{
51struct spi_command cmd[] = {
52{
53.writecnt = writecnt,
54.readcnt = readcnt,
55.writearr = writearr,
56.readarr = readarr,
57}, {
58.writecnt = 0,
59.writearr = NULL,
60.readcnt = 0,
61.readarr = NULL,
62}};
63
64return spi_send_multicommand(flash, cmd);
65}
66
67int default_spi_send_multicommand(struct flashctx *flash,
68 struct spi_command *cmds)
69{
70int result = 0;
71for (; (cmds->writecnt || cmds->readcnt) && !result; cmds++) {
72result = spi_send_command(flash, cmds->writecnt, cmds->readcnt,
73 cmds->writearr, cmds->readarr);
74}
75return result;
76}
77
78int default_spi_read(struct flashctx *flash, uint8_t *buf, unsigned int start,
79 unsigned int len)
80{
81unsigned int max_data = flash->mst->spi.max_data_read;
82if (max_data == MAX_DATA_UNSPECIFIED) {
83msg_perr("%s called, but SPI read chunk size not defined "
84 "on this hardware. Please report a bug at "
85 "flashrom@flashrom.org\n", __func__);
86return 1;
87}
88return spi_read_chunked(flash, buf, start, len, max_data);
89}
90
91int default_spi_write_256(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len)
92{
93unsigned int max_data = flash->mst->spi.max_data_write;
94if (max_data == MAX_DATA_UNSPECIFIED) {
95msg_perr("%s called, but SPI write chunk size not defined "
96 "on this hardware. Please report a bug at "
97 "flashrom@flashrom.org\n", __func__);
98return 1;
99}
100return spi_write_chunked(flash, buf, start, len, max_data);
101}
102
103int spi_chip_read(struct flashctx *flash, uint8_t *buf, unsigned int start,
104 unsigned int len)
105{
106unsigned int addrbase = 0;
107
108/* Check if the chip fits between lowest valid and highest possible
109 * address. Highest possible address with the current SPI implementation
110 * means 0xffffff, the highest unsigned 24bit number.
111 */
112addrbase = spi_get_valid_read_addr(flash);
113if (addrbase + flash->chip->total_size * 1024 > (1 << 24)) {
114msg_perr("Flash chip size exceeds the allowed access window. ");
115msg_perr("Read will probably fail.\n");
116/* Try to get the best alignment subject to constraints. */
117addrbase = (1 << 24) - flash->chip->total_size * 1024;
118}
119/* Check if alignment is native (at least the largest power of two which
120 * is a factor of the mapped size of the chip).
121 */
122if (ffs(flash->chip->total_size * 1024) > (ffs(addrbase) ? : 33)) {
123msg_perr("Flash chip is not aligned natively in the allowed "
124 "access window.\n");
125msg_perr("Read will probably return garbage.\n");
126}
127return flash->mst->spi.read(flash, buf, addrbase + start, len);
128}
129
130/*
131 * Program chip using page (256 bytes) programming.
132 * Some SPI masters can't do this, they use single byte programming instead.
133 * The redirect to single byte programming is achieved by setting
134 * .write_256 = spi_chip_write_1
135 */
136/* real chunksize is up to 256, logical chunksize is 256 */
137int spi_chip_write_256(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len)
138{
139return flash->mst->spi.write_256(flash, buf, start, len);
140}
141
142/*
143 * Get the lowest allowed address for read accesses. This often happens to
144 * be the lowest allowed address for all commands which take an address.
145 * This is a master limitation.
146 */
147uint32_t spi_get_valid_read_addr(struct flashctx *flash)
148{
149switch (flash->mst->spi.type) {
150#if CONFIG_INTERNAL == 1
151#if defined(__i386__) || defined(__x86_64__)
152case SPI_CONTROLLER_ICH7:
153case SPI_CONTROLLER_ICH9:
154/* Return BBAR for ICH chipsets. */
155return ichspi_bbar;
156#endif
157#endif
158default:
159return 0;
160}
161}
162
163int spi_aai_write(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len)
164{
165return flash->mst->spi.write_aai(flash, buf, start, len);
166}
167
168int register_spi_master(const struct spi_master *mst)
169{
170struct registered_master rmst;
171
172if (!mst->write_aai || !mst->write_256 || !mst->read || !mst->command ||
173 !mst->multicommand ||
174 ((mst->command == default_spi_send_command) &&
175 (mst->multicommand == default_spi_send_multicommand))) {
176msg_perr("%s called with incomplete master definition. "
177 "Please report a bug at flashrom@flashrom.org\n",
178 __func__);
179return ERROR_FLASHROM_BUG;
180}
181
182
183rmst.buses_supported = BUS_SPI;
184rmst.spi = *mst;
185return register_master(&rmst);
186}

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