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1/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2010,2011 Carl-Daniel Hailfinger
5 * Written by Carl-Daniel Hailfinger for Angelbird Ltd.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21/* Datasheets are not public (yet?) */
22#if defined(__i386__) || defined(__x86_64__)
23
24#include <stdlib.h>
25#include "flash.h"
26#include "programmer.h"
27#include "hwaccess.h"
28
29uint8_t *mv_bar;
30uint16_t mv_iobar;
31
32const struct dev_entry satas_mv[] = {
33/* 88SX6041 and 88SX6042 are the same according to the datasheet. */
34{0x11ab, 0x7042, OK, "Marvell", "88SX7042 PCI-e 4-port SATA-II"},
35
36{0},
37};
38
39#define NVRAM_PARAM0x1045c
40#define FLASH_PARAM0x1046c
41#define EXPANSION_ROM_BAR_CONTROL0x00d2c
42#define PCI_BAR2_CONTROL0x00c08
43#define GPIO_PORT_CONTROL0x104f0
44
45static void satamv_chip_writeb(const struct flashctx *flash, uint8_t val,
46 chipaddr addr);
47static uint8_t satamv_chip_readb(const struct flashctx *flash,
48 const chipaddr addr);
49static const struct par_master par_master_satamv = {
50.chip_readb= satamv_chip_readb,
51.chip_readw= fallback_chip_readw,
52.chip_readl= fallback_chip_readl,
53.chip_readn= fallback_chip_readn,
54.chip_writeb= satamv_chip_writeb,
55.chip_writew= fallback_chip_writew,
56.chip_writel= fallback_chip_writel,
57.chip_writen= fallback_chip_writen,
58};
59
60/*
61 * Random notes:
62 * FCE#Flash Chip Enable
63 * FWE#Flash Write Enable
64 * FOE#Flash Output Enable
65 * FALE[1:0]Flash Address Latch Enable
66 * FAD[7:0]Flash Multiplexed Address/Data Bus
67 * FA[2:0]Flash Address Low
68 *
69 * GPIO[15,2]GPIO Port Mode
70 * GPIO[4:3]Flash Size
71 *
72 * 0xd2cExpansion ROM BAR Control
73 * 0xc08PCI BAR2 (Flash/NVRAM) Control
74 * 0x1046cFlash Parameters
75 */
76int satamv_init(void)
77{
78struct pci_dev *dev = NULL;
79uintptr_t addr;
80uint32_t tmp;
81
82if (rget_io_perms())
83return 1;
84
85/* BAR0 has all internal registers memory mapped. */
86dev = pcidev_init(satas_mv, PCI_BASE_ADDRESS_0);
87if (!dev)
88return 1;
89
90addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0);
91if (!addr)
92return 1;
93
94mv_bar = rphysmap("Marvell 88SX7042 registers", addr, 0x20000);
95if (mv_bar == ERROR_PTR)
96return 1;
97
98tmp = pci_mmio_readl(mv_bar + FLASH_PARAM);
99msg_pspew("Flash Parameters:\n");
100msg_pspew("TurnOff=0x%01x\n", (tmp >> 0) & 0x7);
101msg_pspew("Acc2First=0x%01x\n", (tmp >> 3) & 0xf);
102msg_pspew("Acc2Next=0x%01x\n", (tmp >> 7) & 0xf);
103msg_pspew("ALE2Wr=0x%01x\n", (tmp >> 11) & 0x7);
104msg_pspew("WrLow=0x%01x\n", (tmp >> 14) & 0x7);
105msg_pspew("WrHigh=0x%01x\n", (tmp >> 17) & 0x7);
106msg_pspew("Reserved[21:20]=0x%01x\n", (tmp >> 20) & 0x3);
107msg_pspew("TurnOffExt=0x%01x\n", (tmp >> 22) & 0x1);
108msg_pspew("Acc2FirstExt=0x%01x\n", (tmp >> 23) & 0x1);
109msg_pspew("Acc2NextExt=0x%01x\n", (tmp >> 24) & 0x1);
110msg_pspew("ALE2WrExt=0x%01x\n", (tmp >> 25) & 0x1);
111msg_pspew("WrLowExt=0x%01x\n", (tmp >> 26) & 0x1);
112msg_pspew("WrHighExt=0x%01x\n", (tmp >> 27) & 0x1);
113msg_pspew("Reserved[31:28]=0x%01x\n", (tmp >> 28) & 0xf);
114
115tmp = pci_mmio_readl(mv_bar + EXPANSION_ROM_BAR_CONTROL);
116msg_pspew("Expansion ROM BAR Control:\n");
117msg_pspew("ExpROMSz=0x%01x\n", (tmp >> 19) & 0x7);
118
119/* Enable BAR2 mapping to flash */
120tmp = pci_mmio_readl(mv_bar + PCI_BAR2_CONTROL);
121msg_pspew("PCI BAR2 (Flash/NVRAM) Control:\n");
122msg_pspew("Bar2En=0x%01x\n", (tmp >> 0) & 0x1);
123msg_pspew("BAR2TransAttr=0x%01x\n", (tmp >> 1) & 0x1f);
124msg_pspew("BAR2Sz=0x%01x\n", (tmp >> 19) & 0x7);
125tmp &= 0xffffffc0;
126tmp |= 0x0000001f;
127pci_rmmio_writel(tmp, mv_bar + PCI_BAR2_CONTROL);
128
129/* Enable flash: GPIO Port Control Register 0x104f0 */
130tmp = pci_mmio_readl(mv_bar + GPIO_PORT_CONTROL);
131msg_pspew("GPIOPortMode=0x%01x\n", (tmp >> 0) & 0x3);
132if (((tmp >> 0) & 0x3) != 0x2)
133msg_pinfo("Warning! Either the straps are incorrect or you "
134 "have no flash or someone overwrote the strap "
135 "values!\n");
136tmp &= 0xfffffffc;
137tmp |= 0x2;
138pci_rmmio_writel(tmp, mv_bar + GPIO_PORT_CONTROL);
139
140/* Get I/O BAR location. */
141addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_2);
142if (!addr)
143return 1;
144
145/* Truncate to reachable range.
146 * FIXME: Check if the I/O BAR is actually reachable.
147 * This is an arch specific check.
148 */
149mv_iobar = addr & 0xffff;
150msg_pspew("Activating I/O BAR at 0x%04x\n", mv_iobar);
151
152/* 512 kByte with two 8-bit latches, and
153 * 4 MByte with additional 3-bit latch. */
154max_rom_decode.parallel = 4 * 1024 * 1024;
155register_par_master(&par_master_satamv, BUS_PARALLEL);
156
157return 0;
158}
159
160/* BAR2 (MEM) can map NVRAM and flash. We set it to flash in the init function.
161 * If BAR2 is disabled, it still can be accessed indirectly via BAR1 (I/O).
162 * This code only supports indirect accesses for now.
163 */
164
165/* Indirect access to via the I/O BAR1. */
166static void satamv_indirect_chip_writeb(uint8_t val, chipaddr addr)
167{
168/* 0x80000000 selects BAR2 for remapping. */
169OUTL(((uint32_t)addr | 0x80000000) & 0xfffffffc, mv_iobar);
170OUTB(val, mv_iobar + 0x80 + (addr & 0x3));
171}
172
173/* Indirect access to via the I/O BAR1. */
174static uint8_t satamv_indirect_chip_readb(const chipaddr addr)
175{
176/* 0x80000000 selects BAR2 for remapping. */
177OUTL(((uint32_t)addr | 0x80000000) & 0xfffffffc, mv_iobar);
178return INB(mv_iobar + 0x80 + (addr & 0x3));
179}
180
181/* FIXME: Prefer direct access to BAR2 if BAR2 is active. */
182static void satamv_chip_writeb(const struct flashctx *flash, uint8_t val,
183 chipaddr addr)
184{
185satamv_indirect_chip_writeb(val, addr);
186}
187
188/* FIXME: Prefer direct access to BAR2 if BAR2 is active. */
189static uint8_t satamv_chip_readb(const struct flashctx *flash,
190 const chipaddr addr)
191{
192return satamv_indirect_chip_readb(addr);
193}
194
195#else
196#error PCI port I/O access is not supported on this architecture yet.
197#endif

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