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Root/trunk/programmer.h

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1/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2000 Silicon Integrated System Corporation
5 * Copyright (C) 2000 Ronald G. Minnich <rminnich@gmail.com>
6 * Copyright (C) 2005-2009 coresystems GmbH
7 * Copyright (C) 2006-2009 Carl-Daniel Hailfinger
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 */
23
24#ifndef __PROGRAMMER_H__
25#define __PROGRAMMER_H__ 1
26
27#include "flash.h"/* for chipaddr and flashctx */
28
29enum programmer {
30#if CONFIG_INTERNAL == 1
31PROGRAMMER_INTERNAL,
32#endif
33#if CONFIG_DUMMY == 1
34PROGRAMMER_DUMMY,
35#endif
36#if CONFIG_NIC3COM == 1
37PROGRAMMER_NIC3COM,
38#endif
39#if CONFIG_NICREALTEK == 1
40PROGRAMMER_NICREALTEK,
41#endif
42#if CONFIG_NICNATSEMI == 1
43PROGRAMMER_NICNATSEMI,
44#endif
45#if CONFIG_GFXNVIDIA == 1
46PROGRAMMER_GFXNVIDIA,
47#endif
48#if CONFIG_DRKAISER == 1
49PROGRAMMER_DRKAISER,
50#endif
51#if CONFIG_SATASII == 1
52PROGRAMMER_SATASII,
53#endif
54#if CONFIG_ATAHPT == 1
55PROGRAMMER_ATAHPT,
56#endif
57#if CONFIG_ATAVIA == 1
58PROGRAMMER_ATAVIA,
59#endif
60#if CONFIG_ATAPROMISE == 1
61PROGRAMMER_ATAPROMISE,
62#endif
63#if CONFIG_IT8212 == 1
64PROGRAMMER_IT8212,
65#endif
66#if CONFIG_FT2232_SPI == 1
67PROGRAMMER_FT2232_SPI,
68#endif
69#if CONFIG_SERPROG == 1
70PROGRAMMER_SERPROG,
71#endif
72#if CONFIG_BUSPIRATE_SPI == 1
73PROGRAMMER_BUSPIRATE_SPI,
74#endif
75#if CONFIG_DEDIPROG == 1
76PROGRAMMER_DEDIPROG,
77#endif
78#if CONFIG_RAYER_SPI == 1
79PROGRAMMER_RAYER_SPI,
80#endif
81#if CONFIG_PONY_SPI == 1
82PROGRAMMER_PONY_SPI,
83#endif
84#if CONFIG_NICINTEL == 1
85PROGRAMMER_NICINTEL,
86#endif
87#if CONFIG_NICINTEL_SPI == 1
88PROGRAMMER_NICINTEL_SPI,
89#endif
90#if CONFIG_NICINTEL_EEPROM == 1
91PROGRAMMER_NICINTEL_EEPROM,
92#endif
93#if CONFIG_OGP_SPI == 1
94PROGRAMMER_OGP_SPI,
95#endif
96#if CONFIG_SATAMV == 1
97PROGRAMMER_SATAMV,
98#endif
99#if CONFIG_LINUX_SPI == 1
100PROGRAMMER_LINUX_SPI,
101#endif
102#if CONFIG_USBBLASTER_SPI == 1
103PROGRAMMER_USBBLASTER_SPI,
104#endif
105#if CONFIG_MSTARDDC_SPI == 1
106PROGRAMMER_MSTARDDC_SPI,
107#endif
108#if CONFIG_PICKIT2_SPI == 1
109PROGRAMMER_PICKIT2_SPI,
110#endif
111#if CONFIG_CH341A_SPI == 1
112PROGRAMMER_CH341A_SPI,
113#endif
114PROGRAMMER_INVALID /* This must always be the last entry. */
115};
116
117enum programmer_type {
118PCI = 1, /* to detect uninitialized values */
119USB,
120OTHER,
121};
122
123struct dev_entry {
124uint16_t vendor_id;
125uint16_t device_id;
126const enum test_state status;
127const char *vendor_name;
128const char *device_name;
129};
130
131struct programmer_entry {
132const char *name;
133const enum programmer_type type;
134union {
135const struct dev_entry *const dev;
136const char *const note;
137} devs;
138
139int (*init) (void);
140
141void *(*map_flash_region) (const char *descr, uintptr_t phys_addr, size_t len);
142void (*unmap_flash_region) (void *virt_addr, size_t len);
143
144void (*delay) (unsigned int usecs);
145};
146
147extern const struct programmer_entry programmer_table[];
148
149int programmer_init(enum programmer prog, const char *param);
150int programmer_shutdown(void);
151
152enum bitbang_spi_master_type {
153BITBANG_SPI_INVALID= 0, /* This must always be the first entry. */
154#if CONFIG_RAYER_SPI == 1
155BITBANG_SPI_MASTER_RAYER,
156#endif
157#if CONFIG_PONY_SPI == 1
158BITBANG_SPI_MASTER_PONY,
159#endif
160#if CONFIG_NICINTEL_SPI == 1
161BITBANG_SPI_MASTER_NICINTEL,
162#endif
163#if CONFIG_INTERNAL == 1
164#if defined(__i386__) || defined(__x86_64__)
165BITBANG_SPI_MASTER_MCP,
166#endif
167#endif
168#if CONFIG_OGP_SPI == 1
169BITBANG_SPI_MASTER_OGP,
170#endif
171};
172
173struct bitbang_spi_master {
174enum bitbang_spi_master_type type;
175
176/* Note that CS# is active low, so val=0 means the chip is active. */
177void (*set_cs) (int val);
178void (*set_sck) (int val);
179void (*set_mosi) (int val);
180int (*get_miso) (void);
181void (*request_bus) (void);
182void (*release_bus) (void);
183/* Length of half a clock period in usecs. */
184unsigned int half_period;
185};
186
187#if NEED_PCI == 1
188struct pci_dev;
189
190/* pcidev.c */
191// FIXME: This needs to be local, not global(?)
192extern struct pci_access *pacc;
193int pci_init_common(void);
194uintptr_t pcidev_readbar(struct pci_dev *dev, int bar);
195struct pci_dev *pcidev_init(const struct dev_entry *devs, int bar);
196/* rpci_write_* are reversible writes. The original PCI config space register
197 * contents will be restored on shutdown.
198 */
199int rpci_write_byte(struct pci_dev *dev, int reg, uint8_t data);
200int rpci_write_word(struct pci_dev *dev, int reg, uint16_t data);
201int rpci_write_long(struct pci_dev *dev, int reg, uint32_t data);
202#endif
203
204#if CONFIG_INTERNAL == 1
205struct penable {
206uint16_t vendor_id;
207uint16_t device_id;
208const enum test_state status;
209const char *vendor_name;
210const char *device_name;
211int (*doit) (struct pci_dev *dev, const char *name);
212};
213
214extern const struct penable chipset_enables[];
215
216enum board_match_phase {
217P1,
218P2,
219P3
220};
221
222struct board_match {
223/* Any device, but make it sensible, like the ISA bridge. */
224uint16_t first_vendor;
225uint16_t first_device;
226uint16_t first_card_vendor;
227uint16_t first_card_device;
228
229/* Any device, but make it sensible, like
230 * the host bridge. May be NULL.
231 */
232uint16_t second_vendor;
233uint16_t second_device;
234uint16_t second_card_vendor;
235uint16_t second_card_device;
236
237/* Pattern to match DMI entries. May be NULL. */
238const char *dmi_pattern;
239
240/* The vendor / part name from the coreboot table. May be NULL. */
241const char *lb_vendor;
242const char *lb_part;
243
244enum board_match_phase phase;
245
246const char *vendor_name;
247const char *board_name;
248
249int max_rom_decode_parallel;
250const enum test_state status;
251int (*enable) (void); /* May be NULL. */
252};
253
254extern const struct board_match board_matches[];
255
256struct board_info {
257const char *vendor;
258const char *name;
259const enum test_state working;
260#ifdef CONFIG_PRINT_WIKI
261const char *url;
262const char *note;
263#endif
264};
265
266extern const struct board_info boards_known[];
267extern const struct board_info laptops_known[];
268#endif
269
270/* udelay.c */
271void myusec_delay(unsigned int usecs);
272void myusec_calibrate_delay(void);
273void internal_sleep(unsigned int usecs);
274void internal_delay(unsigned int usecs);
275
276#if CONFIG_INTERNAL == 1
277/* board_enable.c */
278int selfcheck_board_enables(void);
279int board_parse_parameter(const char *boardstring, const char **vendor, const char **model);
280void w836xx_ext_enter(uint16_t port);
281void w836xx_ext_leave(uint16_t port);
282void probe_superio_winbond(void);
283int it8705f_write_enable(uint8_t port);
284uint8_t sio_read(uint16_t port, uint8_t reg);
285void sio_write(uint16_t port, uint8_t reg, uint8_t data);
286void sio_mask(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask);
287void board_handle_before_superio(void);
288void board_handle_before_laptop(void);
289int board_flash_enable(const char *vendor, const char *model, const char *cb_vendor, const char *cb_model);
290
291/* chipset_enable.c */
292int chipset_flash_enable(void);
293
294/* processor_enable.c */
295int processor_flash_enable(void);
296#endif
297
298/* physmap.c */
299void *physmap(const char *descr, uintptr_t phys_addr, size_t len);
300void *rphysmap(const char *descr, uintptr_t phys_addr, size_t len);
301void *physmap_ro(const char *descr, uintptr_t phys_addr, size_t len);
302void *physmap_ro_unaligned(const char *descr, uintptr_t phys_addr, size_t len);
303void physunmap(void *virt_addr, size_t len);
304void physunmap_unaligned(void *virt_addr, size_t len);
305#if CONFIG_INTERNAL == 1
306int setup_cpu_msr(int cpu);
307void cleanup_cpu_msr(void);
308
309/* cbtable.c */
310int cb_parse_table(const char **vendor, const char **model);
311int cb_check_image(uint8_t *bios, int size);
312
313/* dmi.c */
314#if defined(__i386__) || defined(__x86_64__)
315extern int has_dmi_support;
316void dmi_init(void);
317int dmi_match(const char *pattern);
318#endif // defined(__i386__) || defined(__x86_64__)
319
320/* internal.c */
321struct superio {
322uint16_t vendor;
323uint16_t port;
324uint16_t model;
325};
326extern struct superio superios[];
327extern int superio_count;
328#define SUPERIO_VENDOR_NONE0x0
329#define SUPERIO_VENDOR_ITE0x1
330#define SUPERIO_VENDOR_WINBOND0x2
331#endif
332#if NEED_PCI == 1
333struct pci_dev *pci_dev_find_vendorclass(uint16_t vendor, uint16_t devclass);
334struct pci_dev *pci_dev_find(uint16_t vendor, uint16_t device);
335struct pci_dev *pci_card_find(uint16_t vendor, uint16_t device,
336 uint16_t card_vendor, uint16_t card_device);
337#endif
338int rget_io_perms(void);
339#if CONFIG_INTERNAL == 1
340extern int is_laptop;
341extern int laptop_ok;
342extern int force_boardenable;
343extern int force_boardmismatch;
344void probe_superio(void);
345int register_superio(struct superio s);
346extern enum chipbustype internal_buses_supported;
347int internal_init(void);
348#endif
349
350/* hwaccess.c */
351void mmio_writeb(uint8_t val, void *addr);
352void mmio_writew(uint16_t val, void *addr);
353void mmio_writel(uint32_t val, void *addr);
354uint8_t mmio_readb(void *addr);
355uint16_t mmio_readw(void *addr);
356uint32_t mmio_readl(void *addr);
357void mmio_readn(void *addr, uint8_t *buf, size_t len);
358void mmio_le_writeb(uint8_t val, void *addr);
359void mmio_le_writew(uint16_t val, void *addr);
360void mmio_le_writel(uint32_t val, void *addr);
361uint8_t mmio_le_readb(void *addr);
362uint16_t mmio_le_readw(void *addr);
363uint32_t mmio_le_readl(void *addr);
364#define pci_mmio_writeb mmio_le_writeb
365#define pci_mmio_writew mmio_le_writew
366#define pci_mmio_writel mmio_le_writel
367#define pci_mmio_readb mmio_le_readb
368#define pci_mmio_readw mmio_le_readw
369#define pci_mmio_readl mmio_le_readl
370void rmmio_writeb(uint8_t val, void *addr);
371void rmmio_writew(uint16_t val, void *addr);
372void rmmio_writel(uint32_t val, void *addr);
373void rmmio_le_writeb(uint8_t val, void *addr);
374void rmmio_le_writew(uint16_t val, void *addr);
375void rmmio_le_writel(uint32_t val, void *addr);
376#define pci_rmmio_writeb rmmio_le_writeb
377#define pci_rmmio_writew rmmio_le_writew
378#define pci_rmmio_writel rmmio_le_writel
379void rmmio_valb(void *addr);
380void rmmio_valw(void *addr);
381void rmmio_vall(void *addr);
382
383/* dummyflasher.c */
384#if CONFIG_DUMMY == 1
385int dummy_init(void);
386void *dummy_map(const char *descr, uintptr_t phys_addr, size_t len);
387void dummy_unmap(void *virt_addr, size_t len);
388#endif
389
390/* nic3com.c */
391#if CONFIG_NIC3COM == 1
392int nic3com_init(void);
393extern const struct dev_entry nics_3com[];
394#endif
395
396/* gfxnvidia.c */
397#if CONFIG_GFXNVIDIA == 1
398int gfxnvidia_init(void);
399extern const struct dev_entry gfx_nvidia[];
400#endif
401
402/* drkaiser.c */
403#if CONFIG_DRKAISER == 1
404int drkaiser_init(void);
405extern const struct dev_entry drkaiser_pcidev[];
406#endif
407
408/* nicrealtek.c */
409#if CONFIG_NICREALTEK == 1
410int nicrealtek_init(void);
411extern const struct dev_entry nics_realtek[];
412#endif
413
414/* nicnatsemi.c */
415#if CONFIG_NICNATSEMI == 1
416int nicnatsemi_init(void);
417extern const struct dev_entry nics_natsemi[];
418#endif
419
420/* nicintel.c */
421#if CONFIG_NICINTEL == 1
422int nicintel_init(void);
423extern const struct dev_entry nics_intel[];
424#endif
425
426/* nicintel_spi.c */
427#if CONFIG_NICINTEL_SPI == 1
428int nicintel_spi_init(void);
429extern const struct dev_entry nics_intel_spi[];
430#endif
431
432/* nicintel_eeprom.c */
433#if CONFIG_NICINTEL_EEPROM == 1
434int nicintel_ee_init(void);
435extern const struct dev_entry nics_intel_ee[];
436#endif
437
438/* ogp_spi.c */
439#if CONFIG_OGP_SPI == 1
440int ogp_spi_init(void);
441extern const struct dev_entry ogp_spi[];
442#endif
443
444/* satamv.c */
445#if CONFIG_SATAMV == 1
446int satamv_init(void);
447extern const struct dev_entry satas_mv[];
448#endif
449
450/* satasii.c */
451#if CONFIG_SATASII == 1
452int satasii_init(void);
453extern const struct dev_entry satas_sii[];
454#endif
455
456/* atahpt.c */
457#if CONFIG_ATAHPT == 1
458int atahpt_init(void);
459extern const struct dev_entry ata_hpt[];
460#endif
461
462/* atavia.c */
463#if CONFIG_ATAVIA == 1
464int atavia_init(void);
465void *atavia_map(const char *descr, uintptr_t phys_addr, size_t len);
466extern const struct dev_entry ata_via[];
467#endif
468
469/* atapromise.c */
470#if CONFIG_ATAPROMISE == 1
471int atapromise_init(void);
472void *atapromise_map(const char *descr, uintptr_t phys_addr, size_t len);
473extern const struct dev_entry ata_promise[];
474#endif
475
476/* it8212.c */
477#if CONFIG_IT8212 == 1
478int it8212_init(void);
479extern const struct dev_entry devs_it8212[];
480#endif
481
482/* ft2232_spi.c */
483#if CONFIG_FT2232_SPI == 1
484int ft2232_spi_init(void);
485extern const struct dev_entry devs_ft2232spi[];
486#endif
487
488/* usbblaster_spi.c */
489#if CONFIG_USBBLASTER_SPI == 1
490int usbblaster_spi_init(void);
491extern const struct dev_entry devs_usbblasterspi[];
492#endif
493
494/* mstarddc_spi.c */
495#if CONFIG_MSTARDDC_SPI == 1
496int mstarddc_spi_init(void);
497#endif
498
499/* pickit2_spi.c */
500#if CONFIG_PICKIT2_SPI == 1
501int pickit2_spi_init(void);
502extern const struct dev_entry devs_pickit2_spi[];
503#endif
504
505/* rayer_spi.c */
506#if CONFIG_RAYER_SPI == 1
507int rayer_spi_init(void);
508#endif
509
510/* pony_spi.c */
511#if CONFIG_PONY_SPI == 1
512int pony_spi_init(void);
513#endif
514
515/* bitbang_spi.c */
516int register_spi_bitbang_master(const struct bitbang_spi_master *master);
517
518/* buspirate_spi.c */
519#if CONFIG_BUSPIRATE_SPI == 1
520int buspirate_spi_init(void);
521#endif
522
523/* linux_spi.c */
524#if CONFIG_LINUX_SPI == 1
525int linux_spi_init(void);
526#endif
527
528/* dediprog.c */
529#if CONFIG_DEDIPROG == 1
530int dediprog_init(void);
531extern const struct dev_entry devs_dediprog[];
532#endif
533
534/* ch341a_spi.c */
535#if CONFIG_CH341A_SPI == 1
536int ch341a_spi_init(void);
537void ch341a_spi_delay(unsigned int usecs);
538extern const struct dev_entry devs_ch341a_spi[];
539#endif
540
541/* flashrom.c */
542struct decode_sizes {
543uint32_t parallel;
544uint32_t lpc;
545uint32_t fwh;
546uint32_t spi;
547};
548// FIXME: These need to be local, not global
549extern struct decode_sizes max_rom_decode;
550extern int programmer_may_write;
551extern unsigned long flashbase;
552unsigned int count_max_decode_exceedings(const struct flashctx *flash);
553char *extract_programmer_param(const char *param_name);
554
555/* spi.c */
556enum spi_controller {
557SPI_CONTROLLER_NONE,
558#if CONFIG_INTERNAL == 1
559#if defined(__i386__) || defined(__x86_64__)
560SPI_CONTROLLER_ICH7,
561SPI_CONTROLLER_ICH9,
562SPI_CONTROLLER_IT85XX,
563SPI_CONTROLLER_IT87XX,
564SPI_CONTROLLER_SB600,
565SPI_CONTROLLER_YANGTZE,
566SPI_CONTROLLER_VIA,
567SPI_CONTROLLER_WBSIO,
568#endif
569#endif
570#if CONFIG_FT2232_SPI == 1
571SPI_CONTROLLER_FT2232,
572#endif
573#if CONFIG_DUMMY == 1
574SPI_CONTROLLER_DUMMY,
575#endif
576#if CONFIG_BUSPIRATE_SPI == 1
577SPI_CONTROLLER_BUSPIRATE,
578#endif
579#if CONFIG_DEDIPROG == 1
580SPI_CONTROLLER_DEDIPROG,
581#endif
582#if CONFIG_OGP_SPI == 1 || CONFIG_NICINTEL_SPI == 1 || CONFIG_RAYER_SPI == 1 || CONFIG_PONY_SPI == 1 || (CONFIG_INTERNAL == 1 && (defined(__i386__) || defined(__x86_64__)))
583SPI_CONTROLLER_BITBANG,
584#endif
585#if CONFIG_LINUX_SPI == 1
586SPI_CONTROLLER_LINUX,
587#endif
588#if CONFIG_SERPROG == 1
589SPI_CONTROLLER_SERPROG,
590#endif
591#if CONFIG_USBBLASTER_SPI == 1
592SPI_CONTROLLER_USBBLASTER,
593#endif
594#if CONFIG_MSTARDDC_SPI == 1
595SPI_CONTROLLER_MSTARDDC,
596#endif
597#if CONFIG_PICKIT2_SPI == 1
598SPI_CONTROLLER_PICKIT2,
599#endif
600#if CONFIG_CH341A_SPI == 1
601SPI_CONTROLLER_CH341A_SPI,
602#endif
603};
604
605#define MAX_DATA_UNSPECIFIED 0
606#define MAX_DATA_READ_UNLIMITED 64 * 1024
607#define MAX_DATA_WRITE_UNLIMITED 256
608struct spi_master {
609enum spi_controller type;
610unsigned int max_data_read; // (Ideally,) maximum data read size in one go (excluding opcode+address).
611unsigned int max_data_write; // (Ideally,) maximum data write size in one go (excluding opcode+address).
612int (*command)(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt,
613 const unsigned char *writearr, unsigned char *readarr);
614int (*multicommand)(struct flashctx *flash, struct spi_command *cmds);
615
616/* Optimized functions for this master */
617int (*read)(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len);
618int (*write_256)(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len);
619int (*write_aai)(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len);
620const void *data;
621};
622
623int default_spi_send_command(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt,
624 const unsigned char *writearr, unsigned char *readarr);
625int default_spi_send_multicommand(struct flashctx *flash, struct spi_command *cmds);
626int default_spi_read(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len);
627int default_spi_write_256(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len);
628int default_spi_write_aai(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len);
629int register_spi_master(const struct spi_master *mst);
630
631/* The following enum is needed by ich_descriptor_tool and ich* code as well as in chipset_enable.c. */
632enum ich_chipset {
633CHIPSET_ICH_UNKNOWN,
634CHIPSET_ICH,
635CHIPSET_ICH2345,
636CHIPSET_ICH6,
637CHIPSET_POULSBO, /* SCH U* */
638CHIPSET_TUNNEL_CREEK, /* Atom E6xx */
639CHIPSET_CENTERTON, /* Atom S1220 S1240 S1260 */
640CHIPSET_ICH7,
641CHIPSET_ICH8,
642CHIPSET_ICH9,
643CHIPSET_ICH10,
644CHIPSET_5_SERIES_IBEX_PEAK,
645CHIPSET_6_SERIES_COUGAR_POINT,
646CHIPSET_7_SERIES_PANTHER_POINT,
647CHIPSET_8_SERIES_LYNX_POINT,
648CHIPSET_BAYTRAIL, /* Actually all with Silvermont architecture: Bay Trail, Avoton/Rangeley */
649CHIPSET_8_SERIES_LYNX_POINT_LP,
650CHIPSET_8_SERIES_WELLSBURG,
651CHIPSET_9_SERIES_WILDCAT_POINT,
652};
653
654/* ichspi.c */
655#if CONFIG_INTERNAL == 1
656extern uint32_t ichspi_bbar;
657int ich_init_spi(struct pci_dev *dev, void *spibar, enum ich_chipset ich_generation);
658int via_init_spi(struct pci_dev *dev, uint32_t mmio_base);
659
660/* amd_imc.c */
661int amd_imc_shutdown(struct pci_dev *dev);
662
663/* it85spi.c */
664int it85xx_spi_init(struct superio s);
665
666/* it87spi.c */
667void enter_conf_mode_ite(uint16_t port);
668void exit_conf_mode_ite(uint16_t port);
669void probe_superio_ite(void);
670int init_superio_ite(void);
671
672/* mcp6x_spi.c */
673int mcp6x_spi_init(int want_spi);
674
675/* sb600spi.c */
676int sb600_probe_spi(struct pci_dev *dev);
677
678/* wbsio_spi.c */
679int wbsio_check_for_spi(void);
680#endif
681
682/* opaque.c */
683struct opaque_master {
684int max_data_read;
685int max_data_write;
686/* Specific functions for this master */
687int (*probe) (struct flashctx *flash);
688int (*read) (struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len);
689int (*write) (struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len);
690int (*erase) (struct flashctx *flash, unsigned int blockaddr, unsigned int blocklen);
691const void *data;
692};
693int register_opaque_master(const struct opaque_master *mst);
694
695/* programmer.c */
696int noop_shutdown(void);
697void *fallback_map(const char *descr, uintptr_t phys_addr, size_t len);
698void fallback_unmap(void *virt_addr, size_t len);
699void noop_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr);
700void fallback_chip_writew(const struct flashctx *flash, uint16_t val, chipaddr addr);
701void fallback_chip_writel(const struct flashctx *flash, uint32_t val, chipaddr addr);
702void fallback_chip_writen(const struct flashctx *flash, const uint8_t *buf, chipaddr addr, size_t len);
703uint16_t fallback_chip_readw(const struct flashctx *flash, const chipaddr addr);
704uint32_t fallback_chip_readl(const struct flashctx *flash, const chipaddr addr);
705void fallback_chip_readn(const struct flashctx *flash, uint8_t *buf, const chipaddr addr, size_t len);
706struct par_master {
707void (*chip_writeb) (const struct flashctx *flash, uint8_t val, chipaddr addr);
708void (*chip_writew) (const struct flashctx *flash, uint16_t val, chipaddr addr);
709void (*chip_writel) (const struct flashctx *flash, uint32_t val, chipaddr addr);
710void (*chip_writen) (const struct flashctx *flash, const uint8_t *buf, chipaddr addr, size_t len);
711uint8_t (*chip_readb) (const struct flashctx *flash, const chipaddr addr);
712uint16_t (*chip_readw) (const struct flashctx *flash, const chipaddr addr);
713uint32_t (*chip_readl) (const struct flashctx *flash, const chipaddr addr);
714void (*chip_readn) (const struct flashctx *flash, uint8_t *buf, const chipaddr addr, size_t len);
715const void *data;
716};
717int register_par_master(const struct par_master *mst, const enum chipbustype buses);
718struct registered_master {
719enum chipbustype buses_supported;
720union {
721struct par_master par;
722struct spi_master spi;
723struct opaque_master opaque;
724};
725};
726extern struct registered_master registered_masters[];
727extern int registered_master_count;
728int register_master(const struct registered_master *mst);
729
730/* serprog.c */
731#if CONFIG_SERPROG == 1
732int serprog_init(void);
733void serprog_delay(unsigned int usecs);
734void *serprog_map(const char *descr, uintptr_t phys_addr, size_t len);
735#endif
736
737/* serial.c */
738#if IS_WINDOWS
739typedef HANDLE fdtype;
740#define SER_INV_FDINVALID_HANDLE_VALUE
741#else
742typedef int fdtype;
743#define SER_INV_FD-1
744#endif
745
746void sp_flush_incoming(void);
747fdtype sp_openserport(char *dev, int baud);
748extern fdtype sp_fd;
749int serialport_shutdown(void *data);
750int serialport_write(const unsigned char *buf, unsigned int writecnt);
751int serialport_write_nonblock(const unsigned char *buf, unsigned int writecnt, unsigned int timeout, unsigned int *really_wrote);
752int serialport_read(unsigned char *buf, unsigned int readcnt);
753int serialport_read_nonblock(unsigned char *c, unsigned int readcnt, unsigned int timeout, unsigned int *really_read);
754
755/* Serial port/pin mapping:
756
757 1CD<-
758 2RXD<-
759 3TXD->
760 4DTR->
761 5GND --
762 6DSR<-
763 7RTS->
764 8CTS<-
765 9RI<-
766*/
767enum SP_PIN {
768PIN_CD = 1,
769PIN_RXD,
770PIN_TXD,
771PIN_DTR,
772PIN_GND,
773PIN_DSR,
774PIN_RTS,
775PIN_CTS,
776PIN_RI,
777};
778
779void sp_set_pin(enum SP_PIN pin, int val);
780int sp_get_pin(enum SP_PIN pin);
781
782#endif/* !__PROGRAMMER_H__ */

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