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1/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2009 Joerg Fischer <turboj@gmx.de>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21#if defined(__i386__) || defined(__x86_64__)
22
23#include <stdlib.h>
24#include "flash.h"
25#include "programmer.h"
26#include "hwaccess.h"
27
28#define PCI_VENDOR_ID_REALTEK0x10ec
29#define PCI_VENDOR_ID_SMC12110x1113
30
31static uint32_t io_base_addr = 0;
32static int bios_rom_addr, bios_rom_data;
33
34const struct dev_entry nics_realtek[] = {
35{0x10ec, 0x8139, OK, "Realtek", "RTL8139/8139C/8139C+"},
36{0x10ec, 0x8169, NT, "Realtek", "RTL8169"},
37{0x1113, 0x1211, OK, "SMC", "1211TX"}, /* RTL8139 clone */
38
39{0},
40};
41
42static void nicrealtek_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr);
43static uint8_t nicrealtek_chip_readb(const struct flashctx *flash, const chipaddr addr);
44static const struct par_master par_master_nicrealtek = {
45.chip_readb= nicrealtek_chip_readb,
46.chip_readw= fallback_chip_readw,
47.chip_readl= fallback_chip_readl,
48.chip_readn= fallback_chip_readn,
49.chip_writeb= nicrealtek_chip_writeb,
50.chip_writew= fallback_chip_writew,
51.chip_writel= fallback_chip_writel,
52.chip_writen= fallback_chip_writen,
53};
54
55static int nicrealtek_shutdown(void *data)
56{
57/* FIXME: We forgot to disable software access again. */
58return 0;
59}
60
61int nicrealtek_init(void)
62{
63struct pci_dev *dev = NULL;
64
65if (rget_io_perms())
66return 1;
67
68dev = pcidev_init(nics_realtek, PCI_BASE_ADDRESS_0);
69if (!dev)
70return 1;
71
72io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0);
73if (!io_base_addr)
74return 1;
75
76/* Beware, this ignores the vendor ID! */
77switch (dev->device_id) {
78case 0x8139: /* RTL8139 */
79case 0x1211: /* SMC 1211TX */
80default:
81bios_rom_addr = 0xD4;
82bios_rom_data = 0xD7;
83break;
84case 0x8169: /* RTL8169 */
85bios_rom_addr = 0x30;
86bios_rom_data = 0x33;
87break;
88}
89
90if (register_shutdown(nicrealtek_shutdown, NULL))
91return 1;
92
93register_par_master(&par_master_nicrealtek, BUS_PARALLEL);
94
95return 0;
96}
97
98static void nicrealtek_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr)
99{
100/* Output addr and data, set WE to 0, set OE to 1, set CS to 0,
101 * enable software access.
102 */
103OUTL(((uint32_t)addr & 0x01FFFF) | 0x0A0000 | (val << 24),
104 io_base_addr + bios_rom_addr);
105/* Output addr and data, set WE to 1, set OE to 1, set CS to 1,
106 * enable software access.
107 */
108OUTL(((uint32_t)addr & 0x01FFFF) | 0x1E0000 | (val << 24),
109 io_base_addr + bios_rom_addr);
110}
111
112static uint8_t nicrealtek_chip_readb(const struct flashctx *flash, const chipaddr addr)
113{
114uint8_t val;
115
116/* FIXME: Can we skip reading the old data and simply use 0? */
117/* Read old data. */
118val = INB(io_base_addr + bios_rom_data);
119/* Output new addr and old data, set WE to 1, set OE to 0, set CS to 0,
120 * enable software access.
121 */
122OUTL(((uint32_t)addr & 0x01FFFF) | 0x060000 | (val << 24),
123 io_base_addr + bios_rom_addr);
124
125/* Read new data. */
126val = INB(io_base_addr + bios_rom_data);
127/* Output addr and new data, set WE to 1, set OE to 1, set CS to 1,
128 * enable software access.
129 */
130OUTL(((uint32_t)addr & 0x01FFFF) | 0x1E0000 | (val << 24),
131 io_base_addr + bios_rom_addr);
132
133return val;
134}
135
136#else
137#error PCI port I/O access is not supported on this architecture yet.
138#endif

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