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1/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21#if defined(__i386__) || defined(__x86_64__)
22
23#include <stdlib.h>
24#include "flash.h"
25#include "programmer.h"
26#include "hwaccess.h"
27
28#define BIOS_ROM_ADDR0x04
29#define BIOS_ROM_DATA0x08
30#define INT_STATUS0x0e
31#define INTERNAL_CONFIG0x00
32#define SELECT_REG_WINDOW0x800
33
34#define PCI_VENDOR_ID_3COM0x10b7
35
36static uint32_t io_base_addr = 0;
37static uint32_t internal_conf;
38static uint16_t id;
39
40const struct dev_entry nics_3com[] = {
41/* 3C90xB */
42{0x10b7, 0x9055, OK, "3COM", "3C90xB: PCI 10/100 Mbps; shared 10BASE-T/100BASE-TX"},
43{0x10b7, 0x9001, NT, "3COM", "3C90xB: PCI 10/100 Mbps; shared 10BASE-T/100BASE-T4" },
44{0x10b7, 0x9004, OK, "3COM", "3C90xB: PCI 10BASE-T (TPO)" },
45{0x10b7, 0x9005, NT, "3COM", "3C90xB: PCI 10BASE-T/10BASE2/AUI (COMBO)" },
46{0x10b7, 0x9006, NT, "3COM", "3C90xB: PCI 10BASE-T/10BASE2 (TPC)" },
47{0x10b7, 0x900a, NT, "3COM", "3C90xB: PCI 10BASE-FL" },
48{0x10b7, 0x905a, NT, "3COM", "3C90xB: PCI 10BASE-FX" },
49{0x10b7, 0x9058, OK, "3COM", "3C905B: Cyclone 10/100/BNC" },
50
51/* 3C905C */
52{0x10b7, 0x9200, OK, "3COM", "3C905C: EtherLink 10/100 PCI (TX)" },
53
54/* 3C980C */
55{0x10b7, 0x9805, NT, "3COM", "3C980C: EtherLink Server 10/100 PCI (TX)" },
56
57{0},
58};
59
60static void nic3com_chip_writeb(const struct flashctx *flash, uint8_t val,
61chipaddr addr);
62static uint8_t nic3com_chip_readb(const struct flashctx *flash,
63 const chipaddr addr);
64static const struct par_master par_master_nic3com = {
65.chip_readb= nic3com_chip_readb,
66.chip_readw= fallback_chip_readw,
67.chip_readl= fallback_chip_readl,
68.chip_readn= fallback_chip_readn,
69.chip_writeb= nic3com_chip_writeb,
70.chip_writew= fallback_chip_writew,
71.chip_writel= fallback_chip_writel,
72.chip_writen= fallback_chip_writen,
73};
74
75static int nic3com_shutdown(void *data)
76{
77/* 3COM 3C90xB cards need a special fixup. */
78if (id == 0x9055 || id == 0x9001 || id == 0x9004 || id == 0x9005
79 || id == 0x9006 || id == 0x900a || id == 0x905a || id == 0x9058) {
80/* Select register window 3 and restore the receiver status. */
81OUTW(SELECT_REG_WINDOW + 3, io_base_addr + INT_STATUS);
82OUTL(internal_conf, io_base_addr + INTERNAL_CONFIG);
83}
84
85return 0;
86}
87
88int nic3com_init(void)
89{
90struct pci_dev *dev = NULL;
91
92if (rget_io_perms())
93return 1;
94
95dev = pcidev_init(nics_3com, PCI_BASE_ADDRESS_0);
96if (!dev)
97return 1;
98
99io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0);
100if (!io_base_addr)
101return 1;
102
103id = dev->device_id;
104
105/* 3COM 3C90xB cards need a special fixup. */
106if (id == 0x9055 || id == 0x9001 || id == 0x9004 || id == 0x9005
107 || id == 0x9006 || id == 0x900a || id == 0x905a || id == 0x9058) {
108/* Select register window 3 and save the receiver status. */
109OUTW(SELECT_REG_WINDOW + 3, io_base_addr + INT_STATUS);
110internal_conf = INL(io_base_addr + INTERNAL_CONFIG);
111
112/* Set receiver type to MII for full BIOS ROM access. */
113OUTL((internal_conf & 0xf00fffff) | 0x00600000, io_base_addr);
114}
115
116/*
117 * The lowest 16 bytes of the I/O mapped register space of (most) 3COM
118 * cards form a 'register window' into one of multiple (usually 8)
119 * register banks. For 3C90xB/3C90xC we need register window/bank 0.
120 */
121OUTW(SELECT_REG_WINDOW + 0, io_base_addr + INT_STATUS);
122
123if (register_shutdown(nic3com_shutdown, NULL))
124return 1;
125
126max_rom_decode.parallel = 128 * 1024;
127register_par_master(&par_master_nic3com, BUS_PARALLEL);
128
129return 0;
130}
131
132static void nic3com_chip_writeb(const struct flashctx *flash, uint8_t val,
133chipaddr addr)
134{
135OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR);
136OUTB(val, io_base_addr + BIOS_ROM_DATA);
137}
138
139static uint8_t nic3com_chip_readb(const struct flashctx *flash,
140 const chipaddr addr)
141{
142OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR);
143return INB(io_base_addr + BIOS_ROM_DATA);
144}
145
146#else
147#error PCI port I/O access is not supported on this architecture yet.
148#endif

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