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Root/trunk/jedec.c

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1/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2000 Silicon Integrated System Corporation
5 * Copyright (C) 2006 Giampiero Giancipoli <gianci@email.it>
6 * Copyright (C) 2006 coresystems GmbH <info@coresystems.de>
7 * Copyright (C) 2007-2012 Carl-Daniel Hailfinger
8 * Copyright (C) 2009 Sean Nelson <audiohacked@gmail.com>
9 * Copyright (C) 2014 Stefan Tauner
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
24 */
25
26#include "flash.h"
27#include "chipdrivers.h"
28
29#define MAX_REFLASH_TRIES 0x10
30#define MASK_FULL 0xffff
31#define MASK_2AA 0x7ff
32#define MASK_AAA 0xfff
33
34/* Check one byte for odd parity */
35uint8_t oddparity(uint8_t val)
36{
37val = (val ^ (val >> 4)) & 0xf;
38val = (val ^ (val >> 2)) & 0x3;
39return (val ^ (val >> 1)) & 0x1;
40}
41
42static void toggle_ready_jedec_common(const struct flashctx *flash, chipaddr dst, unsigned int delay)
43{
44unsigned int i = 0;
45uint8_t tmp1, tmp2;
46
47tmp1 = chip_readb(flash, dst) & 0x40;
48
49while (i++ < 0xFFFFFFF) {
50if (delay)
51programmer_delay(delay);
52tmp2 = chip_readb(flash, dst) & 0x40;
53if (tmp1 == tmp2) {
54break;
55}
56tmp1 = tmp2;
57}
58if (i > 0x100000)
59msg_cdbg("%s: excessive loops, i=0x%x\n", __func__, i);
60}
61
62void toggle_ready_jedec(const struct flashctx *flash, chipaddr dst)
63{
64toggle_ready_jedec_common(flash, dst, 0);
65}
66
67/* Some chips require a minimum delay between toggle bit reads.
68 * The Winbond W39V040C wants 50 ms between reads on sector erase toggle,
69 * but experiments show that 2 ms are already enough. Pick a safety factor
70 * of 4 and use an 8 ms delay.
71 * Given that erase is slow on all chips, it is recommended to use
72 * toggle_ready_jedec_slow in erase functions.
73 */
74static void toggle_ready_jedec_slow(const struct flashctx *flash, chipaddr dst)
75{
76toggle_ready_jedec_common(flash, dst, 8 * 1000);
77}
78
79void data_polling_jedec(const struct flashctx *flash, chipaddr dst,
80uint8_t data)
81{
82unsigned int i = 0;
83uint8_t tmp;
84
85data &= 0x80;
86
87while (i++ < 0xFFFFFFF) {
88tmp = chip_readb(flash, dst) & 0x80;
89if (tmp == data) {
90break;
91}
92}
93if (i > 0x100000)
94msg_cdbg("%s: excessive loops, i=0x%x\n", __func__, i);
95}
96
97static unsigned int getaddrmask(const struct flashchip *chip)
98{
99switch (chip->feature_bits & FEATURE_ADDR_MASK) {
100case FEATURE_ADDR_FULL:
101return MASK_FULL;
102break;
103case FEATURE_ADDR_2AA:
104return MASK_2AA;
105break;
106case FEATURE_ADDR_AAA:
107return MASK_AAA;
108break;
109default:
110msg_cerr("%s called with unknown mask\n", __func__);
111return 0;
112break;
113}
114}
115
116static void start_program_jedec_common(const struct flashctx *flash, unsigned int mask)
117{
118chipaddr bios = flash->virtual_memory;
119bool shifted = (flash->chip->feature_bits & FEATURE_ADDR_SHIFTED);
120
121chip_writeb(flash, 0xAA, bios + ((shifted ? 0x2AAA : 0x5555) & mask));
122chip_writeb(flash, 0x55, bios + ((shifted ? 0x5555 : 0x2AAA) & mask));
123chip_writeb(flash, 0xA0, bios + ((shifted ? 0x2AAA : 0x5555) & mask));
124}
125
126int probe_jedec_29gl(struct flashctx *flash)
127{
128unsigned int mask = getaddrmask(flash->chip);
129chipaddr bios = flash->virtual_memory;
130const struct flashchip *chip = flash->chip;
131
132/* Reset chip to a clean slate */
133chip_writeb(flash, 0xF0, bios + (0x5555 & mask));
134
135/* Issue JEDEC Product ID Entry command */
136chip_writeb(flash, 0xAA, bios + (0x5555 & mask));
137chip_writeb(flash, 0x55, bios + (0x2AAA & mask));
138chip_writeb(flash, 0x90, bios + (0x5555 & mask));
139
140/* Read product ID */
141// FIXME: Continuation loop, second byte is at word 0x100/byte 0x200
142uint32_t man_id = chip_readb(flash, bios + 0x00);
143uint32_t dev_id = (chip_readb(flash, bios + 0x01) << 16) |
144 (chip_readb(flash, bios + 0x0E) << 8) |
145 (chip_readb(flash, bios + 0x0F) << 0);
146
147/* Issue JEDEC Product ID Exit command */
148chip_writeb(flash, 0xF0, bios + (0x5555 & mask));
149
150msg_cdbg("%s: man_id 0x%02x, dev_id 0x%06x", __func__, man_id, dev_id);
151if (!oddparity(man_id))
152msg_cdbg(", man_id parity violation");
153
154/* Read the product ID location again. We should now see normal flash contents. */
155uint32_t flashcontent1 = chip_readb(flash, bios + 0x00); // FIXME: Continuation loop
156uint32_t flashcontent2 = (chip_readb(flash, bios + 0x01) << 16) |
157 (chip_readb(flash, bios + 0x0E) << 8) |
158 (chip_readb(flash, bios + 0x0F) << 0);
159
160if (man_id == flashcontent1)
161msg_cdbg(", man_id seems to be normal flash content");
162if (dev_id == flashcontent2)
163msg_cdbg(", dev_id seems to be normal flash content");
164
165msg_cdbg("\n");
166if (man_id != chip->manufacture_id || dev_id != chip->model_id)
167return 0;
168
169return 1;
170}
171
172static int probe_jedec_common(struct flashctx *flash, unsigned int mask)
173{
174chipaddr bios = flash->virtual_memory;
175const struct flashchip *chip = flash->chip;
176bool shifted = (flash->chip->feature_bits & FEATURE_ADDR_SHIFTED);
177uint8_t id1, id2;
178uint32_t largeid1, largeid2;
179uint32_t flashcontent1, flashcontent2;
180unsigned int probe_timing_enter, probe_timing_exit;
181
182if (chip->probe_timing > 0)
183probe_timing_enter = probe_timing_exit = chip->probe_timing;
184else if (chip->probe_timing == TIMING_ZERO) { /* No delay. */
185probe_timing_enter = probe_timing_exit = 0;
186} else if (chip->probe_timing == TIMING_FIXME) { /* == _IGNORED */
187msg_cdbg("Chip lacks correct probe timing information, using default 10ms/40us. ");
188probe_timing_enter = 10000;
189probe_timing_exit = 40;
190} else {
191msg_cerr("Chip has negative value in probe_timing, failing without chip access\n");
192return 0;
193}
194
195/* Earlier probes might have been too fast for the chip to enter ID
196 * mode completely. Allow the chip to finish this before seeing a
197 * reset command.
198 */
199if (probe_timing_enter)
200programmer_delay(probe_timing_enter);
201/* Reset chip to a clean slate */
202if ((chip->feature_bits & FEATURE_RESET_MASK) == FEATURE_LONG_RESET)
203{
204chip_writeb(flash, 0xAA, bios + ((shifted ? 0x2AAA : 0x5555) & mask));
205if (probe_timing_exit)
206programmer_delay(10);
207chip_writeb(flash, 0x55, bios + ((shifted ? 0x5555 : 0x2AAA) & mask));
208if (probe_timing_exit)
209programmer_delay(10);
210}
211chip_writeb(flash, 0xF0, bios + ((shifted ? 0x2AAA : 0x5555) & mask));
212if (probe_timing_exit)
213programmer_delay(probe_timing_exit);
214
215/* Issue JEDEC Product ID Entry command */
216chip_writeb(flash, 0xAA, bios + ((shifted ? 0x2AAA : 0x5555) & mask));
217if (probe_timing_enter)
218programmer_delay(10);
219chip_writeb(flash, 0x55, bios + ((shifted ? 0x5555 : 0x2AAA) & mask));
220if (probe_timing_enter)
221programmer_delay(10);
222chip_writeb(flash, 0x90, bios + ((shifted ? 0x2AAA : 0x5555) & mask));
223if (probe_timing_enter)
224programmer_delay(probe_timing_enter);
225
226/* Read product ID */
227id1 = chip_readb(flash, bios + (0x00 << shifted));
228id2 = chip_readb(flash, bios + (0x01 << shifted));
229largeid1 = id1;
230largeid2 = id2;
231
232/* Check if it is a continuation ID, this should be a while loop. */
233if (id1 == 0x7F) {
234largeid1 <<= 8;
235id1 = chip_readb(flash, bios + 0x100);
236largeid1 |= id1;
237}
238if (id2 == 0x7F) {
239largeid2 <<= 8;
240id2 = chip_readb(flash, bios + 0x101);
241largeid2 |= id2;
242}
243
244/* Issue JEDEC Product ID Exit command */
245if ((chip->feature_bits & FEATURE_RESET_MASK) == FEATURE_LONG_RESET)
246{
247chip_writeb(flash, 0xAA, bios + ((shifted ? 0x2AAA : 0x5555) & mask));
248if (probe_timing_exit)
249programmer_delay(10);
250chip_writeb(flash, 0x55, bios + ((shifted ? 0x5555 : 0x2AAA) & mask));
251if (probe_timing_exit)
252programmer_delay(10);
253}
254chip_writeb(flash, 0xF0, bios + ((shifted ? 0x2AAA : 0x5555) & mask));
255if (probe_timing_exit)
256programmer_delay(probe_timing_exit);
257
258msg_cdbg("%s: id1 0x%02x, id2 0x%02x", __func__, largeid1, largeid2);
259if (!oddparity(id1))
260msg_cdbg(", id1 parity violation");
261
262/* Read the product ID location again. We should now see normal flash contents. */
263flashcontent1 = chip_readb(flash, bios + (0x00 << shifted));
264flashcontent2 = chip_readb(flash, bios + (0x01 << shifted));
265
266/* Check if it is a continuation ID, this should be a while loop. */
267if (flashcontent1 == 0x7F) {
268flashcontent1 <<= 8;
269flashcontent1 |= chip_readb(flash, bios + 0x100);
270}
271if (flashcontent2 == 0x7F) {
272flashcontent2 <<= 8;
273flashcontent2 |= chip_readb(flash, bios + 0x101);
274}
275
276if (largeid1 == flashcontent1)
277msg_cdbg(", id1 is normal flash content");
278if (largeid2 == flashcontent2)
279msg_cdbg(", id2 is normal flash content");
280
281msg_cdbg("\n");
282if (largeid1 != chip->manufacture_id || largeid2 != chip->model_id)
283return 0;
284
285return 1;
286}
287
288static int erase_sector_jedec_common(struct flashctx *flash, unsigned int page,
289 unsigned int pagesize, unsigned int mask)
290{
291chipaddr bios = flash->virtual_memory;
292bool shifted = (flash->chip->feature_bits & FEATURE_ADDR_SHIFTED);
293unsigned int delay_us = 0;
294
295if(flash->chip->probe_timing != TIMING_ZERO)
296delay_us = 10;
297
298/* Issue the Sector Erase command */
299chip_writeb(flash, 0xAA, bios + ((shifted ? 0x2AAA : 0x5555) & mask));
300programmer_delay(delay_us);
301chip_writeb(flash, 0x55, bios + ((shifted ? 0x5555 : 0x2AAA) & mask));
302programmer_delay(delay_us);
303chip_writeb(flash, 0x80, bios + ((shifted ? 0x2AAA : 0x5555) & mask));
304programmer_delay(delay_us);
305
306chip_writeb(flash, 0xAA, bios + ((shifted ? 0x2AAA : 0x5555) & mask));
307programmer_delay(delay_us);
308chip_writeb(flash, 0x55, bios + ((shifted ? 0x5555 : 0x2AAA) & mask));
309programmer_delay(delay_us);
310chip_writeb(flash, 0x30, bios + page);
311programmer_delay(delay_us);
312
313/* wait for Toggle bit ready */
314toggle_ready_jedec_slow(flash, bios);
315
316/* FIXME: Check the status register for errors. */
317return 0;
318}
319
320static int erase_block_jedec_common(struct flashctx *flash, unsigned int block,
321 unsigned int blocksize, unsigned int mask)
322{
323chipaddr bios = flash->virtual_memory;
324bool shifted = (flash->chip->feature_bits & FEATURE_ADDR_SHIFTED);
325unsigned int delay_us = 0;
326
327if(flash->chip->probe_timing != TIMING_ZERO)
328delay_us = 10;
329
330/* Issue the Sector Erase command */
331chip_writeb(flash, 0xAA, bios + ((shifted ? 0x2AAA : 0x5555) & mask));
332programmer_delay(delay_us);
333chip_writeb(flash, 0x55, bios + ((shifted ? 0x5555 : 0x2AAA) & mask));
334programmer_delay(delay_us);
335chip_writeb(flash, 0x80, bios + ((shifted ? 0x2AAA : 0x5555) & mask));
336programmer_delay(delay_us);
337
338chip_writeb(flash, 0xAA, bios + ((shifted ? 0x2AAA : 0x5555) & mask));
339programmer_delay(delay_us);
340chip_writeb(flash, 0x55, bios + ((shifted ? 0x5555 : 0x2AAA) & mask));
341programmer_delay(delay_us);
342chip_writeb(flash, 0x50, bios + block);
343programmer_delay(delay_us);
344
345/* wait for Toggle bit ready */
346toggle_ready_jedec_slow(flash, bios);
347
348/* FIXME: Check the status register for errors. */
349return 0;
350}
351
352static int erase_chip_jedec_common(struct flashctx *flash, unsigned int mask)
353{
354chipaddr bios = flash->virtual_memory;
355bool shifted = (flash->chip->feature_bits & FEATURE_ADDR_SHIFTED);
356unsigned int delay_us = 0;
357
358if(flash->chip->probe_timing != TIMING_ZERO)
359delay_us = 10;
360
361/* Issue the JEDEC Chip Erase command */
362chip_writeb(flash, 0xAA, bios + ((shifted ? 0x2AAA : 0x5555) & mask));
363programmer_delay(delay_us);
364chip_writeb(flash, 0x55, bios + ((shifted ? 0x5555 : 0x2AAA) & mask));
365programmer_delay(delay_us);
366chip_writeb(flash, 0x80, bios + ((shifted ? 0x2AAA : 0x5555) & mask));
367programmer_delay(delay_us);
368
369chip_writeb(flash, 0xAA, bios + ((shifted ? 0x2AAA : 0x5555) & mask));
370programmer_delay(delay_us);
371chip_writeb(flash, 0x55, bios + ((shifted ? 0x5555 : 0x2AAA) & mask));
372programmer_delay(delay_us);
373chip_writeb(flash, 0x10, bios + ((shifted ? 0x2AAA : 0x5555) & mask));
374programmer_delay(delay_us);
375
376toggle_ready_jedec_slow(flash, bios);
377
378/* FIXME: Check the status register for errors. */
379return 0;
380}
381
382static int write_byte_program_jedec_common(const struct flashctx *flash, const uint8_t *src,
383 chipaddr dst, unsigned int mask)
384{
385int tried = 0, failed = 0;
386chipaddr bios = flash->virtual_memory;
387
388/* If the data is 0xFF, don't program it and don't complain. */
389if (*src == 0xFF) {
390return 0;
391}
392
393retry:
394/* Issue JEDEC Byte Program command */
395start_program_jedec_common(flash, mask);
396
397/* transfer data from source to destination */
398chip_writeb(flash, *src, dst);
399toggle_ready_jedec(flash, bios);
400
401if (chip_readb(flash, dst) != *src && tried++ < MAX_REFLASH_TRIES) {
402goto retry;
403}
404
405if (tried >= MAX_REFLASH_TRIES)
406failed = 1;
407
408return failed;
409}
410
411/* chunksize is 1 */
412int write_jedec_1(struct flashctx *flash, const uint8_t *src, unsigned int start,
413 unsigned int len)
414{
415int i, failed = 0;
416chipaddr dst = flash->virtual_memory + start;
417chipaddr olddst;
418unsigned int mask;
419
420mask = getaddrmask(flash->chip);
421
422olddst = dst;
423for (i = 0; i < len; i++) {
424if (write_byte_program_jedec_common(flash, src, dst, mask))
425failed = 1;
426dst++, src++;
427}
428if (failed)
429msg_cerr(" writing sector at 0x%" PRIxPTR " failed!\n", olddst);
430
431return failed;
432}
433
434static int write_page_write_jedec_common(struct flashctx *flash, const uint8_t *src,
435 unsigned int start, unsigned int page_size)
436{
437int i, tried = 0, failed;
438const uint8_t *s = src;
439chipaddr bios = flash->virtual_memory;
440chipaddr dst = bios + start;
441chipaddr d = dst;
442unsigned int mask;
443
444mask = getaddrmask(flash->chip);
445
446retry:
447/* Issue JEDEC Start Program command */
448start_program_jedec_common(flash, mask);
449
450/* transfer data from source to destination */
451for (i = 0; i < page_size; i++) {
452/* If the data is 0xFF, don't program it */
453if (*src != 0xFF)
454chip_writeb(flash, *src, dst);
455dst++;
456src++;
457}
458
459toggle_ready_jedec(flash, dst - 1);
460
461dst = d;
462src = s;
463failed = verify_range(flash, src, start, page_size);
464
465if (failed && tried++ < MAX_REFLASH_TRIES) {
466msg_cerr("retrying.\n");
467goto retry;
468}
469if (failed) {
470msg_cerr(" page 0x%" PRIxPTR " failed!\n", (d - bios) / page_size);
471}
472return failed;
473}
474
475/* chunksize is page_size */
476/*
477 * Write a part of the flash chip.
478 * FIXME: Use the chunk code from Michael Karcher instead.
479 * This function is a slightly modified copy of spi_write_chunked.
480 * Each page is written separately in chunks with a maximum size of chunksize.
481 */
482int write_jedec(struct flashctx *flash, const uint8_t *buf, unsigned int start,
483int unsigned len)
484{
485unsigned int i, starthere, lenhere;
486/* FIXME: page_size is the wrong variable. We need max_writechunk_size
487 * in struct flashctx to do this properly. All chips using
488 * write_jedec have page_size set to max_writechunk_size, so
489 * we're OK for now.
490 */
491unsigned int page_size = flash->chip->page_size;
492
493/* Warning: This loop has a very unusual condition and body.
494 * The loop needs to go through each page with at least one affected
495 * byte. The lowest page number is (start / page_size) since that
496 * division rounds down. The highest page number we want is the page
497 * where the last byte of the range lives. That last byte has the
498 * address (start + len - 1), thus the highest page number is
499 * (start + len - 1) / page_size. Since we want to include that last
500 * page as well, the loop condition uses <=.
501 */
502for (i = start / page_size; i <= (start + len - 1) / page_size; i++) {
503/* Byte position of the first byte in the range in this page. */
504/* starthere is an offset to the base address of the chip. */
505starthere = max(start, i * page_size);
506/* Length of bytes in the range in this page. */
507lenhere = min(start + len, (i + 1) * page_size) - starthere;
508
509if (write_page_write_jedec_common(flash, buf + starthere - start, starthere, lenhere))
510return 1;
511}
512
513return 0;
514}
515
516/* erase chip with block_erase() prototype */
517int erase_chip_block_jedec(struct flashctx *flash, unsigned int addr,
518 unsigned int blocksize)
519{
520unsigned int mask;
521
522mask = getaddrmask(flash->chip);
523if ((addr != 0) || (blocksize != flash->chip->total_size * 1024)) {
524msg_cerr("%s called with incorrect arguments\n",
525__func__);
526return -1;
527}
528return erase_chip_jedec_common(flash, mask);
529}
530
531int probe_jedec(struct flashctx *flash)
532{
533unsigned int mask;
534
535mask = getaddrmask(flash->chip);
536return probe_jedec_common(flash, mask);
537}
538
539int erase_sector_jedec(struct flashctx *flash, unsigned int page,
540 unsigned int size)
541{
542unsigned int mask;
543
544mask = getaddrmask(flash->chip);
545return erase_sector_jedec_common(flash, page, size, mask);
546}
547
548int erase_block_jedec(struct flashctx *flash, unsigned int page,
549 unsigned int size)
550{
551unsigned int mask;
552
553mask = getaddrmask(flash->chip);
554return erase_block_jedec_common(flash, page, size, mask);
555}
556
557int erase_chip_jedec(struct flashctx *flash)
558{
559unsigned int mask;
560
561mask = getaddrmask(flash->chip);
562return erase_chip_jedec_common(flash, mask);
563}
564
565struct unlockblock {
566unsigned int size;
567unsigned int count;
568};
569
570typedef int (*unlockblock_func)(const struct flashctx *flash, chipaddr offset);
571static int regspace2_walk_unlockblocks(const struct flashctx *flash, const struct unlockblock *block, unlockblock_func func)
572{
573chipaddr off = flash->virtual_registers + 2;
574while (block->count != 0) {
575unsigned int j;
576for (j = 0; j < block->count; j++) {
577if (func(flash, off))
578return -1;
579off += block->size;
580}
581block++;
582}
583return 0;
584}
585
586#define REG2_RWLOCK ((1 << 2) | (1 << 0))
587#define REG2_LOCKDOWN (1 << 1)
588#define REG2_MASK (REG2_RWLOCK | REG2_LOCKDOWN)
589
590static int printlock_regspace2_block(const struct flashctx *flash, chipaddr lockreg)
591{
592uint8_t state = chip_readb(flash, lockreg);
593msg_cdbg("Lock status of block at 0x%0*" PRIxPTR " is ", PRIxPTR_WIDTH, lockreg);
594switch (state & REG2_MASK) {
595case 0:
596msg_cdbg("Full Access.\n");
597break;
598case 1:
599msg_cdbg("Write Lock (Default State).\n");
600break;
601case 2:
602msg_cdbg("Locked Open (Full Access, Locked Down).\n");
603break;
604case 3:
605msg_cdbg("Write Lock, Locked Down.\n");
606break;
607case 4:
608msg_cdbg("Read Lock.\n");
609break;
610case 5:
611msg_cdbg("Read/Write Lock.\n");
612break;
613case 6:
614msg_cdbg("Read Lock, Locked Down.\n");
615break;
616case 7:
617msg_cdbg("Read/Write Lock, Locked Down.\n");
618break;
619}
620return 0;
621}
622
623int printlock_regspace2_blocks(const struct flashctx *flash, const struct unlockblock *blocks)
624{
625return regspace2_walk_unlockblocks(flash, blocks, &printlock_regspace2_block);
626}
627
628static int printlock_regspace2_uniform(struct flashctx *flash, unsigned long block_size)
629{
630const unsigned int elems = flash->chip->total_size * 1024 / block_size;
631struct unlockblock blocks[2] = {{.size = block_size, .count = elems}};
632return regspace2_walk_unlockblocks(flash, blocks, &printlock_regspace2_block);
633}
634
635int printlock_regspace2_uniform_64k(struct flashctx *flash)
636{
637return printlock_regspace2_uniform(flash, 64 * 1024);
638}
639
640int printlock_regspace2_block_eraser_0(struct flashctx *flash)
641{
642// FIXME: this depends on the eraseblocks not to be filled up completely (i.e. to be null-terminated).
643const struct unlockblock *unlockblocks =
644(const struct unlockblock *)flash->chip->block_erasers[0].eraseblocks;
645return regspace2_walk_unlockblocks(flash, unlockblocks, &printlock_regspace2_block);
646}
647
648int printlock_regspace2_block_eraser_1(struct flashctx *flash)
649{
650// FIXME: this depends on the eraseblocks not to be filled up completely (i.e. to be null-terminated).
651const struct unlockblock *unlockblocks =
652(const struct unlockblock *)flash->chip->block_erasers[1].eraseblocks;
653return regspace2_walk_unlockblocks(flash, unlockblocks, &printlock_regspace2_block);
654}
655
656/* Try to change the lock register at address lockreg from cur to new.
657 *
658 * - Try to unlock the lock bit if requested and it is currently set (although this is probably futile).
659 * - Try to change the read/write bits if requested.
660 * - Try to set the lockdown bit if requested.
661 * Return an error immediately if any of this fails. */
662static int changelock_regspace2_block(const struct flashctx *flash, chipaddr lockreg, uint8_t cur, uint8_t new)
663{
664/* Only allow changes to known read/write/lockdown bits */
665if (((cur ^ new) & ~REG2_MASK) != 0) {
666msg_cerr("Invalid lock change from 0x%02x to 0x%02x requested at 0x%0*" PRIxPTR "!\n"
667 "Please report a bug at flashrom@flashrom.org\n",
668 cur, new, PRIxPTR_WIDTH, lockreg);
669return -1;
670}
671
672/* Exit early if no change (of read/write/lockdown bits) was requested. */
673if (((cur ^ new) & REG2_MASK) == 0) {
674msg_cdbg2("Lock bits at 0x%0*" PRIxPTR " not changed.\n", PRIxPTR_WIDTH, lockreg);
675return 0;
676}
677
678/* Normally the lockdown bit can not be cleared. Try nevertheless if requested. */
679if ((cur & REG2_LOCKDOWN) && !(new & REG2_LOCKDOWN)) {
680chip_writeb(flash, cur & ~REG2_LOCKDOWN, lockreg);
681cur = chip_readb(flash, lockreg);
682if ((cur & REG2_LOCKDOWN) == REG2_LOCKDOWN) {
683msg_cwarn("Lockdown can't be removed at 0x%0*" PRIxPTR "! New value: 0x%02x.\n",
684 PRIxPTR_WIDTH, lockreg, cur);
685return -1;
686}
687}
688
689/* Change read and/or write bit */
690if ((cur ^ new) & REG2_RWLOCK) {
691/* Do not lockdown yet. */
692uint8_t wanted = (cur & ~REG2_RWLOCK) | (new & REG2_RWLOCK);
693chip_writeb(flash, wanted, lockreg);
694cur = chip_readb(flash, lockreg);
695if (cur != wanted) {
696msg_cerr("Changing lock bits failed at 0x%0*" PRIxPTR "! New value: 0x%02x.\n",
697 PRIxPTR_WIDTH, lockreg, cur);
698return -1;
699}
700msg_cdbg("Changed lock bits at 0x%0*" PRIxPTR " to 0x%02x.\n",
701 PRIxPTR_WIDTH, lockreg, cur);
702}
703
704/* Eventually, enable lockdown if requested. */
705if (!(cur & REG2_LOCKDOWN) && (new & REG2_LOCKDOWN)) {
706chip_writeb(flash, new, lockreg);
707cur = chip_readb(flash, lockreg);
708if (cur != new) {
709msg_cerr("Enabling lockdown FAILED at 0x%0*" PRIxPTR "! New value: 0x%02x.\n",
710 PRIxPTR_WIDTH, lockreg, cur);
711return -1;
712}
713msg_cdbg("Enabled lockdown at 0x%0*" PRIxPTR ".\n", PRIxPTR_WIDTH, lockreg);
714}
715
716return 0;
717}
718
719static int unlock_regspace2_block_generic(const struct flashctx *flash, chipaddr lockreg)
720{
721uint8_t old = chip_readb(flash, lockreg);
722/* We don't care for the lockdown bit as long as the RW locks are 0 after we're done */
723return changelock_regspace2_block(flash, lockreg, old, old & ~REG2_RWLOCK);
724}
725
726static int unlock_regspace2_uniform(struct flashctx *flash, unsigned long block_size)
727{
728const unsigned int elems = flash->chip->total_size * 1024 / block_size;
729struct unlockblock blocks[2] = {{.size = block_size, .count = elems}};
730return regspace2_walk_unlockblocks(flash, blocks, &unlock_regspace2_block_generic);
731}
732
733int unlock_regspace2_uniform_64k(struct flashctx *flash)
734{
735return unlock_regspace2_uniform(flash, 64 * 1024);
736}
737
738int unlock_regspace2_uniform_32k(struct flashctx *flash)
739{
740return unlock_regspace2_uniform(flash, 32 * 1024);
741}
742
743int unlock_regspace2_block_eraser_0(struct flashctx *flash)
744{
745// FIXME: this depends on the eraseblocks not to be filled up completely (i.e. to be null-terminated).
746const struct unlockblock *unlockblocks =
747(const struct unlockblock *)flash->chip->block_erasers[0].eraseblocks;
748return regspace2_walk_unlockblocks(flash, unlockblocks, &unlock_regspace2_block_generic);
749}
750
751int unlock_regspace2_block_eraser_1(struct flashctx *flash)
752{
753// FIXME: this depends on the eraseblocks not to be filled up completely (i.e. to be null-terminated).
754const struct unlockblock *unlockblocks =
755(const struct unlockblock *)flash->chip->block_erasers[1].eraseblocks;
756return regspace2_walk_unlockblocks(flash, unlockblocks, &unlock_regspace2_block_generic);
757}
758

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