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Root/trunk/it87spi.c

1/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2007, 2008, 2009 Carl-Daniel Hailfinger
5 * Copyright (C) 2008 Ronald Hoogenboom <ronald@zonnet.nl>
6 * Copyright (C) 2008 coresystems GmbH
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 */
21
22/*
23 * Contains the ITE IT87* SPI specific routines
24 */
25
26#if defined(__i386__) || defined(__x86_64__)
27
28#include <string.h>
29#include <stdlib.h>
30#include <errno.h>
31#include "flash.h"
32#include "chipdrivers.h"
33#include "programmer.h"
34#include "hwaccess.h"
35#include "spi.h"
36
37#define ITE_SUPERIO_PORT10x2e
38#define ITE_SUPERIO_PORT20x4e
39
40static uint16_t it8716f_flashport = 0;
41/* use fast 33MHz SPI (<>0) or slow 16MHz (0) */
42static int fast_spi = 1;
43
44/* Helper functions for most recent ITE IT87xx Super I/O chips */
45#define CHIP_ID_BYTE1_REG0x20
46#define CHIP_ID_BYTE2_REG0x21
47#define CHIP_VER_REG0x22
48void enter_conf_mode_ite(uint16_t port)
49{
50OUTB(0x87, port);
51OUTB(0x01, port);
52OUTB(0x55, port);
53if (port == ITE_SUPERIO_PORT1)
54OUTB(0x55, port);
55else
56OUTB(0xaa, port);
57}
58
59void exit_conf_mode_ite(uint16_t port)
60{
61sio_write(port, 0x02, 0x02);
62}
63
64uint16_t probe_id_ite(uint16_t port)
65{
66uint16_t id;
67
68enter_conf_mode_ite(port);
69id = sio_read(port, CHIP_ID_BYTE1_REG) << 8;
70id |= sio_read(port, CHIP_ID_BYTE2_REG);
71exit_conf_mode_ite(port);
72
73return id;
74}
75
76void probe_superio_ite(void)
77{
78struct superio s = {0};
79uint16_t ite_ports[] = {ITE_SUPERIO_PORT1, ITE_SUPERIO_PORT2, 0};
80uint16_t *i = ite_ports;
81
82s.vendor = SUPERIO_VENDOR_ITE;
83for (; *i; i++) {
84s.port = *i;
85s.model = probe_id_ite(s.port);
86switch (s.model >> 8) {
87case 0x82:
88case 0x86:
89case 0x87:
90/* FIXME: Print revision for all models? */
91msg_pdbg("Found ITE Super I/O, ID 0x%04hx on port 0x%x\n", s.model, s.port);
92register_superio(s);
93break;
94case 0x85:
95msg_pdbg("Found ITE EC, ID 0x%04hx, Rev 0x%02x on port 0x%x.\n",
96 s.model, sio_read(s.port, CHIP_VER_REG), s.port);
97register_superio(s);
98break;
99}
100}
101
102return;
103}
104
105static int it8716f_spi_send_command(struct flashctx *flash,
106 unsigned int writecnt, unsigned int readcnt,
107 const unsigned char *writearr,
108 unsigned char *readarr);
109static int it8716f_spi_chip_read(struct flashctx *flash, uint8_t *buf,
110 unsigned int start, unsigned int len);
111static int it8716f_spi_chip_write_256(struct flashctx *flash, const uint8_t *buf,
112 unsigned int start, unsigned int len);
113
114static const struct spi_master spi_master_it87xx = {
115.type= SPI_CONTROLLER_IT87XX,
116.max_data_read= MAX_DATA_UNSPECIFIED,
117.max_data_write= MAX_DATA_UNSPECIFIED,
118.command= it8716f_spi_send_command,
119.multicommand= default_spi_send_multicommand,
120.read= it8716f_spi_chip_read,
121.write_256= it8716f_spi_chip_write_256,
122.write_aai= default_spi_write_aai,
123};
124
125static uint16_t it87spi_probe(uint16_t port)
126{
127uint8_t tmp = 0;
128uint16_t flashport = 0;
129
130enter_conf_mode_ite(port);
131
132char *param = extract_programmer_param("dualbiosindex");
133if (param != NULL) {
134sio_write(port, 0x07, 0x07); /* Select GPIO LDN */
135tmp = sio_read(port, 0xEF);
136if (*param == '\0') { /* Print current setting only. */
137free(param);
138} else {
139char *dualbiosindex_suffix;
140errno = 0;
141long chip_index = strtol(param, &dualbiosindex_suffix, 0);
142free(param);
143if (errno != 0 || *dualbiosindex_suffix != '\0' || chip_index < 0 || chip_index > 1) {
144msg_perr("DualBIOS: Invalid chip index requested - choose 0 or 1.\n");
145exit_conf_mode_ite(port);
146return 1;
147}
148if (chip_index != (tmp & 1)) {
149msg_pdbg("DualBIOS: Previous chip index: %d\n", tmp & 1);
150sio_write(port, 0xEF, (tmp & 0xFE) | chip_index);
151tmp = sio_read(port, 0xEF);
152if ((tmp & 1) != chip_index) {
153msg_perr("DualBIOS: Chip selection failed.\n");
154exit_conf_mode_ite(port);
155return 1;
156}
157}
158}
159msg_pinfo("DualBIOS: Selected chip: %d\n", tmp & 1);
160}
161
162/* NOLDN, reg 0x24, mask out lowest bit (suspend) */
163tmp = sio_read(port, 0x24) & 0xFE;
164/* Check if LPC->SPI translation is active. */
165if (!(tmp & 0x0e)) {
166msg_pdbg("No IT87* serial flash segment enabled.\n");
167exit_conf_mode_ite(port);
168/* Nothing to do. */
169return 0;
170}
171msg_pdbg("Serial flash segment 0x%08x-0x%08x %sabled\n",
172 0xFFFE0000, 0xFFFFFFFF, (tmp & 1 << 1) ? "en" : "dis");
173msg_pdbg("Serial flash segment 0x%08x-0x%08x %sabled\n",
174 0x000E0000, 0x000FFFFF, (tmp & 1 << 1) ? "en" : "dis");
175msg_pdbg("Serial flash segment 0x%08x-0x%08x %sabled\n",
176 0xFFEE0000, 0xFFEFFFFF, (tmp & 1 << 2) ? "en" : "dis");
177msg_pdbg("Serial flash segment 0x%08x-0x%08x %sabled\n",
178 0xFFF80000, 0xFFFEFFFF, (tmp & 1 << 3) ? "en" : "dis");
179msg_pdbg("LPC write to serial flash %sabled\n",
180 (tmp & 1 << 4) ? "en" : "dis");
181/* The LPC->SPI force write enable below only makes sense for
182 * non-programmer mode.
183 */
184/* If any serial flash segment is enabled, enable writing. */
185if ((tmp & 0xe) && (!(tmp & 1 << 4))) {
186msg_pdbg("Enabling LPC write to serial flash\n");
187tmp |= 1 << 4;
188sio_write(port, 0x24, tmp);
189}
190msg_pdbg("Serial flash pin %i\n", (tmp & 1 << 5) ? 87 : 29);
191/* LDN 0x7, reg 0x64/0x65 */
192sio_write(port, 0x07, 0x7);
193flashport = sio_read(port, 0x64) << 8;
194flashport |= sio_read(port, 0x65);
195msg_pdbg("Serial flash port 0x%04x\n", flashport);
196/* Non-default port requested? */
197param = extract_programmer_param("it87spiport");
198if (param) {
199char *endptr = NULL;
200unsigned long forced_flashport;
201forced_flashport = strtoul(param, &endptr, 0);
202/* Port 0, port >0x1000, unaligned ports and garbage strings
203 * are rejected.
204 */
205if (!forced_flashport || (forced_flashport >= 0x1000) ||
206 (forced_flashport & 0x7) || (*endptr != '\0')) {
207/* Using ports below 0x100 is a really bad idea, and
208 * should only be done if no port between 0x100 and
209 * 0xff8 works due to routing issues.
210 */
211msg_perr("Error: it87spiport specified, but no valid "
212 "port specified.\nPort must be a multiple of "
213 "0x8 and lie between 0x100 and 0xff8.\n");
214exit_conf_mode_ite(port);
215free(param);
216return 1;
217} else {
218flashport = (uint16_t)forced_flashport;
219msg_pinfo("Forcing serial flash port 0x%04x\n",
220 flashport);
221sio_write(port, 0x64, (flashport >> 8));
222sio_write(port, 0x65, (flashport & 0xff));
223}
224}
225free(param);
226exit_conf_mode_ite(port);
227it8716f_flashport = flashport;
228if (internal_buses_supported & BUS_SPI)
229msg_pdbg("Overriding chipset SPI with IT87 SPI.\n");
230/* FIXME: Add the SPI bus or replace the other buses with it? */
231register_spi_master(&spi_master_it87xx);
232return 0;
233}
234
235int init_superio_ite(void)
236{
237int i;
238int ret = 0;
239
240for (i = 0; i < superio_count; i++) {
241if (superios[i].vendor != SUPERIO_VENDOR_ITE)
242continue;
243
244switch (superios[i].model) {
245case 0x8500:
246case 0x8502:
247case 0x8510:
248case 0x8511:
249case 0x8512:
250/* FIXME: This should be enabled, but we need a check
251 * for laptop whitelisting due to the amount of things
252 * which can go wrong if the EC firmware does not
253 * implement the interface we want.
254 */
255//it85xx_spi_init(superios[i]);
256break;
257case 0x8705:
258ret |= it8705f_write_enable(superios[i].port);
259break;
260case 0x8716:
261case 0x8718:
262case 0x8720:
263case 0x8728:
264ret |= it87spi_probe(superios[i].port);
265break;
266default:
267msg_pdbg2("Super I/O ID 0x%04hx is not on the list of flash-capable controllers.\n",
268 superios[i].model);
269}
270}
271return ret;
272}
273
274/*
275 * The IT8716F only supports commands with length 1,2,4,5 bytes including
276 * command byte and can not read more than 3 bytes from the device.
277 *
278 * This function expects writearr[0] to be the first byte sent to the device,
279 * whereas the IT8716F splits commands internally into address and non-address
280 * commands with the address in inverse wire order. That's why the register
281 * ordering in case 4 and 5 may seem strange.
282 */
283static int it8716f_spi_send_command(struct flashctx *flash,
284 unsigned int writecnt, unsigned int readcnt,
285 const unsigned char *writearr,
286 unsigned char *readarr)
287{
288uint8_t busy, writeenc;
289int i;
290
291do {
292busy = INB(it8716f_flashport) & 0x80;
293} while (busy);
294if (readcnt > 3) {
295msg_pinfo("%s called with unsupported readcnt %i.\n",
296 __func__, readcnt);
297return SPI_INVALID_LENGTH;
298}
299switch (writecnt) {
300case 1:
301OUTB(writearr[0], it8716f_flashport + 1);
302writeenc = 0x0;
303break;
304case 2:
305OUTB(writearr[0], it8716f_flashport + 1);
306OUTB(writearr[1], it8716f_flashport + 7);
307writeenc = 0x1;
308break;
309case 4:
310OUTB(writearr[0], it8716f_flashport + 1);
311OUTB(writearr[1], it8716f_flashport + 4);
312OUTB(writearr[2], it8716f_flashport + 3);
313OUTB(writearr[3], it8716f_flashport + 2);
314writeenc = 0x2;
315break;
316case 5:
317OUTB(writearr[0], it8716f_flashport + 1);
318OUTB(writearr[1], it8716f_flashport + 4);
319OUTB(writearr[2], it8716f_flashport + 3);
320OUTB(writearr[3], it8716f_flashport + 2);
321OUTB(writearr[4], it8716f_flashport + 7);
322writeenc = 0x3;
323break;
324default:
325msg_pinfo("%s called with unsupported writecnt %i.\n",
326 __func__, writecnt);
327return SPI_INVALID_LENGTH;
328}
329/*
330 * Start IO, 33 or 16 MHz, readcnt input bytes, writecnt output bytes.
331 * Note:
332 * We can't use writecnt directly, but have to use a strange encoding.
333 */
334OUTB(((0x4 + (fast_spi ? 1 : 0)) << 4)
335| ((readcnt & 0x3) << 2) | (writeenc), it8716f_flashport);
336
337if (readcnt > 0) {
338do {
339busy = INB(it8716f_flashport) & 0x80;
340} while (busy);
341
342for (i = 0; i < readcnt; i++)
343readarr[i] = INB(it8716f_flashport + 5 + i);
344}
345
346return 0;
347}
348
349/* Page size is usually 256 bytes */
350static int it8716f_spi_page_program(struct flashctx *flash, const uint8_t *buf, unsigned int start)
351{
352unsigned int i;
353int result;
354chipaddr bios = flash->virtual_memory;
355
356result = spi_write_enable(flash);
357if (result)
358return result;
359/* FIXME: The command below seems to be redundant or wrong. */
360OUTB(0x06, it8716f_flashport + 1);
361OUTB(((2 + (fast_spi ? 1 : 0)) << 4), it8716f_flashport);
362for (i = 0; i < flash->chip->page_size; i++)
363mmio_writeb(buf[i], (void *)(bios + start + i));
364OUTB(0, it8716f_flashport);
365/* Wait until the Write-In-Progress bit is cleared.
366 * This usually takes 1-10 ms, so wait in 1 ms steps.
367 */
368while (spi_read_status_register(flash) & SPI_SR_WIP)
369programmer_delay(1000);
370return 0;
371}
372
373/*
374 * IT8716F only allows maximum of 512 kb SPI mapped to LPC memory cycles
375 * Need to read this big flash using firmware cycles 3 byte at a time.
376 */
377static int it8716f_spi_chip_read(struct flashctx *flash, uint8_t *buf,
378 unsigned int start, unsigned int len)
379{
380fast_spi = 0;
381
382/* FIXME: Check if someone explicitly requested to use IT87 SPI although
383 * the mainboard does not use IT87 SPI translation. This should be done
384 * via a programmer parameter for the internal programmer.
385 */
386if ((flash->chip->total_size * 1024 > 512 * 1024)) {
387spi_read_chunked(flash, buf, start, len, 3);
388} else {
389mmio_readn((void *)(flash->virtual_memory + start), buf, len);
390}
391
392return 0;
393}
394
395static int it8716f_spi_chip_write_256(struct flashctx *flash, const uint8_t *buf,
396 unsigned int start, unsigned int len)
397{
398const struct flashchip *chip = flash->chip;
399/*
400 * IT8716F only allows maximum of 512 kb SPI chip size for memory
401 * mapped access. It also can't write more than 1+3+256 bytes at once,
402 * so page_size > 256 bytes needs a fallback.
403 * FIXME: Split too big page writes into chunks IT87* can handle instead
404 * of degrading to single-byte program.
405 * FIXME: Check if someone explicitly requested to use IT87 SPI although
406 * the mainboard does not use IT87 SPI translation. This should be done
407 * via a programmer parameter for the internal programmer.
408 */
409if ((chip->total_size * 1024 > 512 * 1024) || (chip->page_size > 256)) {
410spi_chip_write_1(flash, buf, start, len);
411} else {
412unsigned int lenhere;
413
414if (start % chip->page_size) {
415/* start to the end of the page or to start + len,
416 * whichever is smaller.
417 */
418lenhere = min(len, chip->page_size - start % chip->page_size);
419spi_chip_write_1(flash, buf, start, lenhere);
420start += lenhere;
421len -= lenhere;
422buf += lenhere;
423}
424
425while (len >= chip->page_size) {
426it8716f_spi_page_program(flash, buf, start);
427start += chip->page_size;
428len -= chip->page_size;
429buf += chip->page_size;
430}
431if (len)
432spi_chip_write_1(flash, buf, start, len);
433}
434
435return 0;
436}
437
438#endif

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