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1/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (c) 2010 Matthias Wenzel <bios at mazzoo dot de>
5 * Copyright (c) 2011 Stefan Tauner
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 */
21
22#if defined(__i386__) || defined(__x86_64__)
23#ifndef __ICH_DESCRIPTORS_H__
24#define __ICH_DESCRIPTORS_H__ 1
25
26#include <stdint.h>
27#include "programmer.h" /* for enum ich_chipset */
28
29/* FIXME: Replace with generic return codes */
30#define ICH_RET_OK0
31#define ICH_RET_ERR-1
32#define ICH_RET_WARN-2
33#define ICH_RET_PARAM-3
34#define ICH_RET_OOB-4
35
36#define ICH9_REG_FDOC0xB0/* 32 Bits Flash Descriptor Observability Control */
37/* 0-1: reserved */
38#define FDOC_FDSI_OFF2/* 2-11: Flash Descriptor Section Index */
39#define FDOC_FDSI(0x3f << FDOC_FDSI_OFF)
40#define FDOC_FDSS_OFF12/* 12-14: Flash Descriptor Section Select */
41#define FDOC_FDSS(0x3 << FDOC_FDSS_OFF)
42/* 15-31: reserved */
43
44#define ICH9_REG_FDOD0xB4/* 32 Bits Flash Descriptor Observability Data */
45
46/* Field locations and semantics for LVSCC, UVSCC and related words in the flash
47 * descriptor are equal therefore they all share the same macros below. */
48#define VSCC_BES_OFF0/* 0-1: Block/Sector Erase Size */
49#define VSCC_BES(0x3 << VSCC_BES_OFF)
50#define VSCC_WG_OFF2/* 2: Write Granularity */
51#define VSCC_WG(0x1 << VSCC_WG_OFF)
52#define VSCC_WSR_OFF3/* 3: Write Status Required */
53#define VSCC_WSR(0x1 << VSCC_WSR_OFF)
54#define VSCC_WEWS_OFF4/* 4: Write Enable on Write Status */
55#define VSCC_WEWS(0x1 << VSCC_WEWS_OFF)
56/* 5-7: reserved */
57#define VSCC_EO_OFF8/* 8-15: Erase Opcode */
58#define VSCC_EO(0xff << VSCC_EO_OFF)
59/* 16-22: reserved */
60#define VSCC_VCL_OFF23/* 23: Vendor Component Lock */
61#define VSCC_VCL(0x1 << VSCC_VCL_OFF)
62/* 24-31: reserved */
63
64#define ICH_FREG_BASE(flreg) (((flreg) << 12) & 0x01fff000)
65#define ICH_FREG_LIMIT(flreg) (((flreg) >> 4) & 0x01fff000)
66
67void prettyprint_ich_reg_vscc(uint32_t reg_val, int verbosity, bool print_vcl);
68
69struct ich_desc_content {
70uint32_t FLVALSIG;/* 0x00 */
71union {/* 0x04 */
72uint32_t FLMAP0;
73struct {
74uint32_t FCBA:8, /* Flash Component Base Address */
75 NC:2, /* Number Of Components */
76:6,
77 FRBA:8, /* Flash Region Base Address */
78 NR:3, /* Number Of Regions */
79:5;
80};
81};
82union {/* 0x08 */
83uint32_t FLMAP1;
84struct {
85uint32_t FMBA:8, /* Flash Master Base Address */
86 NM:3, /* Number Of Masters */
87:5,
88 FISBA:8, /* Flash ICH Strap Base Address */
89 ISL:8; /* ICH Strap Length */
90};
91};
92union {/* 0x0c */
93uint32_t FLMAP2;
94struct {
95uint32_t FMSBA:8, /* Flash (G)MCH Strap Base Addr. */
96 MSL:8, /* MCH Strap Length */
97:16;
98};
99};
100};
101
102struct ich_desc_component {
103union {/* 0x00 */
104uint32_t FLCOMP; /* Flash Components Register */
105/* FLCOMP encoding on various generations:
106 *
107 * Chipset/Generationmax_speeddual_outputdensity
108 * [MHz]bitsmax.bits
109 * ICH8:33N/A50:2, 3:5
110 * ICH9:33N/A50:2, 3:5
111 * ICH10:33N/A50:2, 3:5
112 * Ibex Peak/5:50N/A50:2, 3:5
113 * Cougar Point/6:503050:2, 3:5
114 * Patsburg:503050:2, 3:5
115 * Panther Point/7503050:2, 3:5
116 * Lynx Point/8:503070:3, 4:7
117 * Wildcat Point/9:50?? (multi I/O)??:?, ?:?
118 */
119struct {
120uint32_t:17,
121 freq_read:3,
122 fastread:1,
123 freq_fastread:3,
124 freq_write:3,
125 freq_read_id:3,
126 dual_output:1, /* new since Cougar Point/6 */
127:1;
128} modes;
129struct {
130uint32_t comp1_density:3,
131 comp2_density:3,
132:26;
133} dens_old;
134struct {
135uint32_t comp1_density:4, /* new since Lynx Point/8 */
136 comp2_density:4,
137:24;
138} dens_new;
139};
140union {/* 0x04 */
141uint32_t FLILL; /* Flash Invalid Instructions Register */
142struct {
143uint32_t invalid_instr0:8,
144 invalid_instr1:8,
145 invalid_instr2:8,
146 invalid_instr3:8;
147};
148};
149union {/* 0x08 */
150uint32_t FLPB; /* Flash Partition Boundary Register */
151struct {
152uint32_t FPBA:13, /* Flash Partition Boundary Addr */
153:19;
154};
155};
156};
157
158struct ich_desc_region {
159union {
160uint32_t FLREGs[5];
161struct {
162struct { /* FLREG0 Flash Descriptor */
163uint32_t reg0_base:13,
164:3,
165 reg0_limit:13,
166:3;
167};
168struct { /* FLREG1 BIOS */
169uint32_t reg1_base:13,
170:3,
171 reg1_limit:13,
172:3;
173};
174struct { /* FLREG2 ME */
175uint32_t reg2_base:13,
176:3,
177 reg2_limit:13,
178:3;
179};
180struct { /* FLREG3 GbE */
181uint32_t reg3_base:13,
182:3,
183 reg3_limit:13,
184:3;
185};
186struct { /* FLREG4 Platform */
187uint32_t reg4_base:13,
188:3,
189 reg4_limit:13,
190:3;
191};
192};
193};
194};
195
196struct ich_desc_master {
197union {
198uint32_t FLMSTR1;
199struct {
200uint32_t BIOS_req_ID:16,
201 BIOS_descr_r:1,
202 BIOS_BIOS_r:1,
203 BIOS_ME_r:1,
204 BIOS_GbE_r:1,
205 BIOS_plat_r:1,
206:3,
207 BIOS_descr_w:1,
208 BIOS_BIOS_w:1,
209 BIOS_ME_w:1,
210 BIOS_GbE_w:1,
211 BIOS_plat_w:1,
212:3;
213};
214};
215union {
216uint32_t FLMSTR2;
217struct {
218uint32_t ME_req_ID:16,
219 ME_descr_r:1,
220 ME_BIOS_r:1,
221 ME_ME_r:1,
222 ME_GbE_r:1,
223 ME_plat_r:1,
224:3,
225 ME_descr_w:1,
226 ME_BIOS_w:1,
227 ME_ME_w:1,
228 ME_GbE_w:1,
229 ME_plat_w:1,
230:3;
231};
232};
233union {
234uint32_t FLMSTR3;
235struct {
236uint32_t GbE_req_ID:16,
237 GbE_descr_r:1,
238 GbE_BIOS_r:1,
239 GbE_ME_r:1,
240 GbE_GbE_r:1,
241 GbE_plat_r:1,
242:3,
243 GbE_descr_w:1,
244 GbE_BIOS_w:1,
245 GbE_ME_w:1,
246 GbE_GbE_w:1,
247 GbE_plat_w:1,
248:3;
249};
250};
251};
252
253#ifdef ICH_DESCRIPTORS_FROM_DUMP
254struct ich_desc_north_strap {
255union {
256uint32_t STRPs[1]; /* current maximum: ich8 */
257struct { /* ich8 */
258struct { /* STRP2 (in the datasheet) */
259uint32_t MDB:1,
260:31;
261};
262} ich8;
263};
264};
265
266struct ich_desc_south_strap {
267union {
268uint32_t STRPs[18]; /* current maximum: cougar point */
269struct { /* ich8 */
270struct { /* STRP1 */
271uint32_t ME_DISABLE:1,
272:6,
273 TCOMODE:1,
274 ASD:7,
275 BMCMODE:1,
276:3,
277 GLAN_PCIE_SEL:1,
278 GPIO12_SEL:2,
279 SPICS1_LANPHYPC_SEL:1,
280 MESM2SEL:1,
281:1,
282 ASD2:7;
283};
284} ich8;
285struct { /* ibex peak */
286struct { /* STRP0 */
287uint32_t:1,
288 cs_ss2:1,
289:5,
290 SMB_EN:1,
291 SML0_EN:1,
292 SML1_EN:1,
293 SML1FRQ:2,
294 SMB0FRQ:2,
295 SML0FRQ:2,
296:4,
297 LANPHYPC_GP12_SEL:1,
298 cs_ss1:1,
299:2,
300 DMI_REQID_DIS:1,
301:4,
302 BBBS:2,
303:1;
304};
305struct { /* STRP1 */
306uint32_t cs_ss3:4,
307:28;
308};
309struct { /* STRP2 */
310uint32_t:8,
311 MESMASDEN:1,
312 MESMASDA:7,
313:8,
314 MESMI2CEN:1,
315 MESMI2CA:7;
316};
317struct { /* STRP3 */
318uint32_t:32;
319};
320struct { /* STRP4 */
321uint32_t PHYCON:2,
322:6,
323 GBEMAC_SMBUS_ADDR_EN:1,
324 GBEMAC_SMBUS_ADDR:7,
325:1,
326 GBEPHY_SMBUS_ADDR:7,
327:8;
328};
329struct { /* STRP5 */
330uint32_t:32;
331};
332struct { /* STRP6 */
333uint32_t:32;
334};
335struct { /* STRP7 */
336uint32_t MESMA2UDID_VENDOR:16,
337 MESMA2UDID_DEVICE:16;
338};
339struct { /* STRP8 */
340uint32_t:32;
341};
342struct { /* STRP9 */
343uint32_t PCIEPCS1:2,
344 PCIEPCS2:2,
345 PCIELR1:1,
346 PCIELR2:1,
347 DMILR:1,
348:1,
349 PHY_PCIEPORTSEL:3,
350 PHY_PCIE_EN:1,
351:20;
352};
353struct { /* STRP10 */
354uint32_t:1,
355 ME_BOOT_FLASH:1,
356 cs_ss5:1,
357 VE_EN:1,
358:4,
359 MMDDE:1,
360 MMADDR:7,
361 cs_ss7:1,
362:1,
363 ICC_SEL:3,
364 MER_CL1:1,
365:10;
366};
367struct { /* STRP11 */
368uint32_t SML1GPAEN:1,
369 SML1GPA:7,
370:16,
371 SML1I2CAEN:1,
372 SML1I2CA:7;
373};
374struct { /* STRP12 */
375uint32_t:32;
376};
377struct { /* STRP13 */
378uint32_t:32;
379};
380struct { /* STRP14 */
381uint32_t:8,
382 VE_EN2:1,
383:5,
384 VE_BOOT_FLASH:1,
385:1,
386 BW_SSD:1,
387 NVMHCI_EN:1,
388:14;
389};
390struct { /* STRP15 */
391uint32_t:3,
392 cs_ss6:2,
393:1,
394 IWL_EN:1,
395:1,
396 t209min:2,
397:22;
398};
399} ibex;
400struct { /* cougar point */
401struct { /* STRP0 */
402uint32_t:1,
403 cs_ss1:1,
404:5,
405 SMB_EN:1,
406 SML0_EN:1,
407 SML1_EN:1,
408 SML1FRQ:2,
409 SMB0FRQ:2,
410 SML0FRQ:2,
411:4,
412 LANPHYPC_GP12_SEL:1,
413 LINKSEC_DIS:1,
414:2,
415 DMI_REQID_DIS:1,
416:4,
417 BBBS:2,
418:1;
419};
420struct { /* STRP1 */
421uint32_t cs_ss3:4,
422:4,
423 cs_ss2:1,
424:28;
425};
426struct { /* STRP2 */
427uint32_t:8,
428 MESMASDEN:1,
429 MESMASDA:7,
430 MESMMCTPAEN:1,
431 MESMMCTPA:7,
432 MESMI2CEN:1,
433 MESMI2CA:7;
434};
435struct { /* STRP3 */
436uint32_t:32;
437};
438struct { /* STRP4 */
439uint32_t PHYCON:2,
440:6,
441 GBEMAC_SMBUS_ADDR_EN:1,
442 GBEMAC_SMBUS_ADDR:7,
443:1,
444 GBEPHY_SMBUS_ADDR:7,
445:8;
446};
447struct { /* STRP5 */
448uint32_t:32;
449};
450struct { /* STRP6 */
451uint32_t:32;
452};
453struct { /* STRP7 */
454uint32_t MESMA2UDID_VENDOR:16,
455 MESMA2UDID_DEVICE:16;
456};
457struct { /* STRP8 */
458uint32_t:32;
459};
460struct { /* STRP9 */
461uint32_t PCIEPCS1:2,
462 PCIEPCS2:2,
463 PCIELR1:1,
464 PCIELR2:1,
465 DMILR:1,
466 cs_ss4:1,
467 PHY_PCIEPORTSEL:3,
468 PHY_PCIE_EN:1,
469:2,
470 SUB_DECODE_EN:1,
471:7,
472 PCHHOT_SML1ALERT_SEL:1,
473:9;
474};
475struct { /* STRP10 */
476uint32_t:1,
477 ME_BOOT_FLASH:1,
478:6,
479 MDSMBE_EN:1,
480 MDSMBE_ADD:7,
481:2,
482 ICC_SEL:3,
483 MER_CL1:1,
484 ICC_PRO_SEL:1,
485 Deep_SX_EN:1,
486 ME_DBG_LAN:1,
487:7;
488};
489struct { /* STRP11 */
490uint32_t SML1GPAEN:1,
491 SML1GPA:7,
492:16,
493 SML1I2CAEN:1,
494 SML1I2CA:7;
495};
496struct { /* STRP12 */
497uint32_t:32;
498};
499struct { /* STRP13 */
500uint32_t:32;
501};
502struct { /* STRP14 */
503uint32_t:32;
504};
505struct { /* STRP15 */
506uint32_t cs_ss6:6,
507 IWL_EN:1,
508 cs_ss5:2,
509:4,
510 SMLINK1_THERM_SEL:1,
511 SLP_LAN_GP29_SEL:1,
512:16;
513};
514struct { /* STRP16 */
515uint32_t:32;
516};
517struct { /* STRP17 */
518uint32_t ICML:1,
519 cs_ss7:1,
520:30;
521};
522} cougar;
523};
524};
525
526struct ich_desc_upper_map {
527union {
528uint32_t FLUMAP1;/* Flash Upper Map 1 */
529struct {
530uint32_t VTBA:8,/* ME VSCC Table Base Address */
531 VTL:8,/* ME VSCC Table Length */
532:16;
533};
534};
535struct {
536union {/* JEDEC-ID Register */
537uint32_t JID;
538struct {
539uint32_t vid:8, /* Vendor ID */
540 cid0:8, /* Component ID 0 */
541 cid1:8, /* Component ID 1 */
542:8;
543};
544};
545union {/* Vendor Specific Component Capabilities */
546uint32_t VSCC;
547struct {
548uint32_t ubes:2, /* Upper Block/Sector Erase Size */
549 uwg:1, /* Upper Write Granularity */
550 uwsr:1, /* Upper Write Status Required */
551 uwews:1, /* Upper Write Enable on Write Status */
552:3,
553 ueo:8, /* Upper Erase Opcode */
554 lbes:2, /* Lower Block/Sector Erase Size */
555 lwg:1, /* Lower Write Granularity */
556 lwsr:1, /* Lower Write Status Required */
557 lwews:1, /* Lower Write Enable on Write Status */
558:3,
559 leo:16; /* Lower Erase Opcode */
560};
561};
562} vscc_table[128];
563};
564#endif /* ICH_DESCRIPTORS_FROM_DUMP */
565
566struct ich_descriptors {
567struct ich_desc_content content;
568struct ich_desc_component component;
569struct ich_desc_region region;
570struct ich_desc_master master;
571#ifdef ICH_DESCRIPTORS_FROM_DUMP
572struct ich_desc_north_strap north;
573struct ich_desc_south_strap south;
574struct ich_desc_upper_map upper;
575#endif /* ICH_DESCRIPTORS_FROM_DUMP */
576};
577
578void prettyprint_ich_descriptors(enum ich_chipset cs, const struct ich_descriptors *desc);
579
580void prettyprint_ich_descriptor_content(const struct ich_desc_content *content);
581void prettyprint_ich_descriptor_component(enum ich_chipset cs, const struct ich_descriptors *desc);
582void prettyprint_ich_descriptor_region(const struct ich_descriptors *desc);
583void prettyprint_ich_descriptor_master(const struct ich_desc_master *master);
584
585#ifdef ICH_DESCRIPTORS_FROM_DUMP
586
587void prettyprint_ich_descriptor_upper_map(const struct ich_desc_upper_map *umap);
588void prettyprint_ich_descriptor_straps(enum ich_chipset cs, const struct ich_descriptors *desc);
589int read_ich_descriptors_from_dump(const uint32_t *dump, unsigned int len, struct ich_descriptors *desc);
590
591#else /* ICH_DESCRIPTORS_FROM_DUMP */
592
593int read_ich_descriptors_via_fdo(void *spibar, struct ich_descriptors *desc);
594int getFCBA_component_density(enum ich_chipset cs, const struct ich_descriptors *desc, uint8_t idx);
595
596#endif /* ICH_DESCRIPTORS_FROM_DUMP */
597#endif /* __ICH_DESCRIPTORS_H__ */
598#endif /* defined(__i386__) || defined(__x86_64__) */

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