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1/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2009,2010 Carl-Daniel Hailfinger
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21#include "platform.h"
22
23#include <stdint.h>
24#include <string.h>
25#include <stdlib.h>
26#include <errno.h>
27#include <sys/types.h>
28#if !defined (__DJGPP__) && !defined(__LIBPAYLOAD__)
29/* No file access needed/possible to get hardware access permissions. */
30#include <unistd.h>
31#include <fcntl.h>
32#endif
33#include "flash.h"
34#include "hwaccess.h"
35
36#if !(IS_LINUX || IS_MACOSX || defined(__NetBSD__) || defined(__OpenBSD__) || defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) || defined(__DJGPP__) || defined(__LIBPAYLOAD__) || defined(__sun) || defined(__gnu_hurd__))
37#error "Unknown operating system"
38#endif
39
40#define USE_IOPL(IS_LINUX || IS_MACOSX || defined(__NetBSD__) || defined(__OpenBSD__))
41#define USE_DEV_IO(defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__))
42#define USE_IOPERM(defined(__gnu_hurd__))
43
44#if USE_IOPERM
45#include <sys/io.h>
46#endif
47
48#if IS_X86 && USE_DEV_IO
49int io_fd;
50#endif
51
52/* Prevent reordering and/or merging of reads/writes to hardware.
53 * Such reordering and/or merging would break device accesses which depend on the exact access order.
54 */
55static inline void sync_primitive(void)
56{
57/* This is not needed for...
58 * - x86: uses uncached accesses which have a strongly ordered memory model.
59 * - MIPS: uses uncached accesses in mode 2 on /dev/mem which has also a strongly ordered memory model.
60 * - ARM: uses a strongly ordered memory model for device memories.
61 *
62 * See also https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/Documentation/memory-barriers.txt
63 */
64#if IS_PPC // cf. http://lxr.free-electrons.com/source/arch/powerpc/include/asm/barrier.h
65asm("eieio" : : : "memory");
66#elif IS_SPARC
67#if defined(__sparc_v9__) || defined(__sparcv9)
68/* Sparc V9 CPUs support three different memory orderings that range from x86-like TSO to PowerPC-like
69 * RMO. The modes can be switched at runtime thus to make sure we maintain the right order of access we
70 * use the strongest hardware memory barriers that exist on Sparc V9. */
71asm volatile ("membar #Sync" ::: "memory");
72#elif defined(__sparc_v8__) || defined(__sparcv8)
73/* On SPARC V8 there is no RMO just PSO and that does not apply to I/O accesses... but if V8 code is run
74 * on V9 CPUs it might apply... or not... we issue a write barrier anyway. That's the most suitable
75 * operation in the V8 instruction set anyway. If you know better then please tell us. */
76asm volatile ("stbar");
77#else
78#error Unknown and/or unsupported SPARC instruction set version detected.
79#endif
80#endif
81}
82
83#if IS_X86 && !(defined(__DJGPP__) || defined(__LIBPAYLOAD__))
84static int release_io_perms(void *p)
85{
86#if defined (__sun)
87sysi86(SI86V86, V86SC_IOPL, 0);
88#elif USE_DEV_IO
89close(io_fd);
90#elif USE_IOPERM
91ioperm(0, 65536, 0);
92#elif USE_IOPL
93iopl(0);
94#endif
95return 0;
96}
97#endif
98
99/* Get I/O permissions with automatic permission release on shutdown. */
100int rget_io_perms(void)
101{
102#if IS_X86 && !(defined(__DJGPP__) || defined(__LIBPAYLOAD__))
103#if defined (__sun)
104if (sysi86(SI86V86, V86SC_IOPL, PS_IOPL) != 0) {
105#elif USE_DEV_IO
106if ((io_fd = open("/dev/io", O_RDWR)) < 0) {
107#elif USE_IOPERM
108if (ioperm(0, 65536, 1) != 0) {
109#elif USE_IOPL
110if (iopl(3) != 0) {
111#endif
112msg_perr("ERROR: Could not get I/O privileges (%s).\n", strerror(errno));
113msg_perr("You need to be root.\n");
114#if defined (__OpenBSD__)
115msg_perr("If you are root already please set securelevel=-1 in /etc/rc.securelevel and\n"
116 "reboot, or reboot into single user mode.\n");
117#elif defined(__NetBSD__)
118msg_perr("If you are root already please reboot into single user mode or make sure\n"
119 "that your kernel configuration has the option INSECURE enabled.\n");
120#endif
121return 1;
122} else {
123register_shutdown(release_io_perms, NULL);
124}
125#else
126/* DJGPP and libpayload environments have full PCI port I/O permissions by default. */
127/* PCI port I/O support is unimplemented on PPC/MIPS and unavailable on ARM. */
128#endif
129return 0;
130}
131
132void mmio_writeb(uint8_t val, void *addr)
133{
134*(volatile uint8_t *) addr = val;
135sync_primitive();
136}
137
138void mmio_writew(uint16_t val, void *addr)
139{
140*(volatile uint16_t *) addr = val;
141sync_primitive();
142}
143
144void mmio_writel(uint32_t val, void *addr)
145{
146*(volatile uint32_t *) addr = val;
147sync_primitive();
148}
149
150uint8_t mmio_readb(void *addr)
151{
152return *(volatile uint8_t *) addr;
153}
154
155uint16_t mmio_readw(void *addr)
156{
157return *(volatile uint16_t *) addr;
158}
159
160uint32_t mmio_readl(void *addr)
161{
162return *(volatile uint32_t *) addr;
163}
164
165void mmio_readn(void *addr, uint8_t *buf, size_t len)
166{
167memcpy(buf, addr, len);
168return;
169}
170
171void mmio_le_writeb(uint8_t val, void *addr)
172{
173mmio_writeb(cpu_to_le8(val), addr);
174}
175
176void mmio_le_writew(uint16_t val, void *addr)
177{
178mmio_writew(cpu_to_le16(val), addr);
179}
180
181void mmio_le_writel(uint32_t val, void *addr)
182{
183mmio_writel(cpu_to_le32(val), addr);
184}
185
186uint8_t mmio_le_readb(void *addr)
187{
188return le_to_cpu8(mmio_readb(addr));
189}
190
191uint16_t mmio_le_readw(void *addr)
192{
193return le_to_cpu16(mmio_readw(addr));
194}
195
196uint32_t mmio_le_readl(void *addr)
197{
198return le_to_cpu32(mmio_readl(addr));
199}
200
201enum mmio_write_type {
202mmio_write_type_b,
203mmio_write_type_w,
204mmio_write_type_l,
205};
206
207struct undo_mmio_write_data {
208void *addr;
209int reg;
210enum mmio_write_type type;
211union {
212uint8_t bdata;
213uint16_t wdata;
214uint32_t ldata;
215};
216};
217
218int undo_mmio_write(void *p)
219{
220struct undo_mmio_write_data *data = p;
221msg_pdbg("Restoring MMIO space at %p\n", data->addr);
222switch (data->type) {
223case mmio_write_type_b:
224mmio_writeb(data->bdata, data->addr);
225break;
226case mmio_write_type_w:
227mmio_writew(data->wdata, data->addr);
228break;
229case mmio_write_type_l:
230mmio_writel(data->ldata, data->addr);
231break;
232}
233/* p was allocated in register_undo_mmio_write. */
234free(p);
235return 0;
236}
237
238#define register_undo_mmio_write(a, c)\
239{\
240struct undo_mmio_write_data *undo_mmio_write_data;\
241undo_mmio_write_data = malloc(sizeof(struct undo_mmio_write_data)); \
242if (!undo_mmio_write_data) {\
243msg_gerr("Out of memory!\n");\
244exit(1);\
245}\
246undo_mmio_write_data->addr = a;\
247undo_mmio_write_data->type = mmio_write_type_##c;\
248undo_mmio_write_data->c##data = mmio_read##c(a);\
249register_shutdown(undo_mmio_write, undo_mmio_write_data);\
250}
251
252#define register_undo_mmio_writeb(a) register_undo_mmio_write(a, b)
253#define register_undo_mmio_writew(a) register_undo_mmio_write(a, w)
254#define register_undo_mmio_writel(a) register_undo_mmio_write(a, l)
255
256void rmmio_writeb(uint8_t val, void *addr)
257{
258register_undo_mmio_writeb(addr);
259mmio_writeb(val, addr);
260}
261
262void rmmio_writew(uint16_t val, void *addr)
263{
264register_undo_mmio_writew(addr);
265mmio_writew(val, addr);
266}
267
268void rmmio_writel(uint32_t val, void *addr)
269{
270register_undo_mmio_writel(addr);
271mmio_writel(val, addr);
272}
273
274void rmmio_le_writeb(uint8_t val, void *addr)
275{
276register_undo_mmio_writeb(addr);
277mmio_le_writeb(val, addr);
278}
279
280void rmmio_le_writew(uint16_t val, void *addr)
281{
282register_undo_mmio_writew(addr);
283mmio_le_writew(val, addr);
284}
285
286void rmmio_le_writel(uint32_t val, void *addr)
287{
288register_undo_mmio_writel(addr);
289mmio_le_writel(val, addr);
290}
291
292void rmmio_valb(void *addr)
293{
294register_undo_mmio_writeb(addr);
295}
296
297void rmmio_valw(void *addr)
298{
299register_undo_mmio_writew(addr);
300}
301
302void rmmio_vall(void *addr)
303{
304register_undo_mmio_writel(addr);
305}

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