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Root/trunk/chipset_enable.c

1/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2000 Silicon Integrated System Corporation
5 * Copyright (C) 2005-2009 coresystems GmbH
6 * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
7 * Copyright (C) 2007,2008,2009 Carl-Daniel Hailfinger
8 * Copyright (C) 2009 Kontron Modular Computers GmbH
9 * Copyright (C) 2011, 2012 Stefan Tauner
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; version 2 of the License.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 */
24
25/*
26 * Contains the chipset specific flash enables.
27 */
28
29#define _LARGEFILE64_SOURCE
30
31#include <stdlib.h>
32#include <string.h>
33#include <unistd.h>
34#include <inttypes.h>
35#include <errno.h>
36#include "flash.h"
37#include "programmer.h"
38#include "hwaccess.h"
39
40#define NOT_DONE_YET 1
41
42#if defined(__i386__) || defined(__x86_64__)
43
44static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name)
45{
46uint8_t tmp;
47
48/*
49 * ROM Write enable, 0xFFFC0000-0xFFFDFFFF and
50 * 0xFFFE0000-0xFFFFFFFF ROM select enable.
51 */
52tmp = pci_read_byte(dev, 0x47);
53tmp |= 0x46;
54rpci_write_byte(dev, 0x47, tmp);
55
56return 0;
57}
58
59static int enable_flash_rdc_r8610(struct pci_dev *dev, const char *name)
60{
61uint8_t tmp;
62
63/* enable ROMCS for writes */
64tmp = pci_read_byte(dev, 0x43);
65tmp |= 0x80;
66pci_write_byte(dev, 0x43, tmp);
67
68/* read the bootstrapping register */
69tmp = pci_read_byte(dev, 0x40) & 0x3;
70switch (tmp) {
71case 3:
72internal_buses_supported = BUS_FWH;
73break;
74case 2:
75internal_buses_supported = BUS_LPC;
76break;
77default:
78internal_buses_supported = BUS_PARALLEL;
79break;
80}
81
82return 0;
83}
84
85static int enable_flash_sis85c496(struct pci_dev *dev, const char *name)
86{
87uint8_t tmp;
88
89tmp = pci_read_byte(dev, 0xd0);
90tmp |= 0xf8;
91rpci_write_byte(dev, 0xd0, tmp);
92
93return 0;
94}
95
96static int enable_flash_sis_mapping(struct pci_dev *dev, const char *name)
97{
98#define SIS_MAPREG 0x40
99uint8_t new, newer;
100
101/* Extended BIOS enable = 1, Lower BIOS Enable = 1 */
102/* This is 0xFFF8000~0xFFFF0000 decoding on SiS 540/630. */
103new = pci_read_byte(dev, SIS_MAPREG);
104new &= (~0x04); /* No idea why we clear bit 2. */
105new |= 0xb; /* 0x3 for some chipsets, bit 7 seems to be don't care. */
106rpci_write_byte(dev, SIS_MAPREG, new);
107newer = pci_read_byte(dev, SIS_MAPREG);
108if (newer != new) { /* FIXME: share this with other code? */
109msg_pinfo("Setting register 0x%x to 0x%02x on %s failed (WARNING ONLY).\n",
110 SIS_MAPREG, new, name);
111msg_pinfo("Stuck at 0x%02x.\n", newer);
112return -1;
113}
114return 0;
115}
116
117static struct pci_dev *find_southbridge(uint16_t vendor, const char *name)
118{
119struct pci_dev *sbdev;
120
121sbdev = pci_dev_find_vendorclass(vendor, 0x0601);
122if (!sbdev)
123sbdev = pci_dev_find_vendorclass(vendor, 0x0680);
124if (!sbdev)
125sbdev = pci_dev_find_vendorclass(vendor, 0x0000);
126if (!sbdev)
127msg_perr("No southbridge found for %s!\n", name);
128if (sbdev)
129msg_pdbg("Found southbridge %04x:%04x at %02x:%02x:%01x\n",
130 sbdev->vendor_id, sbdev->device_id,
131 sbdev->bus, sbdev->dev, sbdev->func);
132return sbdev;
133}
134
135static int enable_flash_sis501(struct pci_dev *dev, const char *name)
136{
137uint8_t tmp;
138int ret = 0;
139struct pci_dev *sbdev;
140
141sbdev = find_southbridge(dev->vendor_id, name);
142if (!sbdev)
143return -1;
144
145ret = enable_flash_sis_mapping(sbdev, name);
146
147tmp = sio_read(0x22, 0x80);
148tmp &= (~0x20);
149tmp |= 0x4;
150sio_write(0x22, 0x80, tmp);
151
152tmp = sio_read(0x22, 0x70);
153tmp &= (~0x20);
154tmp |= 0x4;
155sio_write(0x22, 0x70, tmp);
156
157return ret;
158}
159
160static int enable_flash_sis5511(struct pci_dev *dev, const char *name)
161{
162uint8_t tmp;
163int ret = 0;
164struct pci_dev *sbdev;
165
166sbdev = find_southbridge(dev->vendor_id, name);
167if (!sbdev)
168return -1;
169
170ret = enable_flash_sis_mapping(sbdev, name);
171
172tmp = sio_read(0x22, 0x50);
173tmp &= (~0x20);
174tmp |= 0x4;
175sio_write(0x22, 0x50, tmp);
176
177return ret;
178}
179
180static int enable_flash_sis5x0(struct pci_dev *dev, const char *name, uint8_t dis_mask, uint8_t en_mask)
181{
182#define SIS_REG 0x45
183uint8_t new, newer;
184int ret = 0;
185struct pci_dev *sbdev;
186
187sbdev = find_southbridge(dev->vendor_id, name);
188if (!sbdev)
189return -1;
190
191ret = enable_flash_sis_mapping(sbdev, name);
192
193new = pci_read_byte(sbdev, SIS_REG);
194new &= (~dis_mask);
195new |= en_mask;
196rpci_write_byte(sbdev, SIS_REG, new);
197newer = pci_read_byte(sbdev, SIS_REG);
198if (newer != new) { /* FIXME: share this with other code? */
199msg_pinfo("Setting register 0x%x to 0x%02x on %s failed (WARNING ONLY).\n", SIS_REG, new, name);
200msg_pinfo("Stuck at 0x%02x\n", newer);
201ret = -1;
202}
203
204return ret;
205}
206
207static int enable_flash_sis530(struct pci_dev *dev, const char *name)
208{
209return enable_flash_sis5x0(dev, name, 0x20, 0x04);
210}
211
212static int enable_flash_sis540(struct pci_dev *dev, const char *name)
213{
214return enable_flash_sis5x0(dev, name, 0x80, 0x40);
215}
216
217/* Datasheet:
218 * - Name: 82371AB PCI-TO-ISA / IDE XCELERATOR (PIIX4)
219 * - URL: http://www.intel.com/design/intarch/datashts/290562.htm
220 * - PDF: http://www.intel.com/design/intarch/datashts/29056201.pdf
221 * - Order Number: 290562-001
222 */
223static int enable_flash_piix4(struct pci_dev *dev, const char *name)
224{
225uint16_t old, new;
226uint16_t xbcs = 0x4e;/* X-Bus Chip Select register. */
227
228internal_buses_supported = BUS_PARALLEL;
229
230old = pci_read_word(dev, xbcs);
231
232/* Set bit 9: 1-Meg Extended BIOS Enable (PCI master accesses to
233 * FFF00000-FFF7FFFF are forwarded to ISA).
234 * Note: This bit is reserved on PIIX/PIIX3/MPIIX.
235 * Set bit 7: Extended BIOS Enable (PCI master accesses to
236 * FFF80000-FFFDFFFF are forwarded to ISA).
237 * Set bit 6: Lower BIOS Enable (PCI master, or ISA master accesses to
238 * the lower 64-Kbyte BIOS block (E0000-EFFFF) at the top
239 * of 1 Mbyte, or the aliases at the top of 4 Gbyte
240 * (FFFE0000-FFFEFFFF) result in the generation of BIOSCS#.
241 * Note: Accesses to FFFF0000-FFFFFFFF are always forwarded to ISA.
242 * Set bit 2: BIOSCS# Write Enable (1=enable, 0=disable).
243 */
244if (dev->device_id == 0x122e || dev->device_id == 0x7000
245 || dev->device_id == 0x1234)
246new = old | 0x00c4; /* PIIX/PIIX3/MPIIX: Bit 9 is reserved. */
247else
248new = old | 0x02c4;
249
250if (new == old)
251return 0;
252
253rpci_write_word(dev, xbcs, new);
254
255if (pci_read_word(dev, xbcs) != new) { /* FIXME: share this with other code? */
256msg_pinfo("Setting register 0x%04x to 0x%04x on %s failed (WARNING ONLY).\n", xbcs, new, name);
257return -1;
258}
259
260return 0;
261}
262
263/* Handle BIOS_CNTL (aka. BCR). Disable locks and enable writes. The register can either be in PCI config space
264 * at the offset given by 'bios_cntl' or at the memory-mapped address 'addr'.
265 *
266 * Note: the ICH0-ICH5 BIOS_CNTL register is actually 16 bit wide, in Poulsbo, Tunnel Creek and other Atom
267 * chipsets/SoCs it is even 32b, but just treating it as 8 bit wide seems to work fine in practice. */
268static int enable_flash_ich_bios_cntl_common(enum ich_chipset ich_generation, void *addr,
269 struct pci_dev *dev, uint8_t bios_cntl)
270{
271uint8_t old, new, wanted;
272
273switch (ich_generation) {
274case CHIPSET_ICH_UNKNOWN:
275return ERROR_FATAL;
276/* Non-SPI-capable */
277case CHIPSET_ICH:
278case CHIPSET_ICH2345:
279break;
280/* Some Atom chipsets are special: The second byte of BIOS_CNTL (D9h) contains a prefetch bit similar to
281 * what other SPI-capable chipsets have at DCh. Others like Bay Trail use a memmapped register.
282 * The Tunnel Creek datasheet contains a lot of details about the SPI controller, among other things it
283 * mentions that the prefetching and caching does only happen for direct memory reads.
284 * Therefore - at least for Tunnel Creek - it should not matter to flashrom because we use the
285 * programmed access only and not memory mapping. */
286case CHIPSET_TUNNEL_CREEK:
287case CHIPSET_POULSBO:
288case CHIPSET_CENTERTON:
289old = pci_read_byte(dev, bios_cntl + 1);
290msg_pdbg("BIOS Prefetch Enable: %sabled, ", (old & 1) ? "en" : "dis");
291break;
292case CHIPSET_BAYTRAIL:
293case CHIPSET_ICH7:
294default: /* Future version might behave the same */
295if (ich_generation == CHIPSET_BAYTRAIL)
296old = (mmio_readl(addr) >> 2) & 0x3;
297else
298old = (pci_read_byte(dev, bios_cntl) >> 2) & 0x3;
299msg_pdbg("SPI Read Configuration: ");
300if (old == 3)
301msg_pdbg("invalid prefetching/caching settings, ");
302else
303msg_pdbg("prefetching %sabled, caching %sabled, ",
304 (old & 0x2) ? "en" : "dis",
305 (old & 0x1) ? "dis" : "en");
306}
307
308if (ich_generation == CHIPSET_BAYTRAIL)
309wanted = old = mmio_readl(addr);
310else
311wanted = old = pci_read_byte(dev, bios_cntl);
312
313/*
314 * Quote from the 6 Series datasheet (Document Number: 324645-004):
315 * "Bit 5: SMM BIOS Write Protect Disable (SMM_BWP)
316 * 1 = BIOS region SMM protection is enabled.
317 * The BIOS Region is not writable unless all processors are in SMM."
318 * In earlier chipsets this bit is reserved.
319 *
320 * Try to unset it in any case.
321 * It won't hurt and makes sense in some cases according to Stefan Reinauer.
322 *
323 * At least in Centerton aforementioned bit is located at bit 7. It is unspecified in all other Atom
324 * and Desktop chipsets before Ibex Peak/5 Series, but we reset bit 5 anyway.
325 */
326int smm_bwp_bit;
327if (ich_generation == CHIPSET_CENTERTON)
328smm_bwp_bit = 7;
329else
330smm_bwp_bit = 5;
331wanted &= ~(1 << smm_bwp_bit);
332
333/* Tunnel Creek has a cache disable at bit 2 of the lowest BIOS_CNTL byte. */
334if (ich_generation == CHIPSET_TUNNEL_CREEK)
335wanted |= (1 << 2);
336
337wanted |= (1 << 0); /* Set BIOS Write Enable */
338wanted &= ~(1 << 1); /* Disable lock (futile) */
339
340/* Only write the register if it's necessary */
341if (wanted != old) {
342if (ich_generation == CHIPSET_BAYTRAIL) {
343rmmio_writel(wanted, addr);
344new = mmio_readl(addr);
345} else {
346rpci_write_byte(dev, bios_cntl, wanted);
347new = pci_read_byte(dev, bios_cntl);
348}
349} else
350new = old;
351
352msg_pdbg("\nBIOS_CNTL = 0x%02x: ", new);
353msg_pdbg("BIOS Lock Enable: %sabled, ", (new & (1 << 1)) ? "en" : "dis");
354msg_pdbg("BIOS Write Enable: %sabled\n", (new & (1 << 0)) ? "en" : "dis");
355if (new & (1 << smm_bwp_bit))
356msg_pwarn("Warning: BIOS region SMM protection is enabled!\n");
357
358if (new != wanted)
359msg_pwarn("Warning: Setting Bios Control at 0x%x from 0x%02x to 0x%02x failed.\n"
360 "New value is 0x%02x.\n", bios_cntl, old, wanted, new);
361
362/* Return an error if we could not set the write enable only. */
363if (!(new & (1 << 0)))
364return -1;
365
366return 0;
367}
368
369static int enable_flash_ich_bios_cntl_config_space(struct pci_dev *dev, enum ich_chipset ich_generation,
370 uint8_t bios_cntl)
371{
372return enable_flash_ich_bios_cntl_common(ich_generation, NULL, dev, bios_cntl);
373}
374
375static int enable_flash_ich_bios_cntl_memmapped(enum ich_chipset ich_generation, void *addr)
376{
377return enable_flash_ich_bios_cntl_common(ich_generation, addr, NULL, 0);
378}
379
380static int enable_flash_ich_fwh_decode(struct pci_dev *dev, enum ich_chipset ich_generation)
381{
382uint8_t fwh_sel1 = 0, fwh_sel2 = 0, fwh_dec_en_lo = 0, fwh_dec_en_hi = 0; /* silence compilers */
383bool implemented = 0;
384void *ilb = NULL; /* Only for Baytrail */
385switch (ich_generation) {
386case CHIPSET_ICH:
387/* FIXME: Unlike later chipsets, ICH and ICH-0 do only support mapping of the top-most 4MB
388 * and therefore do only feature FWH_DEC_EN (E3h, different default too) and FWH_SEL (E8h). */
389break;
390case CHIPSET_ICH2345:
391fwh_sel1 = 0xe8;
392fwh_sel2 = 0xee;
393fwh_dec_en_lo = 0xf0;
394fwh_dec_en_hi = 0xe3;
395implemented = 1;
396break;
397case CHIPSET_POULSBO:
398case CHIPSET_TUNNEL_CREEK:
399/* FIXME: Similar to ICH and ICH-0, Tunnel Creek and Poulsbo do only feature one register each,
400 * FWH_DEC_EN (D7h) and FWH_SEL (D0h). */
401break;
402case CHIPSET_CENTERTON:
403/* FIXME: Similar to above FWH_DEC_EN (D4h) and FWH_SEL (D0h). */
404break;
405case CHIPSET_BAYTRAIL: {
406uint32_t ilb_base = pci_read_long(dev, 0x50) & 0xfffffe00; /* bits 31:9 */
407if (ilb_base == 0) {
408msg_perr("Error: Invalid ILB_BASE_ADDRESS\n");
409return ERROR_FATAL;
410}
411ilb = rphysmap("BYT IBASE", ilb_base, 512);
412fwh_sel1 = 0x18;
413fwh_dec_en_lo = 0xd8;
414fwh_dec_en_hi = 0xd9;
415implemented = 1;
416break;
417}
418case CHIPSET_ICH6:
419case CHIPSET_ICH7:
420default: /* Future version might behave the same */
421fwh_sel1 = 0xd0;
422fwh_sel2 = 0xd4;
423fwh_dec_en_lo = 0xd8;
424fwh_dec_en_hi = 0xd9;
425implemented = 1;
426break;
427}
428
429char *idsel = extract_programmer_param("fwh_idsel");
430if (idsel && strlen(idsel)) {
431if (!implemented) {
432msg_perr("Error: fwh_idsel= specified, but (yet) unsupported on this chipset.\n");
433goto idsel_garbage_out;
434}
435errno = 0;
436/* Base 16, nothing else makes sense. */
437uint64_t fwh_idsel = (uint64_t)strtoull(idsel, NULL, 16);
438if (errno) {
439msg_perr("Error: fwh_idsel= specified, but value could not be converted.\n");
440goto idsel_garbage_out;
441}
442uint64_t fwh_mask = 0xffffffff;
443if (fwh_sel2 > 0)
444fwh_mask |= (0xffffULL << 32);
445if (fwh_idsel & ~fwh_mask) {
446msg_perr("Error: fwh_idsel= specified, but value had unused bits set.\n");
447goto idsel_garbage_out;
448}
449uint64_t fwh_idsel_old;
450if (ich_generation == CHIPSET_BAYTRAIL) {
451fwh_idsel_old = mmio_readl(ilb + fwh_sel1);
452rmmio_writel(fwh_idsel, ilb + fwh_sel1);
453} else {
454fwh_idsel_old = (uint64_t)pci_read_long(dev, fwh_sel1) << 16;
455rpci_write_long(dev, fwh_sel1, (fwh_idsel >> 16) & 0xffffffff);
456if (fwh_sel2 > 0) {
457fwh_idsel_old |= pci_read_word(dev, fwh_sel2);
458rpci_write_word(dev, fwh_sel2, fwh_idsel & 0xffff);
459}
460}
461msg_pdbg("Setting IDSEL from 0x%012" PRIx64 " to 0x%012" PRIx64 " for top 16 MB.\n",
462 fwh_idsel_old, fwh_idsel);
463/* FIXME: Decode settings are not changed. */
464} else if (idsel) {
465msg_perr("Error: fwh_idsel= specified, but no value given.\n");
466idsel_garbage_out:
467free(idsel);
468return ERROR_FATAL;
469}
470free(idsel);
471
472if (!implemented) {
473msg_pdbg2("FWH IDSEL handling is not implemented on this chipset.\n");
474return 0;
475}
476
477/* Ignore all legacy ranges below 1 MB.
478 * We currently only support flashing the chip which responds to
479 * IDSEL=0. To support IDSEL!=0, flashbase and decode size calculations
480 * have to be adjusted.
481 */
482int max_decode_fwh_idsel = 0, max_decode_fwh_decode = 0;
483bool contiguous = 1;
484uint32_t fwh_conf;
485if (ich_generation == CHIPSET_BAYTRAIL)
486fwh_conf = mmio_readl(ilb + fwh_sel1);
487else
488fwh_conf = pci_read_long(dev, fwh_sel1);
489
490int i;
491/* FWH_SEL1 */
492for (i = 7; i >= 0; i--) {
493int tmp = (fwh_conf >> (i * 4)) & 0xf;
494msg_pdbg("0x%08x/0x%08x FWH IDSEL: 0x%x\n",
495 (0x1ff8 + i) * 0x80000,
496 (0x1ff0 + i) * 0x80000,
497 tmp);
498if ((tmp == 0) && contiguous) {
499max_decode_fwh_idsel = (8 - i) * 0x80000;
500} else {
501contiguous = 0;
502}
503}
504if (fwh_sel2 > 0) {
505/* FWH_SEL2 */
506fwh_conf = pci_read_word(dev, fwh_sel2);
507for (i = 3; i >= 0; i--) {
508int tmp = (fwh_conf >> (i * 4)) & 0xf;
509msg_pdbg("0x%08x/0x%08x FWH IDSEL: 0x%x\n",
510 (0xff4 + i) * 0x100000,
511 (0xff0 + i) * 0x100000,
512 tmp);
513if ((tmp == 0) && contiguous) {
514max_decode_fwh_idsel = (8 - i) * 0x100000;
515} else {
516contiguous = 0;
517}
518}
519}
520contiguous = 1;
521/* FWH_DEC_EN1 */
522fwh_conf = pci_read_byte(dev, fwh_dec_en_hi);
523fwh_conf <<= 8;
524fwh_conf |= pci_read_byte(dev, fwh_dec_en_lo);
525for (i = 7; i >= 0; i--) {
526int tmp = (fwh_conf >> (i + 0x8)) & 0x1;
527msg_pdbg("0x%08x/0x%08x FWH decode %sabled\n",
528 (0x1ff8 + i) * 0x80000,
529 (0x1ff0 + i) * 0x80000,
530 tmp ? "en" : "dis");
531if ((tmp == 1) && contiguous) {
532max_decode_fwh_decode = (8 - i) * 0x80000;
533} else {
534contiguous = 0;
535}
536}
537for (i = 3; i >= 0; i--) {
538int tmp = (fwh_conf >> i) & 0x1;
539msg_pdbg("0x%08x/0x%08x FWH decode %sabled\n",
540 (0xff4 + i) * 0x100000,
541 (0xff0 + i) * 0x100000,
542 tmp ? "en" : "dis");
543if ((tmp == 1) && contiguous) {
544max_decode_fwh_decode = (8 - i) * 0x100000;
545} else {
546contiguous = 0;
547}
548}
549max_rom_decode.fwh = min(max_decode_fwh_idsel, max_decode_fwh_decode);
550msg_pdbg("Maximum FWH chip size: 0x%x bytes\n", max_rom_decode.fwh);
551
552return 0;
553}
554
555static int enable_flash_ich_fwh(struct pci_dev *dev, enum ich_chipset ich_generation, uint8_t bios_cntl)
556{
557int err;
558
559/* Configure FWH IDSEL decoder maps. */
560if ((err = enable_flash_ich_fwh_decode(dev, ich_generation)) != 0)
561return err;
562
563internal_buses_supported = BUS_FWH;
564return enable_flash_ich_bios_cntl_config_space(dev, ich_generation, bios_cntl);
565}
566
567static int enable_flash_ich0(struct pci_dev *dev, const char *name)
568{
569return enable_flash_ich_fwh(dev, CHIPSET_ICH, 0x4e);
570}
571
572static int enable_flash_ich2345(struct pci_dev *dev, const char *name)
573{
574return enable_flash_ich_fwh(dev, CHIPSET_ICH2345, 0x4e);
575}
576
577static int enable_flash_ich6(struct pci_dev *dev, const char *name)
578{
579return enable_flash_ich_fwh(dev, CHIPSET_ICH6, 0xdc);
580}
581
582static int enable_flash_poulsbo(struct pci_dev *dev, const char *name)
583{
584return enable_flash_ich_fwh(dev, CHIPSET_POULSBO, 0xd8);
585}
586
587static void enable_flash_ich_handle_gcs(struct pci_dev *dev, enum ich_chipset ich_generation, uint32_t gcs, bool top_swap)
588{
589msg_pdbg("GCS = 0x%x: ", gcs);
590msg_pdbg("BIOS Interface Lock-Down: %sabled, ", (gcs & 0x1) ? "en" : "dis");
591
592static const char *const straps_names_EP80579[] = { "SPI", "reserved", "reserved", "LPC" };
593static const char *const straps_names_ich7_nm10[] = { "reserved", "SPI", "PCI", "LPC" };
594static const char *const straps_names_tunnel_creek[] = { "SPI", "LPC" };
595static const char *const straps_names_ich8910[] = { "SPI", "SPI", "PCI", "LPC" };
596static const char *const straps_names_pch567[] = { "LPC", "reserved", "PCI", "SPI" };
597static const char *const straps_names_pch89_baytrail[] = { "LPC", "reserved", "reserved", "SPI" };
598static const char *const straps_names_pch8_lp[] = { "SPI", "LPC" };
599static const char *const straps_names_unknown[] = { "unknown", "unknown", "unknown", "unknown" };
600
601const char *const *straps_names;
602switch (ich_generation) {
603case CHIPSET_ICH7:
604/* EP80579 may need further changes, but this is the least
605 * intrusive way to get correct BOOT Strap printing without
606 * changing the rest of its code path). */
607if (dev->device_id == 0x5031)
608straps_names = straps_names_EP80579;
609else
610straps_names = straps_names_ich7_nm10;
611break;
612case CHIPSET_ICH8:
613case CHIPSET_ICH9:
614case CHIPSET_ICH10:
615straps_names = straps_names_ich8910;
616break;
617case CHIPSET_TUNNEL_CREEK:
618straps_names = straps_names_tunnel_creek;
619break;
620case CHIPSET_5_SERIES_IBEX_PEAK:
621case CHIPSET_6_SERIES_COUGAR_POINT:
622case CHIPSET_7_SERIES_PANTHER_POINT:
623straps_names = straps_names_pch567;
624break;
625case CHIPSET_8_SERIES_LYNX_POINT:
626case CHIPSET_9_SERIES_WILDCAT_POINT:
627case CHIPSET_BAYTRAIL:
628straps_names = straps_names_pch89_baytrail;
629break;
630case CHIPSET_8_SERIES_LYNX_POINT_LP:
631straps_names = straps_names_pch8_lp;
632break;
633case CHIPSET_8_SERIES_WELLSBURG: // FIXME: check datasheet
634case CHIPSET_CENTERTON: // FIXME: Datasheet does not mention GCS at all
635straps_names = straps_names_unknown;
636break;
637default:
638msg_gerr("%s: unknown ICH generation. Please report!\n", __func__);
639straps_names = straps_names_unknown;
640break;
641}
642
643uint8_t bbs;
644switch (ich_generation) {
645case CHIPSET_TUNNEL_CREEK:
646bbs = (gcs >> 1) & 0x1;
647break;
648case CHIPSET_8_SERIES_LYNX_POINT_LP:
649/* Lynx Point LP uses a single bit for BBS */
650bbs = (gcs >> 10) & 0x1;
651break;
652default:
653/* Other chipsets use two bits for BBS */
654bbs = (gcs >> 10) & 0x3;
655break;
656}
657msg_pdbg("Boot BIOS Straps: 0x%x (%s)\n", bbs, straps_names[bbs]);
658
659/* Centerton has its TS bit in [GPE0BLK] + 0x30 while the exact location for Tunnel Creek is unknown. */
660if (ich_generation != CHIPSET_TUNNEL_CREEK && ich_generation != CHIPSET_CENTERTON)
661msg_pdbg("Top Swap: %s\n", (top_swap) ? "enabled (A16(+) inverted)" : "not enabled");
662}
663
664static int enable_flash_ich_spi(struct pci_dev *dev, enum ich_chipset ich_generation, uint8_t bios_cntl)
665{
666
667/* Get physical address of Root Complex Register Block */
668uint32_t rcra = pci_read_long(dev, 0xf0) & 0xffffc000;
669msg_pdbg("Root Complex Register Block address = 0x%x\n", rcra);
670
671/* Map RCBA to virtual memory */
672void *rcrb = rphysmap("ICH RCRB", rcra, 0x4000);
673if (rcrb == ERROR_PTR)
674return ERROR_FATAL;
675
676enable_flash_ich_handle_gcs(dev, ich_generation, mmio_readl(rcrb + 0x3410), mmio_readb(rcrb + 0x3414));
677
678/* Handle FWH-related parameters and initialization */
679int ret_fwh = enable_flash_ich_fwh(dev, ich_generation, bios_cntl);
680if (ret_fwh == ERROR_FATAL)
681return ret_fwh;
682
683/* SPIBAR is at RCRB+0x3020 for ICH[78], Tunnel Creek and Centerton, and RCRB+0x3800 for ICH9. */
684uint16_t spibar_offset;
685switch (ich_generation) {
686case CHIPSET_BAYTRAIL:
687case CHIPSET_ICH_UNKNOWN:
688return ERROR_FATAL;
689case CHIPSET_ICH7:
690case CHIPSET_ICH8:
691case CHIPSET_TUNNEL_CREEK:
692case CHIPSET_CENTERTON:
693spibar_offset = 0x3020;
694break;
695case CHIPSET_ICH9:
696default:/* Future version might behave the same */
697spibar_offset = 0x3800;
698break;
699}
700msg_pdbg("SPIBAR = 0x%0*" PRIxPTR " + 0x%04x\n", PRIxPTR_WIDTH, (uintptr_t)rcrb, spibar_offset);
701void *spibar = rcrb + spibar_offset;
702
703/* This adds BUS_SPI */
704int ret_spi = ich_init_spi(dev, spibar, ich_generation);
705if (ret_spi == ERROR_FATAL)
706return ret_spi;
707
708if (ret_fwh || ret_spi)
709return ERROR_NONFATAL;
710
711return 0;
712}
713
714static int enable_flash_tunnelcreek(struct pci_dev *dev, const char *name)
715{
716return enable_flash_ich_spi(dev, CHIPSET_TUNNEL_CREEK, 0xd8);
717}
718
719static int enable_flash_s12x0(struct pci_dev *dev, const char *name)
720{
721return enable_flash_ich_spi(dev, CHIPSET_CENTERTON, 0xd8);
722}
723
724static int enable_flash_ich7(struct pci_dev *dev, const char *name)
725{
726return enable_flash_ich_spi(dev, CHIPSET_ICH7, 0xdc);
727}
728
729static int enable_flash_ich8(struct pci_dev *dev, const char *name)
730{
731return enable_flash_ich_spi(dev, CHIPSET_ICH8, 0xdc);
732}
733
734static int enable_flash_ich9(struct pci_dev *dev, const char *name)
735{
736return enable_flash_ich_spi(dev, CHIPSET_ICH9, 0xdc);
737}
738
739static int enable_flash_ich10(struct pci_dev *dev, const char *name)
740{
741return enable_flash_ich_spi(dev, CHIPSET_ICH10, 0xdc);
742}
743
744/* Ibex Peak aka. 5 series & 3400 series */
745static int enable_flash_pch5(struct pci_dev *dev, const char *name)
746{
747return enable_flash_ich_spi(dev, CHIPSET_5_SERIES_IBEX_PEAK, 0xdc);
748}
749
750/* Cougar Point aka. 6 series & c200 series */
751static int enable_flash_pch6(struct pci_dev *dev, const char *name)
752{
753return enable_flash_ich_spi(dev, CHIPSET_6_SERIES_COUGAR_POINT, 0xdc);
754}
755
756/* Panther Point aka. 7 series */
757static int enable_flash_pch7(struct pci_dev *dev, const char *name)
758{
759return enable_flash_ich_spi(dev, CHIPSET_7_SERIES_PANTHER_POINT, 0xdc);
760}
761
762/* Lynx Point aka. 8 series */
763static int enable_flash_pch8(struct pci_dev *dev, const char *name)
764{
765return enable_flash_ich_spi(dev, CHIPSET_8_SERIES_LYNX_POINT, 0xdc);
766}
767
768/* Lynx Point LP aka. 8 series low-power */
769static int enable_flash_pch8_lp(struct pci_dev *dev, const char *name)
770{
771return enable_flash_ich_spi(dev, CHIPSET_8_SERIES_LYNX_POINT_LP, 0xdc);
772}
773
774/* Wellsburg (for Haswell-EP Xeons) */
775static int enable_flash_pch8_wb(struct pci_dev *dev, const char *name)
776{
777return enable_flash_ich_spi(dev, CHIPSET_8_SERIES_WELLSBURG, 0xdc);
778}
779
780/* Wildcat Point */
781static int enable_flash_pch9(struct pci_dev *dev, const char *name)
782{
783return enable_flash_ich_spi(dev, CHIPSET_9_SERIES_WILDCAT_POINT, 0xdc);
784}
785
786/* Silvermont architecture: Bay Trail(-T/-I), Avoton/Rangeley.
787 * These have a distinctly different behavior compared to other Intel chipsets and hence are handled separately.
788 *
789 * Differences include:
790 *- RCBA at LPC config 0xF0 too but mapped range is only 4 B long instead of 16 kB.
791 *- GCS at [RCRB] + 0 (instead of [RCRB] + 0x3410).
792 *- TS (Top Swap) in GCS (instead of [RCRB] + 0x3414).
793 *- SPIBAR (coined SBASE) at LPC config 0x54 (instead of [RCRB] + 0x3800).
794 *- BIOS_CNTL (coined BCR) at [SPIBAR] + 0xFC (instead of LPC config 0xDC).
795 */
796static int enable_flash_silvermont(struct pci_dev *dev, const char *name)
797{
798enum ich_chipset ich_generation = CHIPSET_BAYTRAIL;
799
800/* Get physical address of Root Complex Register Block */
801uint32_t rcba = pci_read_long(dev, 0xf0) & 0xfffffc00;
802msg_pdbg("Root Complex Register Block address = 0x%x\n", rcba);
803
804/* Handle GCS (in RCRB) */
805void *rcrb = physmap("BYT RCRB", rcba, 4);
806uint32_t gcs = mmio_readl(rcrb + 0);
807enable_flash_ich_handle_gcs(dev, ich_generation, gcs, gcs & 0x2);
808physunmap(rcrb, 4);
809
810/* Handle fwh_idsel parameter */
811int ret_fwh = enable_flash_ich_fwh_decode(dev, ich_generation);
812if (ret_fwh == ERROR_FATAL)
813return ret_fwh;
814
815internal_buses_supported = BUS_FWH;
816
817/* Get physical address of SPI Base Address and map it */
818uint32_t sbase = pci_read_long(dev, 0x54) & 0xfffffe00;
819msg_pdbg("SPI_BASE_ADDRESS = 0x%x\n", sbase);
820void *spibar = rphysmap("BYT SBASE", sbase, 512); /* Last defined address on Bay Trail is 0x100 */
821
822/* Enable Flash Writes.
823 * Silvermont-based: BCR at SBASE + 0xFC (some bits of BCR are also accessible via BC at IBASE + 0x1C).
824 */
825enable_flash_ich_bios_cntl_memmapped(ich_generation, spibar + 0xFC);
826
827int ret_spi = ich_init_spi(dev, spibar, ich_generation);
828if (ret_spi == ERROR_FATAL)
829return ret_spi;
830
831if (ret_fwh || ret_spi)
832return ERROR_NONFATAL;
833
834return 0;
835}
836
837static int via_no_byte_merge(struct pci_dev *dev, const char *name)
838{
839uint8_t val;
840
841val = pci_read_byte(dev, 0x71);
842if (val & 0x40) {
843msg_pdbg("Disabling byte merging\n");
844val &= ~0x40;
845rpci_write_byte(dev, 0x71, val);
846}
847return NOT_DONE_YET;/* need to find south bridge, too */
848}
849
850static int enable_flash_vt823x(struct pci_dev *dev, const char *name)
851{
852uint8_t val;
853
854/* Enable ROM decode range (1MB) FFC00000 - FFFFFFFF. */
855rpci_write_byte(dev, 0x41, 0x7f);
856
857/* ROM write enable */
858val = pci_read_byte(dev, 0x40);
859val |= 0x10;
860rpci_write_byte(dev, 0x40, val);
861
862if (pci_read_byte(dev, 0x40) != val) {
863msg_pwarn("\nWarning: Failed to enable flash write on \"%s\"\n", name);
864return -1;
865}
866
867if (dev->device_id == 0x3227) { /* VT8237/VT8237R */
868/* All memory cycles, not just ROM ones, go to LPC. */
869val = pci_read_byte(dev, 0x59);
870val &= ~0x80;
871rpci_write_byte(dev, 0x59, val);
872}
873
874return 0;
875}
876
877static int enable_flash_vt_vx(struct pci_dev *dev, const char *name)
878{
879struct pci_dev *south_north = pci_dev_find(0x1106, 0xa353);
880if (south_north == NULL) {
881msg_perr("Could not find South-North Module Interface Control device!\n");
882return ERROR_FATAL;
883}
884
885msg_pdbg("Strapped to ");
886if ((pci_read_byte(south_north, 0x56) & 0x01) == 0) {
887msg_pdbg("LPC.\n");
888return enable_flash_vt823x(dev, name);
889}
890msg_pdbg("SPI.\n");
891
892uint32_t mmio_base;
893void *mmio_base_physmapped;
894uint32_t spi_cntl;
895#define SPI_CNTL_LEN 0x08
896uint32_t spi0_mm_base = 0;
897switch(dev->device_id) {
898case 0x8353: /* VX800/VX820 */
899spi0_mm_base = pci_read_long(dev, 0xbc) << 8;
900break;
901case 0x8409: /* VX855/VX875 */
902case 0x8410: /* VX900 */
903mmio_base = pci_read_long(dev, 0xbc) << 8;
904mmio_base_physmapped = physmap("VIA VX MMIO register", mmio_base, SPI_CNTL_LEN);
905if (mmio_base_physmapped == ERROR_PTR)
906return ERROR_FATAL;
907
908/* Offset 0 - Bit 0 holds SPI Bus0 Enable Bit. */
909spi_cntl = mmio_readl(mmio_base_physmapped) + 0x00;
910if ((spi_cntl & 0x01) == 0) {
911msg_pdbg ("SPI Bus0 disabled!\n");
912physunmap(mmio_base_physmapped, SPI_CNTL_LEN);
913return ERROR_FATAL;
914}
915/* Offset 1-3 has SPI Bus Memory Map Base Address: */
916spi0_mm_base = spi_cntl & 0xFFFFFF00;
917
918/* Offset 4 - Bit 0 holds SPI Bus1 Enable Bit. */
919spi_cntl = mmio_readl(mmio_base_physmapped) + 0x04;
920if ((spi_cntl & 0x01) == 1)
921msg_pdbg2("SPI Bus1 is enabled too.\n");
922
923physunmap(mmio_base_physmapped, SPI_CNTL_LEN);
924break;
925default:
926msg_perr("%s: Unsupported chipset %x:%x!\n", __func__, dev->vendor_id, dev->device_id);
927return ERROR_FATAL;
928}
929
930return via_init_spi(dev, spi0_mm_base);
931}
932
933static int enable_flash_vt8237s_spi(struct pci_dev *dev, const char *name)
934{
935return via_init_spi(dev, pci_read_long(dev, 0xbc) << 8);
936}
937
938static int enable_flash_cs5530(struct pci_dev *dev, const char *name)
939{
940uint8_t reg8;
941
942#define DECODE_CONTROL_REG20x5b/* F0 index 0x5b */
943#define ROM_AT_LOGIC_CONTROL_REG0x52/* F0 index 0x52 */
944#define CS5530_RESET_CONTROL_REG0x44/* F0 index 0x44 */
945#define CS5530_USB_SHADOW_REG0x43/* F0 index 0x43 */
946
947#define LOWER_ROM_ADDRESS_RANGE(1 << 0)
948#define ROM_WRITE_ENABLE(1 << 1)
949#define UPPER_ROM_ADDRESS_RANGE(1 << 2)
950#define BIOS_ROM_POSITIVE_DECODE(1 << 5)
951#define CS5530_ISA_MASTER(1 << 7)
952#define CS5530_ENABLE_SA2320(1 << 2)
953#define CS5530_ENABLE_SA20(1 << 6)
954
955internal_buses_supported = BUS_PARALLEL;
956/* Decode 0x000E0000-0x000FFFFF (128 kB), not just 64 kB, and
957 * decode 0xFF000000-0xFFFFFFFF (16 MB), not just 256 kB.
958 * FIXME: Should we really touch the low mapping below 1 MB? Flashrom
959 * ignores that region completely.
960 * Make the configured ROM areas writable.
961 */
962reg8 = pci_read_byte(dev, ROM_AT_LOGIC_CONTROL_REG);
963reg8 |= LOWER_ROM_ADDRESS_RANGE;
964reg8 |= UPPER_ROM_ADDRESS_RANGE;
965reg8 |= ROM_WRITE_ENABLE;
966rpci_write_byte(dev, ROM_AT_LOGIC_CONTROL_REG, reg8);
967
968/* Set positive decode on ROM. */
969reg8 = pci_read_byte(dev, DECODE_CONTROL_REG2);
970reg8 |= BIOS_ROM_POSITIVE_DECODE;
971rpci_write_byte(dev, DECODE_CONTROL_REG2, reg8);
972
973reg8 = pci_read_byte(dev, CS5530_RESET_CONTROL_REG);
974if (reg8 & CS5530_ISA_MASTER) {
975/* We have A0-A23 available. */
976max_rom_decode.parallel = 16 * 1024 * 1024;
977} else {
978reg8 = pci_read_byte(dev, CS5530_USB_SHADOW_REG);
979if (reg8 & CS5530_ENABLE_SA2320) {
980/* We have A0-19, A20-A23 available. */
981max_rom_decode.parallel = 16 * 1024 * 1024;
982} else if (reg8 & CS5530_ENABLE_SA20) {
983/* We have A0-19, A20 available. */
984max_rom_decode.parallel = 2 * 1024 * 1024;
985} else {
986/* A20 and above are not active. */
987max_rom_decode.parallel = 1024 * 1024;
988}
989}
990
991return 0;
992}
993
994/*
995 * Geode systems write protect the BIOS via RCONFs (cache settings similar
996 * to MTRRs). To unlock, change MSR 0x1808 top byte to 0x22.
997 *
998 * Geode systems also write protect the NOR flash chip itself via MSR_NORF_CTL.
999 * To enable write to NOR Boot flash for the benefit of systems that have such
1000 * a setup, raise MSR 0x51400018 WE_CS3 (write enable Boot Flash Chip Select).
1001 */
1002static int enable_flash_cs5536(struct pci_dev *dev, const char *name)
1003{
1004#define MSR_RCONF_DEFAULT0x1808
1005#define MSR_NORF_CTL0x51400018
1006
1007msr_t msr;
1008
1009/* Geode only has a single core */
1010if (setup_cpu_msr(0))
1011return -1;
1012
1013msr = rdmsr(MSR_RCONF_DEFAULT);
1014if ((msr.hi >> 24) != 0x22) {
1015msr.hi &= 0xfbffffff;
1016wrmsr(MSR_RCONF_DEFAULT, msr);
1017}
1018
1019msr = rdmsr(MSR_NORF_CTL);
1020/* Raise WE_CS3 bit. */
1021msr.lo |= 0x08;
1022wrmsr(MSR_NORF_CTL, msr);
1023
1024cleanup_cpu_msr();
1025
1026#undef MSR_RCONF_DEFAULT
1027#undef MSR_NORF_CTL
1028return 0;
1029}
1030
1031static int enable_flash_sc1100(struct pci_dev *dev, const char *name)
1032{
1033#define SC_REG 0x52
1034uint8_t new;
1035
1036rpci_write_byte(dev, SC_REG, 0xee);
1037
1038new = pci_read_byte(dev, SC_REG);
1039
1040if (new != 0xee) { /* FIXME: share this with other code? */
1041msg_pinfo("Setting register 0x%x to 0x%02x on %s failed (WARNING ONLY).\n", SC_REG, new, name);
1042return -1;
1043}
1044
1045return 0;
1046}
1047
1048/* Works for AMD-768, AMD-8111, VIA VT82C586A/B, VIA VT82C596, VIA VT82C686A/B.
1049 *
1050 * ROM decode control register matrix
1051 * AMD-768AMD-8111VT82C586A/BVT82C596VT82C686A/B
1052 * 7FFC0_0000h–FFFF_FFFFh<-FFFE0000h-FFFEFFFFh<-<-
1053 * 6FFB0_0000h–FFBF_FFFFh<-FFF80000h-FFFDFFFFh<-<-
1054 * 500E8...<-<-FFF00000h-FFF7FFFFh<-
1055 */
1056static int enable_flash_amd_via(struct pci_dev *dev, const char *name, uint8_t decode_val)
1057{
1058#define AMD_MAPREG 0x43
1059#define AMD_ENREG 0x40
1060uint8_t old, new;
1061
1062old = pci_read_byte(dev, AMD_MAPREG);
1063new = old | decode_val;
1064if (new != old) {
1065rpci_write_byte(dev, AMD_MAPREG, new);
1066if (pci_read_byte(dev, AMD_MAPREG) != new) {
1067msg_pwarn("Setting register 0x%x to 0x%02x on %s failed (WARNING ONLY).\n",
1068 AMD_MAPREG, new, name);
1069} else
1070msg_pdbg("Changed ROM decode range to 0x%02x successfully.\n", new);
1071}
1072
1073/* Enable 'ROM write' bit. */
1074old = pci_read_byte(dev, AMD_ENREG);
1075new = old | 0x01;
1076if (new == old)
1077return 0;
1078rpci_write_byte(dev, AMD_ENREG, new);
1079
1080if (pci_read_byte(dev, AMD_ENREG) != new) {
1081msg_pwarn("Setting register 0x%x to 0x%02x on %s failed (WARNING ONLY).\n",
1082 AMD_ENREG, new, name);
1083return ERROR_NONFATAL;
1084}
1085msg_pdbg2("Set ROM enable bit successfully.\n");
1086
1087return 0;
1088}
1089
1090static int enable_flash_amd_768_8111(struct pci_dev *dev, const char *name)
1091{
1092/* Enable decoding of 0xFFB00000 to 0xFFFFFFFF (5 MB). */
1093max_rom_decode.lpc = 5 * 1024 * 1024;
1094return enable_flash_amd_via(dev, name, 0xC0);
1095}
1096
1097static int enable_flash_vt82c586(struct pci_dev *dev, const char *name)
1098{
1099/* Enable decoding of 0xFFF80000 to 0xFFFFFFFF. (512 kB) */
1100max_rom_decode.parallel = 512 * 1024;
1101return enable_flash_amd_via(dev, name, 0xC0);
1102}
1103
1104/* Works for VT82C686A/B too. */
1105static int enable_flash_vt82c596(struct pci_dev *dev, const char *name)
1106{
1107/* Enable decoding of 0xFFF00000 to 0xFFFFFFFF. (1 MB) */
1108max_rom_decode.parallel = 1024 * 1024;
1109return enable_flash_amd_via(dev, name, 0xE0);
1110}
1111
1112static int enable_flash_sb600(struct pci_dev *dev, const char *name)
1113{
1114uint32_t prot;
1115uint8_t reg;
1116int ret;
1117
1118/* Clear ROM protect 0-3. */
1119for (reg = 0x50; reg < 0x60; reg += 4) {
1120prot = pci_read_long(dev, reg);
1121/* No protection flags for this region?*/
1122if ((prot & 0x3) == 0)
1123continue;
1124msg_pdbg("Chipset %s%sprotected flash from 0x%08x to 0x%08x, unlocking...",
1125 (prot & 0x2) ? "read " : "",
1126 (prot & 0x1) ? "write " : "",
1127 (prot & 0xfffff800),
1128 (prot & 0xfffff800) + (((prot & 0x7fc) << 8) | 0x3ff));
1129prot &= 0xfffffffc;
1130rpci_write_byte(dev, reg, prot);
1131prot = pci_read_long(dev, reg);
1132if ((prot & 0x3) != 0) {
1133msg_perr("Disabling %s%sprotection of flash addresses from 0x%08x to 0x%08x failed.\n",
1134 (prot & 0x2) ? "read " : "",
1135 (prot & 0x1) ? "write " : "",
1136 (prot & 0xfffff800),
1137 (prot & 0xfffff800) + (((prot & 0x7fc) << 8) | 0x3ff));
1138continue;
1139}
1140msg_pdbg("done.\n");
1141}
1142
1143internal_buses_supported = BUS_LPC | BUS_FWH;
1144
1145ret = sb600_probe_spi(dev);
1146
1147/* Read ROM strap override register. */
1148OUTB(0x8f, 0xcd6);
1149reg = INB(0xcd7);
1150reg &= 0x0e;
1151msg_pdbg("ROM strap override is %sactive", (reg & 0x02) ? "" : "not ");
1152if (reg & 0x02) {
1153switch ((reg & 0x0c) >> 2) {
1154case 0x00:
1155msg_pdbg(": LPC");
1156break;
1157case 0x01:
1158msg_pdbg(": PCI");
1159break;
1160case 0x02:
1161msg_pdbg(": FWH");
1162break;
1163case 0x03:
1164msg_pdbg(": SPI");
1165break;
1166}
1167}
1168msg_pdbg("\n");
1169
1170/* Force enable SPI ROM in SB600 PM register.
1171 * If we enable SPI ROM here, we have to disable it after we leave.
1172 * But how can we know which ROM we are going to handle? So we have
1173 * to trade off. We only access LPC ROM if we boot via LPC ROM. And
1174 * only SPI ROM if we boot via SPI ROM. If you want to access SPI on
1175 * boards with LPC straps, you have to use the code below.
1176 */
1177/*
1178OUTB(0x8f, 0xcd6);
1179OUTB(0x0e, 0xcd7);
1180*/
1181
1182return ret;
1183}
1184
1185/* sets bit 0 in 0x6d */
1186static int enable_flash_nvidia_common(struct pci_dev *dev, const char *name)
1187{
1188uint8_t old, new;
1189
1190old = pci_read_byte(dev, 0x6d);
1191new = old | 0x01;
1192if (new == old)
1193return 0;
1194
1195rpci_write_byte(dev, 0x6d, new);
1196if (pci_read_byte(dev, 0x6d) != new) {
1197msg_pinfo("Setting register 0x6d to 0x%02x on %s failed.\n", new, name);
1198return 1;
1199}
1200return 0;
1201}
1202
1203static int enable_flash_nvidia_nforce2(struct pci_dev *dev, const char *name)
1204{
1205rpci_write_byte(dev, 0x92, 0);
1206if (enable_flash_nvidia_common(dev, name))
1207return ERROR_NONFATAL;
1208else
1209return 0;
1210}
1211
1212static int enable_flash_ck804(struct pci_dev *dev, const char *name)
1213{
1214uint32_t segctrl;
1215uint8_t reg, old, new;
1216unsigned int err = 0;
1217
1218/* 0x8A is special: it is a single byte and only one nibble is touched. */
1219reg = 0x8A;
1220segctrl = pci_read_byte(dev, reg);
1221if ((segctrl & 0x3) != 0x0) {
1222if ((segctrl & 0xC) != 0x0) {
1223msg_pinfo("Can not unlock existing protection in register 0x%02x.\n", reg);
1224err++;
1225} else {
1226msg_pdbg("Unlocking protection in register 0x%02x... ", reg);
1227rpci_write_byte(dev, reg, segctrl & 0xF0);
1228
1229segctrl = pci_read_byte(dev, reg);
1230if ((segctrl & 0x3) != 0x0) {
1231msg_pinfo("Could not unlock protection in register 0x%02x (new value: 0x%x).\n",
1232 reg, segctrl);
1233err++;
1234} else
1235msg_pdbg("OK\n");
1236}
1237}
1238
1239for (reg = 0x8C; reg <= 0x94; reg += 4) {
1240segctrl = pci_read_long(dev, reg);
1241if ((segctrl & 0x33333333) == 0x00000000) {
1242/* reads and writes are unlocked */
1243continue;
1244}
1245if ((segctrl & 0xCCCCCCCC) != 0x00000000) {
1246msg_pinfo("Can not unlock existing protection in register 0x%02x.\n", reg);
1247err++;
1248continue;
1249}
1250msg_pdbg("Unlocking protection in register 0x%02x... ", reg);
1251rpci_write_long(dev, reg, 0x00000000);
1252
1253segctrl = pci_read_long(dev, reg);
1254if ((segctrl & 0x33333333) != 0x00000000) {
1255msg_pinfo("Could not unlock protection in register 0x%02x (new value: 0x%08x).\n",
1256 reg, segctrl);
1257err++;
1258} else
1259msg_pdbg("OK\n");
1260}
1261
1262if (err > 0) {
1263msg_pinfo("%d locks could not be disabled, disabling writes (reads may also fail).\n", err);
1264programmer_may_write = 0;
1265}
1266
1267reg = 0x88;
1268old = pci_read_byte(dev, reg);
1269new = old | 0xC0;
1270if (new != old) {
1271rpci_write_byte(dev, reg, new);
1272if (pci_read_byte(dev, reg) != new) { /* FIXME: share this with other code? */
1273msg_pinfo("Setting register 0x%02x to 0x%02x on %s failed.\n", reg, new, name);
1274err++;
1275}
1276}
1277
1278if (enable_flash_nvidia_common(dev, name))
1279err++;
1280
1281if (err > 0)
1282return ERROR_NONFATAL;
1283else
1284return 0;
1285}
1286
1287static int enable_flash_osb4(struct pci_dev *dev, const char *name)
1288{
1289uint8_t tmp;
1290
1291internal_buses_supported = BUS_PARALLEL;
1292
1293tmp = INB(0xc06);
1294tmp |= 0x1;
1295OUTB(tmp, 0xc06);
1296
1297tmp = INB(0xc6f);
1298tmp |= 0x40;
1299OUTB(tmp, 0xc6f);
1300
1301return 0;
1302}
1303
1304/* ATI Technologies Inc IXP SB400 PCI-ISA Bridge (rev 80) */
1305static int enable_flash_sb400(struct pci_dev *dev, const char *name)
1306{
1307uint8_t tmp;
1308struct pci_dev *smbusdev;
1309
1310/* Look for the SMBus device. */
1311smbusdev = pci_dev_find(0x1002, 0x4372);
1312
1313if (!smbusdev) {
1314msg_perr("ERROR: SMBus device not found. Aborting.\n");
1315return ERROR_FATAL;
1316}
1317
1318/* Enable some SMBus stuff. */
1319tmp = pci_read_byte(smbusdev, 0x79);
1320tmp |= 0x01;
1321rpci_write_byte(smbusdev, 0x79, tmp);
1322
1323/* Change southbridge. */
1324tmp = pci_read_byte(dev, 0x48);
1325tmp |= 0x21;
1326rpci_write_byte(dev, 0x48, tmp);
1327
1328/* Now become a bit silly. */
1329tmp = INB(0xc6f);
1330OUTB(tmp, 0xeb);
1331OUTB(tmp, 0xeb);
1332tmp |= 0x40;
1333OUTB(tmp, 0xc6f);
1334OUTB(tmp, 0xeb);
1335OUTB(tmp, 0xeb);
1336
1337return 0;
1338}
1339
1340static int enable_flash_mcp55(struct pci_dev *dev, const char *name)
1341{
1342uint8_t val;
1343uint16_t wordval;
1344
1345/* Set the 0-16 MB enable bits. */
1346val = pci_read_byte(dev, 0x88);
1347val |= 0xff;/* 256K */
1348rpci_write_byte(dev, 0x88, val);
1349val = pci_read_byte(dev, 0x8c);
1350val |= 0xff;/* 1M */
1351rpci_write_byte(dev, 0x8c, val);
1352wordval = pci_read_word(dev, 0x90);
1353wordval |= 0x7fff;/* 16M */
1354rpci_write_word(dev, 0x90, wordval);
1355
1356if (enable_flash_nvidia_common(dev, name))
1357return ERROR_NONFATAL;
1358else
1359return 0;
1360}
1361
1362/*
1363 * The MCP6x/MCP7x code is based on cleanroom reverse engineering.
1364 * It is assumed that LPC chips need the MCP55 code and SPI chips need the
1365 * code provided in enable_flash_mcp6x_7x_common.
1366 */
1367static int enable_flash_mcp6x_7x(struct pci_dev *dev, const char *name)
1368{
1369int ret = 0, want_spi = 0;
1370uint8_t val;
1371
1372/* dev is the ISA bridge. No idea what the stuff below does. */
1373val = pci_read_byte(dev, 0x8a);
1374msg_pdbg("ISA/LPC bridge reg 0x8a contents: 0x%02x, bit 6 is %i, bit 5 "
1375 "is %i\n", val, (val >> 6) & 0x1, (val >> 5) & 0x1);
1376
1377switch ((val >> 5) & 0x3) {
1378case 0x0:
1379ret = enable_flash_mcp55(dev, name);
1380internal_buses_supported = BUS_LPC;
1381msg_pdbg("Flash bus type is LPC\n");
1382break;
1383case 0x2:
1384want_spi = 1;
1385/* SPI is added in mcp6x_spi_init if it works.
1386 * Do we really want to disable LPC in this case?
1387 */
1388internal_buses_supported = BUS_NONE;
1389msg_pdbg("Flash bus type is SPI\n");
1390break;
1391default:
1392/* Should not happen. */
1393internal_buses_supported = BUS_NONE;
1394msg_pwarn("Flash bus type is unknown (none)\n");
1395msg_pinfo("Please send the log files created by \"flashrom -p internal -o logfile\" to \n"
1396 "flashrom@flashrom.org with \"your board name: flashrom -V\" as the subject to\n"
1397 "help us finish support for your chipset. Thanks.\n");
1398return ERROR_NONFATAL;
1399}
1400
1401/* Force enable SPI and disable LPC? Not a good idea. */
1402#if 0
1403val |= (1 << 6);
1404val &= ~(1 << 5);
1405rpci_write_byte(dev, 0x8a, val);
1406#endif
1407
1408if (mcp6x_spi_init(want_spi))
1409ret = 1;
1410
1411return ret;
1412}
1413
1414static int enable_flash_ht1000(struct pci_dev *dev, const char *name)
1415{
1416uint8_t val;
1417
1418/* Set the 4MB enable bit. */
1419val = pci_read_byte(dev, 0x41);
1420val |= 0x0e;
1421rpci_write_byte(dev, 0x41, val);
1422
1423val = pci_read_byte(dev, 0x43);
1424val |= (1 << 4);
1425rpci_write_byte(dev, 0x43, val);
1426
1427return 0;
1428}
1429
1430/*
1431 * Usually on the x86 architectures (and on other PC-like platforms like some
1432 * Alphas or Itanium) the system flash is mapped right below 4G. On the AMD
1433 * Elan SC520 only a small piece of the system flash is mapped there, but the
1434 * complete flash is mapped somewhere below 1G. The position can be determined
1435 * by the BOOTCS PAR register.
1436 */
1437static int get_flashbase_sc520(struct pci_dev *dev, const char *name)
1438{
1439int i, bootcs_found = 0;
1440uint32_t parx = 0;
1441void *mmcr;
1442
1443/* 1. Map MMCR */
1444mmcr = physmap("Elan SC520 MMCR", 0xfffef000, getpagesize());
1445if (mmcr == ERROR_PTR)
1446return ERROR_FATAL;
1447
1448/* 2. Scan PAR0 (0x88) - PAR15 (0xc4) for
1449 * BOOTCS region (PARx[31:29] = 100b)e
1450 */
1451for (i = 0x88; i <= 0xc4; i += 4) {
1452parx = mmio_readl(mmcr + i);
1453if ((parx >> 29) == 4) {
1454bootcs_found = 1;
1455break; /* BOOTCS found */
1456}
1457}
1458
1459/* 3. PARx[25] = 1b --> flashbase[29:16] = PARx[13:0]
1460 * PARx[25] = 0b --> flashbase[29:12] = PARx[17:0]
1461 */
1462if (bootcs_found) {
1463if (parx & (1 << 25)) {
1464parx &= (1 << 14) - 1; /* Mask [13:0] */
1465flashbase = parx << 16;
1466} else {
1467parx &= (1 << 18) - 1; /* Mask [17:0] */
1468flashbase = parx << 12;
1469}
1470} else {
1471msg_pinfo("AMD Elan SC520 detected, but no BOOTCS. "
1472 "Assuming flash at 4G.\n");
1473}
1474
1475/* 4. Clean up */
1476physunmap(mmcr, getpagesize());
1477return 0;
1478}
1479
1480#endif
1481
1482/* Please keep this list numerically sorted by vendor/device ID. */
1483const struct penable chipset_enables[] = {
1484#if defined(__i386__) || defined(__x86_64__)
1485{0x1002, 0x4377, OK, "ATI", "SB400",enable_flash_sb400},
1486{0x1002, 0x438d, OK, "AMD", "SB600",enable_flash_sb600},
1487{0x1002, 0x439d, OK, "AMD", "SB7x0/SB8x0/SB9x0",enable_flash_sb600},
1488{0x100b, 0x0510, NT, "AMD", "SC1100",enable_flash_sc1100},
1489{0x1022, 0x2080, OK, "AMD", "CS5536",enable_flash_cs5536},
1490{0x1022, 0x2090, OK, "AMD", "CS5536",enable_flash_cs5536},
1491{0x1022, 0x3000, OK, "AMD", "Elan SC520",get_flashbase_sc520},
1492{0x1022, 0x7440, OK, "AMD", "AMD-768",enable_flash_amd_768_8111},
1493{0x1022, 0x7468, OK, "AMD", "AMD-8111",enable_flash_amd_768_8111},
1494{0x1022, 0x780e, OK, "AMD", "FCH",enable_flash_sb600},
1495{0x1039, 0x0406, NT, "SiS", "501/5101/5501",enable_flash_sis501},
1496{0x1039, 0x0496, NT, "SiS", "85C496+497",enable_flash_sis85c496},
1497{0x1039, 0x0530, OK, "SiS", "530",enable_flash_sis530},
1498{0x1039, 0x0540, NT, "SiS", "540",enable_flash_sis540},
1499{0x1039, 0x0620, NT, "SiS", "620",enable_flash_sis530},
1500{0x1039, 0x0630, NT, "SiS", "630",enable_flash_sis540},
1501{0x1039, 0x0635, NT, "SiS", "635",enable_flash_sis540},
1502{0x1039, 0x0640, NT, "SiS", "640",enable_flash_sis540},
1503{0x1039, 0x0645, NT, "SiS", "645",enable_flash_sis540},
1504{0x1039, 0x0646, OK, "SiS", "645DX",enable_flash_sis540},
1505{0x1039, 0x0648, OK, "SiS", "648",enable_flash_sis540},
1506{0x1039, 0x0650, OK, "SiS", "650",enable_flash_sis540},
1507{0x1039, 0x0651, OK, "SiS", "651",enable_flash_sis540},
1508{0x1039, 0x0655, NT, "SiS", "655",enable_flash_sis540},
1509{0x1039, 0x0661, OK, "SiS", "661",enable_flash_sis540},
1510{0x1039, 0x0730, OK, "SiS", "730",enable_flash_sis540},
1511{0x1039, 0x0733, NT, "SiS", "733",enable_flash_sis540},
1512{0x1039, 0x0735, OK, "SiS", "735",enable_flash_sis540},
1513{0x1039, 0x0740, NT, "SiS", "740",enable_flash_sis540},
1514{0x1039, 0x0741, OK, "SiS", "741",enable_flash_sis540},
1515{0x1039, 0x0745, OK, "SiS", "745",enable_flash_sis540},
1516{0x1039, 0x0746, NT, "SiS", "746",enable_flash_sis540},
1517{0x1039, 0x0748, NT, "SiS", "748",enable_flash_sis540},
1518{0x1039, 0x0755, OK, "SiS", "755",enable_flash_sis540},
1519{0x1039, 0x5511, NT, "SiS", "5511",enable_flash_sis5511},
1520{0x1039, 0x5571, NT, "SiS", "5571",enable_flash_sis530},
1521{0x1039, 0x5591, NT, "SiS", "5591/5592",enable_flash_sis530},
1522{0x1039, 0x5596, NT, "SiS", "5596",enable_flash_sis5511},
1523{0x1039, 0x5597, NT, "SiS", "5597/5598/5581/5120",enable_flash_sis530},
1524{0x1039, 0x5600, NT, "SiS", "600",enable_flash_sis530},
1525{0x1078, 0x0100, OK, "AMD", "CS5530(A)",enable_flash_cs5530},
1526{0x10b9, 0x1533, OK, "ALi", "M1533",enable_flash_ali_m1533},
1527{0x10de, 0x0030, OK, "NVIDIA", "nForce4/MCP4",enable_flash_nvidia_nforce2},
1528{0x10de, 0x0050, OK, "NVIDIA", "CK804",enable_flash_ck804}, /* LPC */
1529{0x10de, 0x0051, OK, "NVIDIA", "CK804",enable_flash_ck804}, /* Pro */
1530{0x10de, 0x0060, OK, "NVIDIA", "NForce2",enable_flash_nvidia_nforce2},
1531{0x10de, 0x00e0, OK, "NVIDIA", "NForce3",enable_flash_nvidia_nforce2},
1532/* Slave, should not be here, to fix known bug for A01. */
1533{0x10de, 0x00d3, OK, "NVIDIA", "CK804",enable_flash_ck804},
1534{0x10de, 0x0260, OK, "NVIDIA", "MCP51",enable_flash_ck804},
1535{0x10de, 0x0261, OK, "NVIDIA", "MCP51",enable_flash_ck804},
1536{0x10de, 0x0262, NT, "NVIDIA", "MCP51",enable_flash_ck804},
1537{0x10de, 0x0263, NT, "NVIDIA", "MCP51",enable_flash_ck804},
1538{0x10de, 0x0360, OK, "NVIDIA", "MCP55",enable_flash_mcp55}, /* M57SLI*/
1539/* 10de:0361 is present in Tyan S2915 OEM systems, but not connected to
1540 * the flash chip. Instead, 10de:0364 is connected to the flash chip.
1541 * Until we have PCI device class matching or some fallback mechanism,
1542 * this is needed to get flashrom working on Tyan S2915 and maybe other
1543 * dual-MCP55 boards.
1544 */
1545#if 0
1546{0x10de, 0x0361, NT, "NVIDIA", "MCP55",enable_flash_mcp55}, /* LPC */
1547#endif
1548{0x10de, 0x0362, OK, "NVIDIA", "MCP55",enable_flash_mcp55}, /* LPC */
1549{0x10de, 0x0363, OK, "NVIDIA", "MCP55",enable_flash_mcp55}, /* LPC */
1550{0x10de, 0x0364, OK, "NVIDIA", "MCP55",enable_flash_mcp55}, /* LPC */
1551{0x10de, 0x0365, OK, "NVIDIA", "MCP55",enable_flash_mcp55}, /* LPC */
1552{0x10de, 0x0366, OK, "NVIDIA", "MCP55",enable_flash_mcp55}, /* LPC */
1553{0x10de, 0x0367, OK, "NVIDIA", "MCP55",enable_flash_mcp55}, /* Pro */
1554{0x10de, 0x03e0, OK, "NVIDIA", "MCP61",enable_flash_mcp6x_7x},
1555{0x10de, 0x03e1, OK, "NVIDIA", "MCP61",enable_flash_mcp6x_7x},
1556{0x10de, 0x03e3, NT, "NVIDIA", "MCP61",enable_flash_mcp6x_7x},
1557{0x10de, 0x0440, NT, "NVIDIA", "MCP65",enable_flash_mcp6x_7x},
1558{0x10de, 0x0441, NT, "NVIDIA", "MCP65",enable_flash_mcp6x_7x},
1559{0x10de, 0x0442, NT, "NVIDIA", "MCP65",enable_flash_mcp6x_7x},
1560{0x10de, 0x0443, NT, "NVIDIA", "MCP65",enable_flash_mcp6x_7x},
1561{0x10de, 0x0548, OK, "NVIDIA", "MCP67",enable_flash_mcp6x_7x},
1562{0x10de, 0x075c, OK, "NVIDIA", "MCP78S",enable_flash_mcp6x_7x},
1563{0x10de, 0x075d, OK, "NVIDIA", "MCP78S",enable_flash_mcp6x_7x},
1564{0x10de, 0x07d7, OK, "NVIDIA", "MCP73",enable_flash_mcp6x_7x},
1565{0x10de, 0x0aac, OK, "NVIDIA", "MCP79",enable_flash_mcp6x_7x},
1566{0x10de, 0x0aad, NT, "NVIDIA", "MCP79",enable_flash_mcp6x_7x},
1567{0x10de, 0x0aae, NT, "NVIDIA", "MCP79",enable_flash_mcp6x_7x},
1568{0x10de, 0x0aaf, NT, "NVIDIA", "MCP79",enable_flash_mcp6x_7x},
1569{0x10de, 0x0d80, NT, "NVIDIA", "MCP89",enable_flash_mcp6x_7x},
1570/* VIA northbridges */
1571{0x1106, 0x0585, NT, "VIA", "VT82C585VPX",via_no_byte_merge},
1572{0x1106, 0x0595, NT, "VIA", "VT82C595",via_no_byte_merge},
1573{0x1106, 0x0597, NT, "VIA", "VT82C597",via_no_byte_merge},
1574{0x1106, 0x0601, NT, "VIA", "VT8601/VT8601A",via_no_byte_merge},
1575{0x1106, 0x0691, OK, "VIA", "VT82C69x",via_no_byte_merge},
1576{0x1106, 0x8601, NT, "VIA", "VT8601T",via_no_byte_merge},
1577/* VIA southbridges */
1578{0x1106, 0x0586, OK, "VIA", "VT82C586A/B",enable_flash_vt82c586},
1579{0x1106, 0x0596, OK, "VIA", "VT82C596",enable_flash_vt82c596},
1580{0x1106, 0x0686, OK, "VIA", "VT82C686A/B",enable_flash_vt82c596},
1581{0x1106, 0x3074, OK, "VIA", "VT8233",enable_flash_vt823x},
1582{0x1106, 0x3147, OK, "VIA", "VT8233A",enable_flash_vt823x},
1583{0x1106, 0x3177, OK, "VIA", "VT8235",enable_flash_vt823x},
1584{0x1106, 0x3227, OK, "VIA", "VT8237(R)",enable_flash_vt823x},
1585{0x1106, 0x3287, OK, "VIA", "VT8251",enable_flash_vt823x},
1586{0x1106, 0x3337, OK, "VIA", "VT8237A",enable_flash_vt823x},
1587{0x1106, 0x3372, OK, "VIA", "VT8237S",enable_flash_vt8237s_spi},
1588{0x1106, 0x8231, NT, "VIA", "VT8231",enable_flash_vt823x},
1589{0x1106, 0x8324, OK, "VIA", "CX700",enable_flash_vt823x},
1590{0x1106, 0x8353, NT, "VIA", "VX800/VX820",enable_flash_vt_vx},
1591{0x1106, 0x8409, NT, "VIA", "VX855/VX875",enable_flash_vt_vx},
1592{0x1106, 0x8410, NT, "VIA", "VX900",enable_flash_vt_vx},
1593{0x1166, 0x0200, OK, "Broadcom", "OSB4",enable_flash_osb4},
1594{0x1166, 0x0205, OK, "Broadcom", "HT-1000",enable_flash_ht1000},
1595{0x17f3, 0x6030, OK, "RDC", "R8610/R3210",enable_flash_rdc_r8610},
1596{0x8086, 0x0c60, NT, "Intel", "S12x0",enable_flash_s12x0},
1597{0x8086, 0x0f1c, OK, "Intel", "Bay Trail",enable_flash_silvermont},
1598{0x8086, 0x0f1d, NT, "Intel", "Bay Trail",enable_flash_silvermont},
1599{0x8086, 0x0f1e, NT, "Intel", "Bay Trail",enable_flash_silvermont},
1600{0x8086, 0x0f1f, NT, "Intel", "Bay Trail",enable_flash_silvermont},
1601{0x8086, 0x122e, OK, "Intel", "PIIX",enable_flash_piix4},
1602{0x8086, 0x1234, NT, "Intel", "MPIIX",enable_flash_piix4},
1603{0x8086, 0x1c44, DEP, "Intel", "Z68",enable_flash_pch6},
1604{0x8086, 0x1c46, DEP, "Intel", "P67",enable_flash_pch6},
1605{0x8086, 0x1c47, NT, "Intel", "UM67",enable_flash_pch6},
1606{0x8086, 0x1c49, NT, "Intel", "HM65",enable_flash_pch6},
1607{0x8086, 0x1c4a, DEP, "Intel", "H67",enable_flash_pch6},
1608{0x8086, 0x1c4b, NT, "Intel", "HM67",enable_flash_pch6},
1609{0x8086, 0x1c4c, NT, "Intel", "Q65",enable_flash_pch6},
1610{0x8086, 0x1c4d, NT, "Intel", "QS67",enable_flash_pch6},
1611{0x8086, 0x1c4e, NT, "Intel", "Q67",enable_flash_pch6},
1612{0x8086, 0x1c4f, DEP, "Intel", "QM67",enable_flash_pch6},
1613{0x8086, 0x1c50, NT, "Intel", "B65",enable_flash_pch6},
1614{0x8086, 0x1c52, NT, "Intel", "C202",enable_flash_pch6},
1615{0x8086, 0x1c54, DEP, "Intel", "C204",enable_flash_pch6},
1616{0x8086, 0x1c56, NT, "Intel", "C206",enable_flash_pch6},
1617{0x8086, 0x1c5c, DEP, "Intel", "H61",enable_flash_pch6},
1618{0x8086, 0x1d40, DEP, "Intel", "C60x/X79",enable_flash_pch6},
1619{0x8086, 0x1d41, DEP, "Intel", "C60x/X79",enable_flash_pch6},
1620{0x8086, 0x1e44, DEP, "Intel", "Z77",enable_flash_pch7},
1621{0x8086, 0x1e46, NT, "Intel", "Z75",enable_flash_pch7},
1622{0x8086, 0x1e47, NT, "Intel", "Q77",enable_flash_pch7},
1623{0x8086, 0x1e48, NT, "Intel", "Q75",enable_flash_pch7},
1624{0x8086, 0x1e49, DEP, "Intel", "B75",enable_flash_pch7},
1625{0x8086, 0x1e4a, DEP, "Intel", "H77",enable_flash_pch7},
1626{0x8086, 0x1e53, NT, "Intel", "C216",enable_flash_pch7},
1627{0x8086, 0x1e55, DEP, "Intel", "QM77",enable_flash_pch7},
1628{0x8086, 0x1e56, NT, "Intel", "QS77",enable_flash_pch7},
1629{0x8086, 0x1e57, DEP, "Intel", "HM77",enable_flash_pch7},
1630{0x8086, 0x1e58, NT, "Intel", "UM77",enable_flash_pch7},
1631{0x8086, 0x1e59, NT, "Intel", "HM76",enable_flash_pch7},
1632{0x8086, 0x1e5d, NT, "Intel", "HM75",enable_flash_pch7},
1633{0x8086, 0x1e5e, NT, "Intel", "HM70",enable_flash_pch7},
1634{0x8086, 0x1e5f, DEP, "Intel", "NM70",enable_flash_pch7},
1635{0x8086, 0x1f38, DEP, "Intel", "Avoton/Rangeley",enable_flash_silvermont},
1636{0x8086, 0x1f39, NT, "Intel", "Avoton/Rangeley",enable_flash_silvermont},
1637{0x8086, 0x1f3a, NT, "Intel", "Avoton/Rangeley",enable_flash_silvermont},
1638{0x8086, 0x1f3b, NT, "Intel", "Avoton/Rangeley",enable_flash_silvermont},
1639{0x8086, 0x229c, NT, "Intel", "Braswell",enable_flash_silvermont},
1640{0x8086, 0x2310, NT, "Intel", "DH89xxCC (Cave Creek)",enable_flash_pch7},
1641{0x8086, 0x2390, NT, "Intel", "Coleto Creek",enable_flash_pch7},
1642{0x8086, 0x2410, OK, "Intel", "ICH",enable_flash_ich0},
1643{0x8086, 0x2420, OK, "Intel", "ICH0",enable_flash_ich0},
1644{0x8086, 0x2440, OK, "Intel", "ICH2",enable_flash_ich2345},
1645{0x8086, 0x244c, OK, "Intel", "ICH2-M",enable_flash_ich2345},
1646{0x8086, 0x2450, NT, "Intel", "C-ICH",enable_flash_ich2345},
1647{0x8086, 0x2480, OK, "Intel", "ICH3-S",enable_flash_ich2345},
1648{0x8086, 0x248c, OK, "Intel", "ICH3-M",enable_flash_ich2345},
1649{0x8086, 0x24c0, OK, "Intel", "ICH4/ICH4-L",enable_flash_ich2345},
1650{0x8086, 0x24cc, OK, "Intel", "ICH4-M",enable_flash_ich2345},
1651{0x8086, 0x24d0, OK, "Intel", "ICH5/ICH5R",enable_flash_ich2345},
1652{0x8086, 0x25a1, OK, "Intel", "6300ESB",enable_flash_ich2345},
1653{0x8086, 0x2640, OK, "Intel", "ICH6/ICH6R",enable_flash_ich6},
1654{0x8086, 0x2641, OK, "Intel", "ICH6-M",enable_flash_ich6},
1655{0x8086, 0x2642, NT, "Intel", "ICH6W/ICH6RW",enable_flash_ich6},
1656{0x8086, 0x2670, OK, "Intel", "631xESB/632xESB/3100",enable_flash_ich6},
1657{0x8086, 0x27b0, OK, "Intel", "ICH7DH",enable_flash_ich7},
1658{0x8086, 0x27b8, OK, "Intel", "ICH7/ICH7R",enable_flash_ich7},
1659{0x8086, 0x27b9, OK, "Intel", "ICH7M",enable_flash_ich7},
1660{0x8086, 0x27bc, OK, "Intel", "NM10",enable_flash_ich7},
1661{0x8086, 0x27bd, OK, "Intel", "ICH7MDH",enable_flash_ich7},
1662{0x8086, 0x2810, DEP, "Intel", "ICH8/ICH8R",enable_flash_ich8},
1663{0x8086, 0x2811, DEP, "Intel", "ICH8M-E",enable_flash_ich8},
1664{0x8086, 0x2812, DEP, "Intel", "ICH8DH",enable_flash_ich8},
1665{0x8086, 0x2814, DEP, "Intel", "ICH8DO",enable_flash_ich8},
1666{0x8086, 0x2815, DEP, "Intel", "ICH8M",enable_flash_ich8},
1667{0x8086, 0x2910, DEP, "Intel", "ICH9 Eng. Sample",enable_flash_ich9},
1668{0x8086, 0x2912, DEP, "Intel", "ICH9DH",enable_flash_ich9},
1669{0x8086, 0x2914, DEP, "Intel", "ICH9DO",enable_flash_ich9},
1670{0x8086, 0x2916, DEP, "Intel", "ICH9R",enable_flash_ich9},
1671{0x8086, 0x2917, DEP, "Intel", "ICH9M-E",enable_flash_ich9},
1672{0x8086, 0x2918, DEP, "Intel", "ICH9",enable_flash_ich9},
1673{0x8086, 0x2919, DEP, "Intel", "ICH9M",enable_flash_ich9},
1674{0x8086, 0x3a10, NT, "Intel", "ICH10R Eng. Sample",enable_flash_ich10},
1675{0x8086, 0x3a14, DEP, "Intel", "ICH10DO",enable_flash_ich10},
1676{0x8086, 0x3a16, DEP, "Intel", "ICH10R",enable_flash_ich10},
1677{0x8086, 0x3a18, DEP, "Intel", "ICH10",enable_flash_ich10},
1678{0x8086, 0x3a1a, DEP, "Intel", "ICH10D",enable_flash_ich10},
1679{0x8086, 0x3a1e, NT, "Intel", "ICH10 Eng. Sample",enable_flash_ich10},
1680{0x8086, 0x3b00, NT, "Intel", "3400 Desktop",enable_flash_pch5},
1681{0x8086, 0x3b01, NT, "Intel", "3400 Mobile",enable_flash_pch5},
1682{0x8086, 0x3b02, NT, "Intel", "P55",enable_flash_pch5},
1683{0x8086, 0x3b03, NT, "Intel", "PM55",enable_flash_pch5},
1684{0x8086, 0x3b06, DEP, "Intel", "H55",enable_flash_pch5},
1685{0x8086, 0x3b07, DEP, "Intel", "QM57",enable_flash_pch5},
1686{0x8086, 0x3b08, NT, "Intel", "H57",enable_flash_pch5},
1687{0x8086, 0x3b09, NT, "Intel", "HM55",enable_flash_pch5},
1688{0x8086, 0x3b0a, NT, "Intel", "Q57",enable_flash_pch5},
1689{0x8086, 0x3b0b, NT, "Intel", "HM57",enable_flash_pch5},
1690{0x8086, 0x3b0d, NT, "Intel", "3400 Mobile SFF",enable_flash_pch5},
1691{0x8086, 0x3b0e, NT, "Intel", "B55",enable_flash_pch5},
1692{0x8086, 0x3b0f, DEP, "Intel", "QS57",enable_flash_pch5},
1693{0x8086, 0x3b12, NT, "Intel", "3400",enable_flash_pch5},
1694{0x8086, 0x3b14, DEP, "Intel", "3420",enable_flash_pch5},
1695{0x8086, 0x3b16, NT, "Intel", "3450",enable_flash_pch5},
1696{0x8086, 0x3b1e, NT, "Intel", "B55",enable_flash_pch5},
1697{0x8086, 0x5031, OK, "Intel", "EP80579",enable_flash_ich7},
1698{0x8086, 0x7000, OK, "Intel", "PIIX3",enable_flash_piix4},
1699{0x8086, 0x7110, OK, "Intel", "PIIX4/4E/4M",enable_flash_piix4},
1700{0x8086, 0x7198, OK, "Intel", "440MX",enable_flash_piix4},
1701{0x8086, 0x8119, OK, "Intel", "SCH Poulsbo",enable_flash_poulsbo},
1702{0x8086, 0x8186, OK, "Intel", "Atom E6xx(T) (Tunnel Creek)",enable_flash_tunnelcreek},
1703{0x8086, 0x8c40, NT, "Intel", "Lynx Point",enable_flash_pch8},
1704{0x8086, 0x8c41, NT, "Intel", "Lynx Point Mobile Eng. Sample",enable_flash_pch8},
1705{0x8086, 0x8c42, NT, "Intel", "Lynx Point Desktop Eng. Sample",enable_flash_pch8},
1706{0x8086, 0x8c43, NT, "Intel", "Lynx Point",enable_flash_pch8},
1707{0x8086, 0x8c44, DEP, "Intel", "Z87",enable_flash_pch8},
1708{0x8086, 0x8c45, NT, "Intel", "Lynx Point",enable_flash_pch8},
1709{0x8086, 0x8c46, NT, "Intel", "Z85",enable_flash_pch8},
1710{0x8086, 0x8c47, NT, "Intel", "Lynx Point",enable_flash_pch8},
1711{0x8086, 0x8c48, NT, "Intel", "Lynx Point",enable_flash_pch8},
1712{0x8086, 0x8c49, NT, "Intel", "HM86",enable_flash_pch8},
1713{0x8086, 0x8c4a, DEP, "Intel", "H87",enable_flash_pch8},
1714{0x8086, 0x8c4b, DEP, "Intel", "HM87",enable_flash_pch8},
1715{0x8086, 0x8c4c, NT, "Intel", "Q85",enable_flash_pch8},
1716{0x8086, 0x8c4d, NT, "Intel", "Lynx Point",enable_flash_pch8},
1717{0x8086, 0x8c4e, NT, "Intel", "Q87",enable_flash_pch8},
1718{0x8086, 0x8c4f, NT, "Intel", "QM87",enable_flash_pch8},
1719{0x8086, 0x8c50, DEP, "Intel", "B85",enable_flash_pch8},
1720{0x8086, 0x8c51, NT, "Intel", "Lynx Point",enable_flash_pch8},
1721{0x8086, 0x8c52, NT, "Intel", "C222",enable_flash_pch8},
1722{0x8086, 0x8c53, NT, "Intel", "Lynx Point",enable_flash_pch8},
1723{0x8086, 0x8c54, NT, "Intel", "C224",enable_flash_pch8},
1724{0x8086, 0x8c55, NT, "Intel", "Lynx Point",enable_flash_pch8},
1725{0x8086, 0x8c56, NT, "Intel", "C226",enable_flash_pch8},
1726{0x8086, 0x8c57, NT, "Intel", "Lynx Point",enable_flash_pch8},
1727{0x8086, 0x8c58, NT, "Intel", "Lynx Point",enable_flash_pch8},
1728{0x8086, 0x8c59, NT, "Intel", "Lynx Point",enable_flash_pch8},
1729{0x8086, 0x8c5a, NT, "Intel", "Lynx Point",enable_flash_pch8},
1730{0x8086, 0x8c5b, NT, "Intel", "Lynx Point",enable_flash_pch8},
1731{0x8086, 0x8c5c, NT, "Intel", "H81",enable_flash_pch8},
1732{0x8086, 0x8c5d, NT, "Intel", "Lynx Point",enable_flash_pch8},
1733{0x8086, 0x8c5e, NT, "Intel", "Lynx Point",enable_flash_pch8},
1734{0x8086, 0x8c5f, NT, "Intel", "Lynx Point",enable_flash_pch8},
1735{0x8086, 0x8cc1, NT, "Intel", "9 Series",enable_flash_pch9},
1736{0x8086, 0x8cc2, NT, "Intel", "9 Series Engineering Sample",enable_flash_pch9},
1737{0x8086, 0x8cc3, NT, "Intel", "9 Series",enable_flash_pch9},
1738{0x8086, 0x8cc4, NT, "Intel", "Z97",enable_flash_pch9},
1739{0x8086, 0x8cc6, NT, "Intel", "H97",enable_flash_pch9},
1740{0x8086, 0x8d40, NT, "Intel", "C610/X99 (Wellsburg)",enable_flash_pch8_wb},
1741{0x8086, 0x8d41, NT, "Intel", "C610/X99 (Wellsburg)",enable_flash_pch8_wb},
1742{0x8086, 0x8d42, NT, "Intel", "C610/X99 (Wellsburg)",enable_flash_pch8_wb},
1743{0x8086, 0x8d43, NT, "Intel", "C610/X99 (Wellsburg)",enable_flash_pch8_wb},
1744{0x8086, 0x8d44, NT, "Intel", "C610/X99 (Wellsburg)",enable_flash_pch8_wb},
1745{0x8086, 0x8d45, NT, "Intel", "C610/X99 (Wellsburg)",enable_flash_pch8_wb},
1746{0x8086, 0x8d46, NT, "Intel", "C610/X99 (Wellsburg)",enable_flash_pch8_wb},
1747{0x8086, 0x8d47, NT, "Intel", "C610/X99 (Wellsburg)",enable_flash_pch8_wb},
1748{0x8086, 0x8d48, NT, "Intel", "C610/X99 (Wellsburg)",enable_flash_pch8_wb},
1749{0x8086, 0x8d49, NT, "Intel", "C610/X99 (Wellsburg)",enable_flash_pch8_wb},
1750{0x8086, 0x8d4a, NT, "Intel", "C610/X99 (Wellsburg)",enable_flash_pch8_wb},
1751{0x8086, 0x8d4b, NT, "Intel", "C610/X99 (Wellsburg)",enable_flash_pch8_wb},
1752{0x8086, 0x8d4c, NT, "Intel", "C610/X99 (Wellsburg)",enable_flash_pch8_wb},
1753{0x8086, 0x8d4d, NT, "Intel", "C610/X99 (Wellsburg)",enable_flash_pch8_wb},
1754{0x8086, 0x8d4e, NT, "Intel", "C610/X99 (Wellsburg)",enable_flash_pch8_wb},
1755{0x8086, 0x8d4f, NT, "Intel", "C610/X99 (Wellsburg)",enable_flash_pch8_wb},
1756{0x8086, 0x8d50, NT, "Intel", "C610/X99 (Wellsburg)",enable_flash_pch8_wb},
1757{0x8086, 0x8d51, NT, "Intel", "C610/X99 (Wellsburg)",enable_flash_pch8_wb},
1758{0x8086, 0x8d52, NT, "Intel", "C610/X99 (Wellsburg)",enable_flash_pch8_wb},
1759{0x8086, 0x8d53, NT, "Intel", "C610/X99 (Wellsburg)",enable_flash_pch8_wb},
1760{0x8086, 0x8d54, NT, "Intel", "C610/X99 (Wellsburg)",enable_flash_pch8_wb},
1761{0x8086, 0x8d55, NT, "Intel", "C610/X99 (Wellsburg)",enable_flash_pch8_wb},
1762{0x8086, 0x8d56, NT, "Intel", "C610/X99 (Wellsburg)",enable_flash_pch8_wb},
1763{0x8086, 0x8d57, NT, "Intel", "C610/X99 (Wellsburg)",enable_flash_pch8_wb},
1764{0x8086, 0x8d58, NT, "Intel", "C610/X99 (Wellsburg)",enable_flash_pch8_wb},
1765{0x8086, 0x8d59, NT, "Intel", "C610/X99 (Wellsburg)",enable_flash_pch8_wb},
1766{0x8086, 0x8d5a, NT, "Intel", "C610/X99 (Wellsburg)",enable_flash_pch8_wb},
1767{0x8086, 0x8d5b, NT, "Intel", "C610/X99 (Wellsburg)",enable_flash_pch8_wb},
1768{0x8086, 0x8d5c, NT, "Intel", "C610/X99 (Wellsburg)",enable_flash_pch8_wb},
1769{0x8086, 0x8d5d, NT, "Intel", "C610/X99 (Wellsburg)",enable_flash_pch8_wb},
1770{0x8086, 0x8d5e, NT, "Intel", "C610/X99 (Wellsburg)",enable_flash_pch8_wb},
1771{0x8086, 0x8d5f, NT, "Intel", "C610/X99 (Wellsburg)",enable_flash_pch8_wb},
1772{0x8086, 0x9c41, NT, "Intel", "Lynx Point LP Eng. Sample",enable_flash_pch8_lp},
1773{0x8086, 0x9c43, NT, "Intel", "Lynx Point LP Premium",enable_flash_pch8_lp},
1774{0x8086, 0x9c45, NT, "Intel", "Lynx Point LP Mainstream",enable_flash_pch8_lp},
1775{0x8086, 0x9c47, NT, "Intel", "Lynx Point LP Value",enable_flash_pch8_lp},
1776{0x8086, 0x9cc1, NT, "Intel", "Haswell U Sample",enable_flash_pch9},
1777{0x8086, 0x9cc2, NT, "Intel", "Broadwell U Sample",enable_flash_pch9},
1778{0x8086, 0x9cc3, NT, "Intel", "Broadwell U Premium",enable_flash_pch9},
1779{0x8086, 0x9cc5, NT, "Intel", "Broadwell U Base",enable_flash_pch9},
1780{0x8086, 0x9cc6, NT, "Intel", "Broadwell Y Sample",enable_flash_pch9},
1781{0x8086, 0x9cc7, NT, "Intel", "Broadwell Y Premium",enable_flash_pch9},
1782{0x8086, 0x9cc9, NT, "Intel", "Broadwell Y Base",enable_flash_pch9},
1783{0x8086, 0x9ccb, NT, "Intel", "Broadwell H",enable_flash_pch9},
1784{0x8086, 0x9d41, BAD, "Intel", "Sunrise Point (Skylake LP Sample)",NULL},
1785{0x8086, 0x9d43, BAD, "Intel", "Sunrise Point (Skylake-U Base)",NULL},
1786{0x8086, 0x9d48, BAD, "Intel", "Sunrise Point (Skylake-U Premium)",NULL},
1787{0x8086, 0x9d46, BAD, "Intel", "Sunrise Point (Skylake-Y Premium)",NULL},
1788#endif
1789{0},
1790};
1791
1792int chipset_flash_enable(void)
1793{
1794struct pci_dev *dev = NULL;
1795int ret = -2;/* Nothing! */
1796int i;
1797
1798/* Now let's try to find the chipset we have... */
1799for (i = 0; chipset_enables[i].vendor_name != NULL; i++) {
1800dev = pci_dev_find(chipset_enables[i].vendor_id,
1801 chipset_enables[i].device_id);
1802if (!dev)
1803continue;
1804if (ret != -2) {
1805msg_pwarn("Warning: unexpected second chipset match: "
1806 "\"%s %s\"\n"
1807 "ignoring, please report lspci and board URL "
1808 "to flashrom@flashrom.org\n"
1809 "with \'CHIPSET: your board name\' in the "
1810 "subject line.\n",
1811chipset_enables[i].vendor_name,
1812chipset_enables[i].device_name);
1813continue;
1814}
1815msg_pinfo("Found chipset \"%s %s\"",
1816 chipset_enables[i].vendor_name,
1817 chipset_enables[i].device_name);
1818msg_pdbg(" with PCI ID %04x:%04x",
1819 chipset_enables[i].vendor_id,
1820 chipset_enables[i].device_id);
1821msg_pinfo(".\n");
1822
1823if (chipset_enables[i].status == BAD) {
1824msg_perr("ERROR: This chipset is not supported yet.\n");
1825return ERROR_FATAL;
1826}
1827if (chipset_enables[i].status == NT) {
1828msg_pinfo("This chipset is marked as untested. If "
1829 "you are using an up-to-date version\nof "
1830 "flashrom *and* were (not) able to "
1831 "successfully update your firmware with it,\n"
1832 "then please email a report to "
1833 "flashrom@flashrom.org including a verbose "
1834 "(-V) log.\nThank you!\n");
1835}
1836msg_pinfo("Enabling flash write... ");
1837ret = chipset_enables[i].doit(dev, chipset_enables[i].device_name);
1838if (ret == NOT_DONE_YET) {
1839ret = -2;
1840msg_pinfo("OK - searching further chips.\n");
1841} else if (ret < 0)
1842msg_pinfo("FAILED!\n");
1843else if (ret == 0)
1844msg_pinfo("OK.\n");
1845else if (ret == ERROR_NONFATAL)
1846msg_pinfo("PROBLEMS, continuing anyway\n");
1847if (ret == ERROR_FATAL) {
1848msg_perr("FATAL ERROR!\n");
1849return ret;
1850}
1851}
1852
1853return ret;
1854}

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