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Root/trunk/board_enable.c

1/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2005-2007 coresystems GmbH <stepan@coresystems.de>
5 * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
6 * Copyright (C) 2007-2009 Luc Verhaegen <libv@skynet.be>
7 * Copyright (C) 2007 Carl-Daniel Hailfinger
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 */
22
23/*
24 * Contains the board specific flash enables.
25 */
26
27#include <strings.h>
28#include <string.h>
29#include <stdlib.h>
30#include "flash.h"
31#include "programmer.h"
32#include "hwaccess.h"
33
34#if defined(__i386__) || defined(__x86_64__)
35/*
36 * Helper functions for many Winbond Super I/Os of the W836xx range.
37 */
38/* Enter extended functions */
39void w836xx_ext_enter(uint16_t port)
40{
41OUTB(0x87, port);
42OUTB(0x87, port);
43}
44
45/* Leave extended functions */
46void w836xx_ext_leave(uint16_t port)
47{
48OUTB(0xAA, port);
49}
50
51/* Generic Super I/O helper functions */
52uint8_t sio_read(uint16_t port, uint8_t reg)
53{
54OUTB(reg, port);
55return INB(port + 1);
56}
57
58void sio_write(uint16_t port, uint8_t reg, uint8_t data)
59{
60OUTB(reg, port);
61OUTB(data, port + 1);
62}
63
64void sio_mask(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask)
65{
66uint8_t tmp;
67
68OUTB(reg, port);
69tmp = INB(port + 1) & ~mask;
70OUTB(tmp | (data & mask), port + 1);
71}
72
73/* Winbond W83697 documentation indicates that the index register has to be written for each access. */
74void sio_mask_alzheimer(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask)
75{
76uint8_t tmp;
77
78OUTB(reg, port);
79tmp = INB(port + 1) & ~mask;
80OUTB(reg, port);
81OUTB(tmp | (data & mask), port + 1);
82}
83
84/* Not used yet. */
85#if 0
86static int enable_flash_decode_superio(void)
87{
88int ret;
89uint8_t tmp;
90
91switch (superio.vendor) {
92case SUPERIO_VENDOR_NONE:
93ret = -1;
94break;
95case SUPERIO_VENDOR_ITE:
96enter_conf_mode_ite(superio.port);
97/* Enable flash mapping. Works for most old ITE style Super I/O. */
98tmp = sio_read(superio.port, 0x24);
99tmp |= 0xfc;
100sio_write(superio.port, 0x24, tmp);
101exit_conf_mode_ite(superio.port);
102ret = 0;
103break;
104default:
105msg_pdbg("Unhandled Super I/O type!\n");
106ret = -1;
107break;
108}
109return ret;
110}
111#endif
112
113/*
114 * SMSC FDC37B787: Raise GPIO50
115 */
116static int fdc37b787_gpio50_raise(uint16_t port)
117{
118uint8_t id, val;
119
120OUTB(0x55, port);/* enter conf mode */
121id = sio_read(port, 0x20);
122if (id != 0x44) {
123msg_perr("\nERROR: FDC37B787: Wrong ID 0x%02X.\n", id);
124OUTB(0xAA, port); /* leave conf mode */
125return -1;
126}
127
128sio_write(port, 0x07, 0x08);/* Select Aux I/O subdevice */
129
130val = sio_read(port, 0xC8);/* GP50 */
131if ((val & 0x1B) != 0x10)/* output, no invert, GPIO */
132{
133msg_perr("\nERROR: GPIO50 mode 0x%02X unexpected.\n", val);
134OUTB(0xAA, port);
135return -1;
136}
137
138sio_mask(port, 0xF9, 0x01, 0x01);
139
140OUTB(0xAA, port);/* Leave conf mode */
141return 0;
142}
143
144/*
145 * Suited for:
146 * - Nokia IP530: Intel 440BX + PIIX4 + FDC37B787
147 */
148static int fdc37b787_gpio50_raise_3f0(void)
149{
150return fdc37b787_gpio50_raise(0x3f0);
151}
152
153struct winbond_mux {
154uint8_t reg;/* 0 if the corresponding pin is not muxed */
155uint8_t data;/* reg/data/mask may be directly ... */
156uint8_t mask;/* ... passed to sio_mask */
157};
158
159struct winbond_port {
160const struct winbond_mux *mux; /* NULL or pointer to mux info for the 8 bits */
161uint8_t ldn;/* LDN this GPIO register is located in */
162uint8_t enable_bit;/* bit in 0x30 of that LDN to enable
163 the GPIO port */
164uint8_t base;/* base register in that LDN for the port */
165};
166
167struct winbond_chip {
168uint8_t device_id;/* reg 0x20 of the expected w83626x */
169uint8_t gpio_port_count;
170const struct winbond_port *port;
171};
172
173
174#define UNIMPLEMENTED_PORT {NULL, 0, 0, 0}
175
176enum winbond_id {
177WINBOND_W83627HF_ID = 0x52,
178WINBOND_W83627EHF_ID = 0x88,
179WINBOND_W83627THF_ID = 0x82,
180WINBOND_W83697HF_ID = 0x60,
181};
182
183static const struct winbond_mux w83627hf_port2_mux[8] = {
184{0x2A, 0x01, 0x01},/* or MIDI */
185{0x2B, 0x80, 0x80},/* or SPI */
186{0x2B, 0x40, 0x40},/* or SPI */
187{0x2B, 0x20, 0x20},/* or power LED */
188{0x2B, 0x10, 0x10},/* or watchdog */
189{0x2B, 0x08, 0x08},/* or infra red */
190{0x2B, 0x04, 0x04},/* or infra red */
191{0x2B, 0x03, 0x03}/* or IRQ1 input */
192};
193
194static const struct winbond_port w83627hf[3] = {
195UNIMPLEMENTED_PORT,
196{w83627hf_port2_mux, 0x08, 0, 0xF0},
197UNIMPLEMENTED_PORT,
198};
199
200static const struct winbond_mux w83627ehf_port2_mux[8] = {
201{0x29, 0x06, 0x02},/* or MIDI */
202{0x29, 0x06, 0x02},
203{0x24, 0x02, 0x00},/* or SPI ROM interface */
204{0x24, 0x02, 0x00},
205{0x2A, 0x01, 0x01},/* or keyboard/mouse interface */
206{0x2A, 0x01, 0x01},
207{0x2A, 0x01, 0x01},
208{0x2A, 0x01, 0x01},
209};
210
211static const struct winbond_port w83627ehf[6] = {
212UNIMPLEMENTED_PORT,
213{w83627ehf_port2_mux, 0x09, 0, 0xE3},
214UNIMPLEMENTED_PORT,
215UNIMPLEMENTED_PORT,
216UNIMPLEMENTED_PORT,
217UNIMPLEMENTED_PORT,
218};
219
220static const struct winbond_mux w83627thf_port4_mux[8] = {
221{0x2D, 0x01, 0x01},/* or watchdog or VID level strap */
222{0x2D, 0x02, 0x02},/* or resume reset */
223{0x2D, 0x04, 0x04},/* or S3 input */
224{0x2D, 0x08, 0x08},/* or PSON# */
225{0x2D, 0x10, 0x10},/* or PWROK */
226{0x2D, 0x20, 0x20},/* or suspend LED */
227{0x2D, 0x40, 0x40},/* or panel switch input */
228{0x2D, 0x80, 0x80},/* or panel switch output */
229};
230
231static const struct winbond_port w83627thf[5] = {
232UNIMPLEMENTED_PORT,/* GPIO1 */
233UNIMPLEMENTED_PORT,/* GPIO2 */
234UNIMPLEMENTED_PORT,/* GPIO3 */
235{w83627thf_port4_mux, 0x09, 1, 0xF4},
236UNIMPLEMENTED_PORT,/* GPIO5 */
237};
238
239static const struct winbond_chip winbond_chips[] = {
240{WINBOND_W83627HF_ID, ARRAY_SIZE(w83627hf), w83627hf },
241{WINBOND_W83627EHF_ID, ARRAY_SIZE(w83627ehf), w83627ehf},
242{WINBOND_W83627THF_ID, ARRAY_SIZE(w83627thf), w83627thf},
243};
244
245#define WINBOND_SUPERIO_PORT10x2e
246#define WINBOND_SUPERIO_PORT20x4e
247
248/* We don't really care about the hardware monitor, but it offers better (more specific) device ID info than
249 * the simple device ID in the normal configuration registers.
250 * Note: This function expects to be called while the Super I/O is in config mode.
251 */
252static uint8_t w836xx_deviceid_hwmon(uint16_t sio_port)
253{
254uint16_t hwmport;
255uint16_t hwm_vendorid;
256uint8_t hwm_deviceid;
257
258sio_write(sio_port, 0x07, 0x0b); /* Select LDN 0xb (HWM). */
259if ((sio_read(sio_port, 0x30) & (1 << 0)) != (1 << 0)) {
260msg_pinfo("W836xx hardware monitor disabled or does not exist.\n");
261return 0;
262}
263/* Get HWM base address (stored in LDN 0xb, index 0x60/0x61). */
264hwmport = sio_read(sio_port, 0x60) << 8;
265hwmport |= sio_read(sio_port, 0x61);
266/* HWM address register = HWM base address + 5. */
267hwmport += 5;
268msg_pdbg2("W836xx Hardware Monitor at port %04x\n", hwmport);
269/* FIXME: This busy check should happen before each HWM access. */
270if (INB(hwmport) & 0x80) {
271msg_pinfo("W836xx hardware monitor busy, ignoring it.\n");
272return 0;
273}
274/* Set HBACS=1. */
275sio_mask_alzheimer(hwmport, 0x4e, 0x80, 0x80);
276/* Read upper byte of vendor ID. */
277hwm_vendorid = sio_read(hwmport, 0x4f) << 8;
278/* Set HBACS=0. */
279sio_mask_alzheimer(hwmport, 0x4e, 0x00, 0x80);
280/* Read lower byte of vendor ID. */
281hwm_vendorid |= sio_read(hwmport, 0x4f);
282if (hwm_vendorid != 0x5ca3) {
283msg_pinfo("W836xx hardware monitor vendor ID weirdness: expected 0x5ca3, got %04x\n",
284 hwm_vendorid);
285return 0;
286}
287/* Set Bank=0. */
288sio_mask_alzheimer(hwmport, 0x4e, 0x00, 0x07);
289/* Read "chip" ID. We call this one the device ID. */
290hwm_deviceid = sio_read(hwmport, 0x58);
291return hwm_deviceid;
292}
293
294void probe_superio_winbond(void)
295{
296struct superio s = {0};
297uint16_t winbond_ports[] = {WINBOND_SUPERIO_PORT1, WINBOND_SUPERIO_PORT2, 0};
298uint16_t *i = winbond_ports;
299uint8_t model;
300uint8_t tmp;
301
302s.vendor = SUPERIO_VENDOR_WINBOND;
303for (; *i; i++) {
304s.port = *i;
305/* If we're already in Super I/O config more, the W836xx enter sequence won't hurt. */
306w836xx_ext_enter(s.port);
307model = sio_read(s.port, 0x20);
308/* No response, no point leaving the config mode. */
309if (model == 0xff)
310continue;
311/* Try to leave config mode. If the ID register is still readable, it's not a Winbond chip. */
312w836xx_ext_leave(s.port);
313if (model == sio_read(s.port, 0x20)) {
314msg_pdbg("W836xx enter config mode worked or we were already in config mode. W836xx "
315 "leave config mode had no effect.\n");
316if (model == 0x87) {
317/* ITE IT8707F and IT8710F are special: They need the W837xx enter sequence,
318 * but they want the ITE exit sequence. Handle them here.
319 */
320tmp = sio_read(s.port, 0x21);
321switch (tmp) {
322case 0x07:
323case 0x10:
324s.vendor = SUPERIO_VENDOR_ITE;
325s.model = (0x87 << 8) | tmp ;
326msg_pdbg("Found ITE Super I/O, ID 0x%04hx on port "
327 "0x%x\n", s.model, s.port);
328register_superio(s);
329/* Exit ITE config mode. */
330exit_conf_mode_ite(s.port);
331/* Restore vendor for next loop iteration. */
332s.vendor = SUPERIO_VENDOR_WINBOND;
333continue;
334}
335}
336msg_pdbg("Active config mode, unknown reg 0x20 ID: %02x.\n", model);
337continue;
338}
339/* The Super I/O reacts to W836xx enter and exit config mode, it's probably Winbond. */
340w836xx_ext_enter(s.port);
341s.model = sio_read(s.port, 0x20);
342switch (s.model) {
343case WINBOND_W83627HF_ID:
344case WINBOND_W83627EHF_ID:
345case WINBOND_W83627THF_ID:
346msg_pdbg("Found Winbond Super I/O, id 0x%02hx\n", s.model);
347register_superio(s);
348break;
349case WINBOND_W83697HF_ID:
350/* This code is extremely paranoid. */
351tmp = sio_read(s.port, 0x26) & 0x40;
352if (((tmp == 0x00) && (s.port != WINBOND_SUPERIO_PORT1)) ||
353 ((tmp == 0x40) && (s.port != WINBOND_SUPERIO_PORT2))) {
354msg_pdbg("Winbond Super I/O probe weirdness: Port mismatch for ID "
355 "0x%02x at port 0x%04x\n", s.model, s.port);
356break;
357}
358tmp = w836xx_deviceid_hwmon(s.port);
359/* FIXME: This might be too paranoid... */
360if (!tmp) {
361msg_pdbg("Probably not a Winbond Super I/O\n");
362break;
363}
364if (tmp != s.model) {
365msg_pinfo("W83 series hardware monitor device ID weirdness: expected 0x%02x, "
366 "got 0x%02x\n", WINBOND_W83697HF_ID, tmp);
367break;
368}
369msg_pinfo("Found Winbond Super I/O, id 0x%02hx\n", s.model);
370register_superio(s);
371break;
372}
373w836xx_ext_leave(s.port);
374}
375return;
376}
377
378static const struct winbond_chip *winbond_superio_chipdef(void)
379{
380int i, j;
381
382for (i = 0; i < superio_count; i++) {
383if (superios[i].vendor != SUPERIO_VENDOR_WINBOND)
384continue;
385for (j = 0; j < ARRAY_SIZE(winbond_chips); j++)
386if (winbond_chips[j].device_id == superios[i].model)
387return &winbond_chips[j];
388}
389return NULL;
390}
391
392/*
393 * The chipid parameter goes away as soon as we have Super I/O matching in the
394 * board enable table. The call to winbond_superio_detect() goes away as
395 * soon as we have generic Super I/O detection code.
396 */
397static int winbond_gpio_set(uint16_t base, enum winbond_id chipid,
398 int pin, int raise)
399{
400const struct winbond_chip *chip = NULL;
401const struct winbond_port *gpio;
402int port = pin / 10;
403int bit = pin % 10;
404
405chip = winbond_superio_chipdef();
406if (!chip) {
407msg_perr("\nERROR: No supported Winbond Super I/O found\n");
408return -1;
409}
410if (chip->device_id != chipid) {
411msg_perr("\nERROR: Found Winbond chip with ID 0x%x, "
412 "expected %x\n", chip->device_id, chipid);
413return -1;
414}
415if (bit >= 8 || port == 0 || port > chip->gpio_port_count) {
416msg_perr("\nERROR: winbond_gpio_set: Invalid GPIO number %d\n",
417 pin);
418return -1;
419}
420
421gpio = &chip->port[port - 1];
422
423if (gpio->ldn == 0) {
424msg_perr("\nERROR: GPIO%d is not supported yet on this"
425 " winbond chip\n", port);
426return -1;
427}
428
429w836xx_ext_enter(base);
430
431/* Select logical device. */
432sio_write(base, 0x07, gpio->ldn);
433
434/* Activate logical device. */
435sio_mask(base, 0x30, 1 << gpio->enable_bit, 1 << gpio->enable_bit);
436
437/* Select GPIO function of that pin. */
438if (gpio->mux && gpio->mux[bit].reg)
439sio_mask(base, gpio->mux[bit].reg,
440 gpio->mux[bit].data, gpio->mux[bit].mask);
441
442sio_mask(base, gpio->base + 0, 0, 1 << bit);/* Make pin output */
443sio_mask(base, gpio->base + 2, 0, 1 << bit);/* Clear inversion */
444sio_mask(base, gpio->base + 1, raise << bit, 1 << bit);
445
446w836xx_ext_leave(base);
447
448return 0;
449}
450
451/*
452 * Winbond W83627HF: Raise GPIO24.
453 *
454 * Suited for:
455 * - Agami Aruma
456 * - IWILL DK8-HTX
457 */
458static int w83627hf_gpio24_raise_2e(void)
459{
460return winbond_gpio_set(0x2e, WINBOND_W83627HF_ID, 24, 1);
461}
462
463/*
464 * Winbond W83627HF: Raise GPIO25.
465 *
466 * Suited for:
467 * - MSI MS-6577
468 */
469static int w83627hf_gpio25_raise_2e(void)
470{
471return winbond_gpio_set(0x2e, WINBOND_W83627HF_ID, 25, 1);
472}
473
474/*
475 * Winbond W83627EHF: Raise GPIO22.
476 *
477 * Suited for:
478 * - ASUS A8N-VM CSM: AMD Socket 939 + GeForce 6150 (C51) + MCP51
479 */
480static int w83627ehf_gpio22_raise_2e(void)
481{
482return winbond_gpio_set(0x2e, WINBOND_W83627EHF_ID, 22, 1);
483}
484
485/*
486 * Winbond W83627THF: Raise GPIO 44.
487 *
488 * Suited for:
489 * - MSI K8T Neo2-F V2.0
490 */
491static int w83627thf_gpio44_raise_2e(void)
492{
493return winbond_gpio_set(0x2e, WINBOND_W83627THF_ID, 44, 1);
494}
495
496/*
497 * Winbond W83627THF: Raise GPIO 44.
498 *
499 * Suited for:
500 * - MSI K8N Neo3
501 */
502static int w83627thf_gpio44_raise_4e(void)
503{
504return winbond_gpio_set(0x4e, WINBOND_W83627THF_ID, 44, 1);
505}
506
507/*
508 * Enable MEMW# and set ROM size to max.
509 * Supported chips: W83L517D, W83697HF/F/HG, W83697SF/UF/UG
510 */
511static void w836xx_memw_enable(uint16_t port)
512{
513w836xx_ext_enter(port);
514if (!(sio_read(port, 0x24) & 0x02)) {/* Flash ROM enabled? */
515/* Enable MEMW# and set ROM size select to max. (4M). */
516sio_mask(port, 0x24, 0x28, 0x28);
517}
518w836xx_ext_leave(port);
519}
520
521/**
522 * Enable MEMW# and set ROM size to max.
523 * Supported chips:
524 * W83697HF/F/HG, W83697SF/UF/UG
525 */
526void w83697xx_memw_enable(uint16_t port)
527{
528w836xx_ext_enter(port);
529if (!(sio_read(port, 0x24) & 0x02)) { /* Flash ROM enabled? */
530if((sio_read(port, 0x2A) & 0xF0) == 0xF0) {
531
532/* CR24 Bits 7 & 2 must be set to 0 enable the flash ROM */
533/* address segments 000E0000h ~ 000FFFFFh on W83697SF/UF/UG */
534/* These bits are reserved on W83697HF/F/HG */
535/* Shouldn't be needed though. */
536
537/* CR28 Bit3 must be set to 1 to enable flash access to */
538/* FFE80000h ~ FFEFFFFFh on W83697SF/UF/UG. */
539/* This bit is reserved on W83697HF/F/HG which default to 0 */
540sio_mask(port, 0x28, 0x08, 0x08);
541
542/* Enable MEMW# and set ROM size select to max. (4M)*/
543sio_mask(port, 0x24, 0x28, 0x38);
544
545} else {
546msg_pwarn("Warning: Flash interface in use by GPIO!\n");
547}
548} else {
549msg_pinfo("BIOS ROM is disabled\n");
550 }
551 w836xx_ext_leave(port);
552}
553
554/*
555 * Suited for:
556 * - Biostar M7VIQ: VIA KM266 + VT8235
557 */
558static int w83697xx_memw_enable_2e(void)
559{
560w83697xx_memw_enable(0x2E);
561
562return 0;
563}
564
565
566/*
567 * Suited for:
568 * - DFI AD77: VIA KT400 + VT8235 + W83697HF
569 * - EPoX EP-8K5A2: VIA KT333 + VT8235
570 * - Albatron PM266A Pro: VIA P4M266A + VT8235
571 * - Shuttle AK31 (all versions): VIA KT266 + VT8233
572 * - ASUS A7V8X-MX SE and A7V400-MX: AMD K7 + VIA KM400A + VT8235
573 * - Tyan S2498 (Tomcat K7M): AMD Geode NX + VIA KM400 + VT8237
574 * - MSI KM4M-V and KM4AM-V: VIA KM400/KM400A + VT8237
575 * - MSI MS-6561 (745 Ultra): SiS 745 + W83697HF
576 * - MSI MS-6787 (P4MAM-V/P4MAM-L): VIA P4M266 + VT8235
577 * - ASRock K7S41: SiS 741 + SiS 963 + W83697HF
578 * - ASRock K7S41GX: SiS 741GX + SiS 963L + W83697HF
579 */
580static int w836xx_memw_enable_2e(void)
581{
582w836xx_memw_enable(0x2E);
583
584return 0;
585}
586
587/*
588 * Suited for:
589 * - Termtek TK-3370 (rev. 2.5b)
590 */
591static int w836xx_memw_enable_4e(void)
592{
593w836xx_memw_enable(0x4E);
594
595return 0;
596}
597
598/*
599 * Suited for all boards with ITE IT8705F.
600 * The SIS950 Super I/O probably requires a similar flash write enable.
601 */
602int it8705f_write_enable(uint8_t port)
603{
604uint8_t tmp;
605int ret = 0;
606
607enter_conf_mode_ite(port);
608tmp = sio_read(port, 0x24);
609/* Check if at least one flash segment is enabled. */
610if (tmp & 0xf0) {
611/* The IT8705F will respond to LPC cycles and translate them. */
612internal_buses_supported = BUS_PARALLEL;
613/* Flash ROM I/F Writes Enable */
614tmp |= 0x04;
615msg_pdbg("Enabling IT8705F flash ROM interface write.\n");
616if (tmp & 0x02) {
617/* The data sheet contradicts itself about max size. */
618max_rom_decode.parallel = 1024 * 1024;
619msg_pinfo("IT8705F with very unusual settings.\n"
620 "Please send the output of \"flashrom -V -p internal\" to flashrom@flashrom.org\n"
621 "with \"IT8705: your board name: flashrom -V\" as the subject to help us finish\n"
622 "support for your Super I/O. Thanks.\n");
623ret = 1;
624} else if (tmp & 0x08) {
625max_rom_decode.parallel = 512 * 1024;
626} else {
627max_rom_decode.parallel = 256 * 1024;
628}
629/* Safety checks. The data sheet is unclear here: Segments 1+3
630 * overlap, no segment seems to cover top - 1MB to top - 512kB.
631 * We assume that certain combinations make no sense.
632 */
633if (((tmp & 0x02) && !(tmp & 0x08)) || /* 1 MB en, 512 kB dis */
634 (!(tmp & 0x10)) || /* 128 kB dis */
635 (!(tmp & 0x40))) { /* 256/512 kB dis */
636msg_perr("Inconsistent IT8705F decode size!\n");
637ret = 1;
638}
639if (sio_read(port, 0x25) != 0) {
640msg_perr("IT8705F flash data pins disabled!\n");
641ret = 1;
642}
643if (sio_read(port, 0x26) != 0) {
644msg_perr("IT8705F flash address pins 0-7 disabled!\n");
645ret = 1;
646}
647if (sio_read(port, 0x27) != 0) {
648msg_perr("IT8705F flash address pins 8-15 disabled!\n");
649ret = 1;
650}
651if ((sio_read(port, 0x29) & 0x10) != 0) {
652msg_perr("IT8705F flash write enable pin disabled!\n");
653ret = 1;
654}
655if ((sio_read(port, 0x29) & 0x08) != 0) {
656msg_perr("IT8705F flash chip select pin disabled!\n");
657ret = 1;
658}
659if ((sio_read(port, 0x29) & 0x04) != 0) {
660msg_perr("IT8705F flash read strobe pin disabled!\n");
661ret = 1;
662}
663if ((sio_read(port, 0x29) & 0x03) != 0) {
664msg_perr("IT8705F flash address pins 16-17 disabled!\n");
665/* Not really an error if you use flash chips smaller
666 * than 256 kByte, but such a configuration is unlikely.
667 */
668ret = 1;
669}
670msg_pdbg("Maximum IT8705F parallel flash decode size is %u.\n",
671max_rom_decode.parallel);
672if (ret) {
673msg_pinfo("Not enabling IT8705F flash write.\n");
674} else {
675sio_write(port, 0x24, tmp);
676}
677} else {
678msg_pdbg("No IT8705F flash segment enabled.\n");
679ret = 0;
680}
681exit_conf_mode_ite(port);
682
683return ret;
684}
685
686/*
687 * The ITE IT8707F is a custom chip made by ITE exclusively for ASUS.
688 * It uses the Winbond command sequence to enter extended configuration
689 * mode and the ITE sequence to exit.
690 *
691 * Registers seems similar to the ones on ITE IT8710F.
692 */
693static int it8707f_write_enable(uint8_t port)
694{
695uint8_t tmp;
696
697w836xx_ext_enter(port);
698
699/* Set bit 3 (GLB_REG_WE) of reg 0x23: Makes reg 0x24-0x2A rw */
700tmp = sio_read(port, 0x23);
701tmp |= (1 << 3);
702sio_write(port, 0x23, tmp);
703
704/* Set bit 2 (FLASH_WE) and bit 3 (FLASH_IF_EN) of reg 0x24 */
705tmp = sio_read(port, 0x24);
706tmp |= (1 << 2) | (1 << 3);
707sio_write(port, 0x24, tmp);
708
709/* Clear bit 3 (GLB_REG_WE) of reg 0x23: Makes reg 0x24-0x2A ro */
710tmp = sio_read(port, 0x23);
711tmp &= ~(1 << 3);
712sio_write(port, 0x23, tmp);
713
714exit_conf_mode_ite(port);
715
716return 0;
717}
718
719/*
720 * Suited for:
721 * - ASUS P4SC-E: SiS 651 + 962 + ITE IT8707F
722 */
723static int it8707f_write_enable_2e(void)
724{
725return it8707f_write_enable(0x2e);
726}
727
728#define PC87360_ID 0xE1
729#define PC87364_ID 0xE4
730
731static int pc8736x_gpio_set(uint8_t chipid, uint8_t gpio, int raise)
732{
733static const int bankbase[] = {0, 4, 8, 10, 12};
734int gpio_bank = gpio / 8;
735int gpio_pin = gpio % 8;
736uint16_t baseport;
737uint8_t id, val;
738
739if (gpio_bank > 4) {
740msg_perr("PC8736x: Invalid GPIO %d\n", gpio);
741return -1;
742}
743
744id = sio_read(0x2E, 0x20);
745if (id != chipid) {
746msg_perr("PC8736x: unexpected ID %02x (expected %02x)\n",
747 id, chipid);
748return -1;
749}
750
751sio_write(0x2E, 0x07, 0x07);/* Select GPIO device. */
752baseport = (sio_read(0x2E, 0x60) << 8) | sio_read(0x2E, 0x61);
753if ((baseport & 0xFFF0) == 0xFFF0 || baseport == 0) {
754msg_perr("PC87360: invalid GPIO base address %04x\n",
755 baseport);
756return -1;
757}
758sio_mask (0x2E, 0x30, 0x01, 0x01);/* Enable logical device. */
759sio_write(0x2E, 0xF0, gpio_bank * 16 + gpio_pin);
760sio_mask (0x2E, 0xF1, 0x01, 0x01);/* Make pin output. */
761
762val = INB(baseport + bankbase[gpio_bank]);
763if (raise)
764val |= 1 << gpio_pin;
765else
766val &= ~(1 << gpio_pin);
767OUTB(val, baseport + bankbase[gpio_bank]);
768
769return 0;
770}
771
772/*
773 * VIA VT823x: Set one of the GPIO pins.
774 */
775static int via_vt823x_gpio_set(uint8_t gpio, int raise)
776{
777struct pci_dev *dev;
778uint16_t base;
779uint8_t val, bit, offset;
780
781dev = pci_dev_find_vendorclass(0x1106, 0x0601);
782switch (dev->device_id) {
783case 0x3177:/* VT8235 */
784case 0x3227:/* VT8237/VT8237R */
785case 0x3337:/* VT8237A */
786break;
787default:
788msg_perr("\nERROR: VT823x ISA bridge not found.\n");
789return -1;
790}
791
792if ((gpio >= 12) && (gpio <= 15)) {
793/* GPIO12-15 -> output */
794val = pci_read_byte(dev, 0xE4);
795val |= 0x10;
796pci_write_byte(dev, 0xE4, val);
797} else if (gpio == 9) {
798/* GPIO9 -> Output */
799val = pci_read_byte(dev, 0xE4);
800val |= 0x20;
801pci_write_byte(dev, 0xE4, val);
802} else if (gpio == 5) {
803val = pci_read_byte(dev, 0xE4);
804val |= 0x01;
805pci_write_byte(dev, 0xE4, val);
806} else {
807msg_perr("\nERROR: "
808"VT823x GPIO%02d is not implemented.\n", gpio);
809return -1;
810}
811
812/* We need the I/O Base Address for this board's flash enable. */
813base = pci_read_word(dev, 0x88) & 0xff80;
814
815offset = 0x4C + gpio / 8;
816bit = 0x01 << (gpio % 8);
817
818val = INB(base + offset);
819if (raise)
820val |= bit;
821else
822val &= ~bit;
823OUTB(val, base + offset);
824
825return 0;
826}
827
828/*
829 * Suited for:
830 * - ASUS M2V-MX: VIA K8M890 + VT8237A + IT8716F
831 */
832static int via_vt823x_gpio5_raise(void)
833{
834/* On M2V-MX: GPO5 is connected to WP# and TBL#. */
835return via_vt823x_gpio_set(5, 1);
836}
837
838/*
839 * Suited for:
840 * - VIA EPIA EK & N & NL
841 */
842static int via_vt823x_gpio9_raise(void)
843{
844return via_vt823x_gpio_set(9, 1);
845}
846
847/*
848 * Suited for:
849 * - VIA EPIA M and MII (and maybe other CLE266 based EPIAs)
850 *
851 * We don't need to do this for EPIA M when using coreboot, GPIO15 is never
852 * lowered there.
853 */
854static int via_vt823x_gpio15_raise(void)
855{
856return via_vt823x_gpio_set(15, 1);
857}
858
859/*
860 * Winbond W83697HF Super I/O + VIA VT8235 southbridge
861 *
862 * Suited for:
863 * - MSI KT4V and KT4V-L: AMD K7 + VIA KT400 + VT8235
864 * - MSI KT4 Ultra: AMD K7 + VIA KT400 + VT8235
865 */
866static int board_msi_kt4v(void)
867{
868int ret;
869
870ret = via_vt823x_gpio_set(12, 1);
871w836xx_memw_enable(0x2E);
872
873return ret;
874}
875
876/*
877 * Suited for:
878 * - ASUS P5A
879 *
880 * This is rather nasty code, but there's no way to do this cleanly.
881 * We're basically talking to some unknown device on SMBus, my guess
882 * is that it is the Winbond W83781D that lives near the DIP BIOS.
883 */
884static int board_asus_p5a(void)
885{
886uint8_t tmp;
887int i;
888
889#define ASUSP5A_LOOP 5000
890
891OUTB(0x00, 0xE807);
892OUTB(0xEF, 0xE803);
893
894OUTB(0xFF, 0xE800);
895
896for (i = 0; i < ASUSP5A_LOOP; i++) {
897OUTB(0xE1, 0xFF);
898if (INB(0xE800) & 0x04)
899break;
900}
901
902if (i == ASUSP5A_LOOP) {
903msg_perr("Unable to contact device.\n");
904return -1;
905}
906
907OUTB(0x20, 0xE801);
908OUTB(0x20, 0xE1);
909
910OUTB(0xFF, 0xE802);
911
912for (i = 0; i < ASUSP5A_LOOP; i++) {
913tmp = INB(0xE800);
914if (tmp & 0x70)
915break;
916}
917
918if ((i == ASUSP5A_LOOP) || !(tmp & 0x10)) {
919msg_perr("Failed to read device.\n");
920return -1;
921}
922
923tmp = INB(0xE804);
924tmp &= ~0x02;
925
926OUTB(0x00, 0xE807);
927OUTB(0xEE, 0xE803);
928
929OUTB(tmp, 0xE804);
930
931OUTB(0xFF, 0xE800);
932OUTB(0xE1, 0xFF);
933
934OUTB(0x20, 0xE801);
935OUTB(0x20, 0xE1);
936
937OUTB(0xFF, 0xE802);
938
939for (i = 0; i < ASUSP5A_LOOP; i++) {
940tmp = INB(0xE800);
941if (tmp & 0x70)
942break;
943}
944
945if ((i == ASUSP5A_LOOP) || !(tmp & 0x10)) {
946msg_perr("Failed to write to device.\n");
947return -1;
948}
949
950return 0;
951}
952
953/*
954 * Set GPIO lines in the Broadcom HT-1000 southbridge.
955 *
956 * It's not a Super I/O but it uses the same index/data port method.
957 */
958static int board_hp_dl145_g3_enable(void)
959{
960/* GPIO 0 reg from PM regs */
961/* Set GPIO 2 and 5 high, connected to flash WP# and TBL# pins. */
962sio_mask(0xcd6, 0x44, 0x24, 0x24);
963
964return 0;
965}
966
967/*
968 * Set GPIO lines in the Broadcom HT-1000 southbridge.
969 *
970 * It's not a Super I/O but it uses the same index/data port method.
971 */
972static int board_hp_dl165_g6_enable(void)
973{
974/* Variant of DL145, with slightly different pin placement. */
975sio_mask(0xcd6, 0x44, 0x80, 0x80); /* TBL# */
976sio_mask(0xcd6, 0x46, 0x04, 0x04); /* WP# */
977
978return 0;
979}
980
981static int board_ibm_x3455(void)
982{
983/* Raise GPIO13. */
984sio_mask(0xcd6, 0x45, 0x20, 0x20);
985
986return 0;
987}
988
989/*
990 * Suited for:
991 * - Elitegroup GeForce6100SM-M: NVIDIA MCP61 + ITE IT8726F
992 */
993static int board_ecs_geforce6100sm_m(void)
994{
995struct pci_dev *dev;
996uint32_t tmp;
997
998dev = pci_dev_find(0x10DE, 0x03EB); /* NVIDIA MCP61 SMBus. */
999if (!dev) {
1000msg_perr("\nERROR: NVIDIA MCP61 SMBus not found.\n");
1001return -1;
1002}
1003
1004tmp = pci_read_byte(dev, 0xE0);
1005tmp &= ~(1 << 3);
1006pci_write_byte(dev, 0xE0, tmp);
1007
1008return 0;
1009}
1010
1011/*
1012 * Very similar to AMD 8111 IO Hub.
1013 */
1014static int nvidia_mcp_gpio_set(int gpio, int raise)
1015{
1016struct pci_dev *dev;
1017uint16_t base, devclass;
1018uint8_t tmp;
1019
1020if ((gpio < 0) || (gpio >= 0x40)) {
1021msg_perr("\nERROR: unsupported GPIO: %d.\n", gpio);
1022return -1;
1023}
1024
1025/* Check for the ISA bridge first. */
1026dev = pci_dev_find_vendorclass(0x10DE, 0x0601);
1027switch (dev->device_id) {
1028case 0x0030: /* CK804 */
1029case 0x0050: /* MCP04 */
1030case 0x0060: /* MCP2 */
1031case 0x00E0: /* CK8 */
1032break;
1033case 0x0260: /* MCP51 */
1034case 0x0261: /* MCP51 */
1035case 0x0360: /* MCP55 */
1036case 0x0364: /* MCP55 */
1037/* find SMBus controller on *this* southbridge */
1038/* The infamous Tyan S2915-E has two south bridges; they are
1039 easily told apart from each other by the class of the
1040 LPC bridge, but have the same SMBus bridge IDs */
1041if (dev->func != 0) {
1042msg_perr("MCP LPC bridge at unexpected function"
1043 " number %d\n", dev->func);
1044return -1;
1045}
1046
1047#if !defined(OLD_PCI_GET_DEV)
1048dev = pci_get_dev(pacc, dev->domain, dev->bus, dev->dev, 1);
1049#else
1050/* pciutils/libpci before version 2.2 is too old to support
1051 * PCI domains. Such old machines usually don't have domains
1052 * besides domain 0, so this is not a problem.
1053 */
1054dev = pci_get_dev(pacc, dev->bus, dev->dev, 1);
1055#endif
1056if (!dev) {
1057msg_perr("MCP SMBus controller could not be found\n");
1058return -1;
1059}
1060devclass = pci_read_word(dev, PCI_CLASS_DEVICE);
1061if (devclass != 0x0C05) {
1062msg_perr("Unexpected device class %04x for SMBus"
1063 " controller\n", devclass);
1064return -1;
1065}
1066break;
1067default:
1068msg_perr("\nERROR: no NVIDIA LPC/SMBus controller found.\n");
1069return -1;
1070}
1071
1072base = pci_read_long(dev, 0x64) & 0x0000FF00; /* System control area */
1073base += 0xC0;
1074
1075tmp = INB(base + gpio);
1076tmp &= ~0x0F; /* null lower nibble */
1077tmp |= 0x04; /* gpio -> output. */
1078if (raise)
1079tmp |= 0x01;
1080OUTB(tmp, base + gpio);
1081
1082return 0;
1083}
1084
1085/*
1086 * Suited for:
1087 * - ASUS A8M2N-LA (HP OEM "NodusM3-GL8E"): NVIDIA MCP51
1088 * - ASUS A8N-LA (HP OEM "Nagami-GL8E"): NVIDIA MCP51
1089 * - ASUS M2NBP-VM CSM: NVIDIA MCP51
1090 */
1091static int nvidia_mcp_gpio0_raise(void)
1092{
1093return nvidia_mcp_gpio_set(0x00, 1);
1094}
1095
1096/*
1097 * Suited for:
1098 * - abit KN8 Ultra: NVIDIA CK804
1099 * - abit KN9 Ultra: NVIDIA MCP55
1100 */
1101static int nvidia_mcp_gpio2_lower(void)
1102{
1103return nvidia_mcp_gpio_set(0x02, 0);
1104}
1105
1106/*
1107 * Suited for:
1108 * - Foxconn 6150K8MD-8EKRSH: Socket 939 + NVIDIA MCP51
1109 * - MSI K8N Neo4(-F/-FI/-FX/Platinum): NVIDIA CK804
1110 * - MSI K8NGM2-L: NVIDIA MCP51
1111 * - MSI K9N SLI: NVIDIA MCP55
1112 */
1113static int nvidia_mcp_gpio2_raise(void)
1114{
1115return nvidia_mcp_gpio_set(0x02, 1);
1116}
1117
1118/*
1119 * Suited for:
1120 * - EPoX EP-8NPA7I: Socket 754 + NVIDIA nForce4 4X
1121 */
1122static int nvidia_mcp_gpio4_raise(void)
1123{
1124return nvidia_mcp_gpio_set(0x04, 1);
1125}
1126
1127/*
1128 * Suited for:
1129 * - HP xw9400 (Tyan S2915-E OEM): Dual(!) NVIDIA MCP55
1130 *
1131 * Notes: a) There are two MCP55 chips, so also two SMBus bridges on that
1132 * board. We can't tell the SMBus logical devices apart, but we
1133 * can tell the LPC bridge functions apart.
1134 * We need to choose the SMBus bridge next to the LPC bridge with
1135 * ID 0x364 and the "LPC bridge" class.
1136 * b) #TBL is hardwired on that board to a pull-down. It can be
1137 * overridden by connecting the two solder points next to F2.
1138 */
1139static int nvidia_mcp_gpio5_raise(void)
1140{
1141return nvidia_mcp_gpio_set(0x05, 1);
1142}
1143
1144/*
1145 * Suited for:
1146 * - abit NF7-S: NVIDIA CK804
1147 */
1148static int nvidia_mcp_gpio8_raise(void)
1149{
1150return nvidia_mcp_gpio_set(0x08, 1);
1151}
1152
1153/*
1154 * Suited for:
1155 * - GIGABYTE GA-K8NS Pro-939: Socket 939 + NVIDIA nForce3 + CK8
1156 * - Probably other versions of the GA-K8NS
1157 */
1158static int nvidia_mcp_gpio0a_raise(void)
1159{
1160return nvidia_mcp_gpio_set(0x0a, 1);
1161}
1162
1163/*
1164 * Suited for:
1165 * - MSI K8N Neo Platinum: Socket 754 + nForce3 Ultra + CK8
1166 * - MSI K8N Neo2 Platinum: Socket 939 + nForce3 Ultra + CK8
1167 */
1168static int nvidia_mcp_gpio0c_raise(void)
1169{
1170return nvidia_mcp_gpio_set(0x0c, 1);
1171}
1172
1173/*
1174 * Suited for:
1175 * - abit NF-M2 nView: Socket AM2 + NVIDIA MCP51
1176 */
1177static int nvidia_mcp_gpio4_lower(void)
1178{
1179return nvidia_mcp_gpio_set(0x04, 0);
1180}
1181
1182/*
1183 * Suited for:
1184 * - ASUS P5ND2-SLI Deluxe: LGA775 + nForce4 SLI + MCP04
1185 */
1186static int nvidia_mcp_gpio10_raise(void)
1187{
1188return nvidia_mcp_gpio_set(0x10, 1);
1189}
1190
1191/*
1192 * Suited for:
1193 * - GIGABYTE GA-K8N-SLI: AMD socket 939 + NVIDIA CK804 + ITE IT8712F
1194 */
1195static int nvidia_mcp_gpio21_raise(void)
1196{
1197return nvidia_mcp_gpio_set(0x21, 0x01);
1198}
1199
1200/*
1201 * Suited for:
1202 * - EPoX EP-8RDA3+: Socket A + nForce2 Ultra 400 + MCP2
1203 */
1204static int nvidia_mcp_gpio31_raise(void)
1205{
1206return nvidia_mcp_gpio_set(0x31, 0x01);
1207}
1208
1209/*
1210 * Suited for:
1211 * - GIGABYTE GA-K8N51GMF: Socket 754 + Geforce 6100 + MCP51
1212 * - GIGABYTE GA-K8N51GMF-9: Socket 939 + Geforce 6100 + MCP51
1213 */
1214static int nvidia_mcp_gpio3b_raise(void)
1215{
1216return nvidia_mcp_gpio_set(0x3b, 1);
1217}
1218
1219/*
1220 * Suited for:
1221 * - Sun Ultra 40 M2: Dual Socket F (1207) + MCP55
1222 */
1223static int board_sun_ultra_40_m2(void)
1224{
1225int ret;
1226uint8_t reg;
1227uint16_t base;
1228struct pci_dev *dev;
1229
1230ret = nvidia_mcp_gpio4_lower();
1231if (ret)
1232return ret;
1233
1234dev = pci_dev_find(0x10de, 0x0364); /* NVIDIA MCP55 LPC bridge */
1235if (!dev) {
1236msg_perr("\nERROR: NVIDIA MCP55 LPC bridge not found.\n");
1237return -1;
1238}
1239
1240base = pci_read_word(dev, 0xb4); /* some IO BAR? */
1241if (!base)
1242return -1;
1243
1244reg = INB(base + 0x4b);
1245reg |= 0x10;
1246OUTB(reg, base + 0x4b);
1247
1248return 0;
1249}
1250
1251/*
1252 * Suited for:
1253 * - Artec Group DBE61 and DBE62
1254 */
1255static int board_artecgroup_dbe6x(void)
1256{
1257#define DBE6x_MSR_DIVIL_BALL_OPTS0x51400015
1258#define DBE6x_PRI_BOOT_LOC_SHIFT2
1259#define DBE6x_BOOT_OP_LATCHED_SHIFT8
1260#define DBE6x_SEC_BOOT_LOC_SHIFT10
1261#define DBE6x_PRI_BOOT_LOC(3 << DBE6x_PRI_BOOT_LOC_SHIFT)
1262#define DBE6x_BOOT_OP_LATCHED(3 << DBE6x_BOOT_OP_LATCHED_SHIFT)
1263#define DBE6x_SEC_BOOT_LOC(3 << DBE6x_SEC_BOOT_LOC_SHIFT)
1264#define DBE6x_BOOT_LOC_FLASH2
1265#define DBE6x_BOOT_LOC_FWHUB3
1266
1267msr_t msr;
1268unsigned long boot_loc;
1269
1270/* Geode only has a single core */
1271if (setup_cpu_msr(0))
1272return -1;
1273
1274msr = rdmsr(DBE6x_MSR_DIVIL_BALL_OPTS);
1275
1276if ((msr.lo & (DBE6x_BOOT_OP_LATCHED)) ==
1277 (DBE6x_BOOT_LOC_FWHUB << DBE6x_BOOT_OP_LATCHED_SHIFT))
1278boot_loc = DBE6x_BOOT_LOC_FWHUB;
1279else
1280boot_loc = DBE6x_BOOT_LOC_FLASH;
1281
1282msr.lo &= ~(DBE6x_PRI_BOOT_LOC | DBE6x_SEC_BOOT_LOC);
1283msr.lo |= ((boot_loc << DBE6x_PRI_BOOT_LOC_SHIFT) |
1284 (boot_loc << DBE6x_SEC_BOOT_LOC_SHIFT));
1285
1286wrmsr(DBE6x_MSR_DIVIL_BALL_OPTS, msr);
1287
1288cleanup_cpu_msr();
1289
1290return 0;
1291}
1292
1293/*
1294 * Suited for:
1295 * - ASUS A8AE-LE (Codename AmberineM; used in Compaq Presario 061)
1296 * Datasheet(s) used:
1297 * - AMD document 43009 "AMD SB700/710/750 Register Reference Guide" rev. 1.00
1298 */
1299static int amd_sbxxx_gpio9_raise(void)
1300{
1301struct pci_dev *dev;
1302uint32_t reg;
1303
1304dev = pci_dev_find(0x1002, 0x4372); /* AMD SMBus controller */
1305if (!dev) {
1306msg_perr("\nERROR: AMD SMBus Controller (0x4372) not found.\n");
1307return -1;
1308}
1309
1310reg = pci_read_long(dev, 0xA8); /* GPIO_12_to_4_Cntrl CI_Reg: A8h-ABh */
1311/* enable output (0: enable, 1: tristate):
1312 GPIO9 output enable is at bit 5 in 0xA9 */
1313reg &= ~((uint32_t)1<<(8+5));
1314/* raise:
1315 GPIO9 output register is at bit 5 in 0xA8 */
1316reg |= (1<<5);
1317pci_write_long(dev, 0xA8, reg);
1318
1319return 0;
1320}
1321
1322/*
1323 * Helper function to raise/drop a given gpo line on Intel PIIX4{,E,M}.
1324 */
1325static int intel_piix4_gpo_set(unsigned int gpo, int raise)
1326{
1327unsigned int gpo_byte, gpo_bit;
1328struct pci_dev *dev;
1329uint32_t tmp, base;
1330
1331/* GPO{0,8,27,28,30} are always available. */
1332static const uint32_t nonmuxed_gpos = 0x58000101;
1333
1334static const struct {unsigned int reg, mask, value; } piix4_gpo[] = {
1335{0},
1336{0xB0, 0x0001, 0x0000}, /* GPO1... */
1337{0xB0, 0x0001, 0x0000},
1338{0xB0, 0x0001, 0x0000},
1339{0xB0, 0x0001, 0x0000},
1340{0xB0, 0x0001, 0x0000},
1341{0xB0, 0x0001, 0x0000},
1342{0xB0, 0x0001, 0x0000}, /* ...GPO7: GENCFG bit 0 */
1343{0},
1344{0xB0, 0x0100, 0x0000}, /* GPO9: GENCFG bit 8 */
1345{0xB0, 0x0200, 0x0000}, /* GPO10: GENCFG bit 9 */
1346{0xB0, 0x0400, 0x0000}, /* GPO11: GENCFG bit 10 */
1347{0x4E, 0x0100, 0x0000}, /* GPO12... */
1348{0x4E, 0x0100, 0x0000},
1349{0x4E, 0x0100, 0x0000}, /* ...GPO14: XBCS bit 8 */
1350{0xB2, 0x0002, 0x0002}, /* GPO15... */
1351{0xB2, 0x0002, 0x0002}, /* ...GPO16: GENCFG bit 17 */
1352{0xB2, 0x0004, 0x0004}, /* GPO17: GENCFG bit 18 */
1353{0xB2, 0x0008, 0x0008}, /* GPO18: GENCFG bit 19 */
1354{0xB2, 0x0010, 0x0010}, /* GPO19: GENCFG bit 20 */
1355{0xB2, 0x0020, 0x0020}, /* GPO20: GENCFG bit 21 */
1356{0xB2, 0x0040, 0x0040}, /* GPO21: GENCFG bit 22 */
1357{0xB2, 0x1000, 0x1000}, /* GPO22... */
1358{0xB2, 0x1000, 0x1000}, /* ...GPO23: GENCFG bit 28 */
1359{0xB2, 0x2000, 0x2000}, /* GPO24: GENCFG bit 29 */
1360{0xB2, 0x4000, 0x4000}, /* GPO25: GENCFG bit 30 */
1361{0xB2, 0x8000, 0x8000}, /* GPO26: GENCFG bit 31 */
1362{0},
1363{0},
1364{0x4E, 0x0100, 0x0000}, /* ...GPO29: XBCS bit 8 */
1365{0}
1366};
1367
1368dev = pci_dev_find(0x8086, 0x7110);/* Intel PIIX4 ISA bridge */
1369if (!dev) {
1370msg_perr("\nERROR: Intel PIIX4 ISA bridge not found.\n");
1371return -1;
1372}
1373
1374/* Sanity check. */
1375if (gpo > 30) {
1376msg_perr("\nERROR: Intel PIIX4 has no GPO%d.\n", gpo);
1377return -1;
1378}
1379
1380if ((((1 << gpo) & nonmuxed_gpos) == 0) &&
1381 ((pci_read_word(dev, piix4_gpo[gpo].reg) & piix4_gpo[gpo].mask) !=
1382 piix4_gpo[gpo].value)) {
1383msg_perr("\nERROR: PIIX4 GPO%d not programmed for output.\n", gpo);
1384return -1;
1385}
1386
1387dev = pci_dev_find(0x8086, 0x7113);/* Intel PIIX4 PM */
1388if (!dev) {
1389msg_perr("\nERROR: Intel PIIX4 PM not found.\n");
1390return -1;
1391}
1392
1393/* PM IO base */
1394base = pci_read_long(dev, 0x40) & 0x0000FFC0;
1395
1396gpo_byte = gpo >> 3;
1397gpo_bit = gpo & 7;
1398tmp = INB(base + 0x34 + gpo_byte); /* GPO register */
1399if (raise)
1400tmp |= 0x01 << gpo_bit;
1401else
1402tmp &= ~(0x01 << gpo_bit);
1403OUTB(tmp, base + 0x34 + gpo_byte);
1404
1405return 0;
1406}
1407
1408/*
1409 * Suited for:
1410 * - ASUS OPLX-M
1411 * - ASUS P2B-N
1412 */
1413static int intel_piix4_gpo18_lower(void)
1414{
1415return intel_piix4_gpo_set(18, 0);
1416}
1417
1418/*
1419 * Suited for:
1420 * - MSI MS-6163 v2 (MS-6163 Pro): Intel 440BX + PIIX4E + Winbond W83977EF
1421 */
1422static int intel_piix4_gpo14_raise(void)
1423{
1424return intel_piix4_gpo_set(14, 1);
1425}
1426
1427/*
1428 * Suited for:
1429 * - EPoX EP-BX3
1430 */
1431static int intel_piix4_gpo22_raise(void)
1432{
1433return intel_piix4_gpo_set(22, 1);
1434}
1435
1436/*
1437 * Suited for:
1438 * - abit BM6
1439 */
1440static int intel_piix4_gpo26_lower(void)
1441{
1442return intel_piix4_gpo_set(26, 0);
1443}
1444
1445/*
1446 * Suited for:
1447 * - Intel SE440BX-2
1448 */
1449static int intel_piix4_gpo27_lower(void)
1450{
1451return intel_piix4_gpo_set(27, 0);
1452}
1453
1454/*
1455 * Suited for:
1456 * - Dell OptiPlex GX1
1457 */
1458static int intel_piix4_gpo30_lower(void)
1459{
1460return intel_piix4_gpo_set(30, 0);
1461}
1462
1463/*
1464 * Set a GPIO line on a given Intel ICH LPC controller.
1465 */
1466static int intel_ich_gpio_set(int gpio, int raise)
1467{
1468/* Table mapping the different Intel ICH LPC chipsets. */
1469static struct {
1470uint16_t id;
1471uint8_t base_reg;
1472uint32_t bank0;
1473uint32_t bank1;
1474uint32_t bank2;
1475} intel_ich_gpio_table[] = {
1476{0x2410, 0x58, 0x0FE30000, 0, 0}, /* 82801AA (ICH) */
1477{0x2420, 0x58, 0x0FE30000, 0, 0}, /* 82801AB (ICH0) */
1478{0x2440, 0x58, 0x1BFF391B, 0, 0}, /* 82801BA (ICH2) */
1479{0x244C, 0x58, 0x1A23399B, 0, 0}, /* 82801BAM (ICH2M) */
1480{0x2450, 0x58, 0x1BFF0000, 0, 0}, /* 82801E (C-ICH) */
1481{0x2480, 0x58, 0x1BFF0000, 0x00000FFF, 0}, /* 82801CA (ICH3-S) */
1482{0x248C, 0x58, 0x1A230000, 0x00000FFF, 0}, /* 82801CAM (ICH3-M) */
1483{0x24C0, 0x58, 0x1BFF0000, 0x00000FFF, 0}, /* 82801DB/DBL (ICH4/ICH4-L) */
1484{0x24CC, 0x58, 0x1A030000, 0x00000FFF, 0}, /* 82801DBM (ICH4-M) */
1485{0x24D0, 0x58, 0x1BFF0000, 0x00030305, 0}, /* 82801EB/ER (ICH5/ICH5R) */
1486{0x2640, 0x48, 0x1BFF0000, 0x00030307, 0}, /* 82801FB/FR (ICH6/ICH6R) */
1487{0x2641, 0x48, 0x1BFF0000, 0x00030307, 0}, /* 82801FBM (ICH6M) */
1488{0x27B0, 0x48, 0xFFFFFFFF, 0x000300FF, 0}, /* 82801GDH (ICH7 DH) */
1489{0x27B8, 0x48, 0xFFFFFFFF, 0x000300FF, 0}, /* 82801GB/GR (ICH7 Family) */
1490{0x27B9, 0x48, 0xFFEBFFFE, 0x000300FE, 0}, /* 82801GBM (ICH7-M) */
1491{0x27BD, 0x48, 0xFFEBFFFE, 0x000300FE, 0}, /* 82801GHM (ICH7-M DH) */
1492{0x2810, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HB/HR (ICH8/R) */
1493{0x2811, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HBM (ICH8M-E) */
1494{0x2812, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HH (ICH8DH) */
1495{0x2814, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HO (ICH8DO) */
1496{0x2815, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HEM (ICH8M) */
1497{0x2912, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IH (ICH9DH) */
1498{0x2914, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IO (ICH9DO) */
1499{0x2916, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IR (ICH9R) */
1500{0x2917, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IEM (ICH9M-E) */
1501{0x2918, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IB (ICH9) */
1502{0x2919, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IBM (ICH9M) */
1503{0x3A14, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JDO (ICH10DO) */
1504{0x3A16, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JIR (ICH10R) */
1505{0x3A18, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JIB (ICH10) */
1506{0x3A1A, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JD (ICH10D) */
1507{0, 0, 0, 0, 0} /* end marker */
1508};
1509
1510struct pci_dev *dev;
1511uint16_t base;
1512uint32_t tmp;
1513int i, allowed;
1514
1515/* First, look for a known LPC bridge */
1516for (dev = pacc->devices; dev; dev = dev->next) {
1517uint16_t device_class;
1518/* libpci before version 2.2.4 does not store class info. */
1519device_class = pci_read_word(dev, PCI_CLASS_DEVICE);
1520if ((dev->vendor_id == 0x8086) &&
1521 (device_class == 0x0601)) { /* ISA bridge */
1522/* Is this device in our list? */
1523for (i = 0; intel_ich_gpio_table[i].id; i++)
1524if (dev->device_id == intel_ich_gpio_table[i].id)
1525break;
1526
1527if (intel_ich_gpio_table[i].id)
1528break;
1529}
1530}
1531
1532if (!dev) {
1533msg_perr("\nERROR: No known Intel LPC bridge found.\n");
1534return -1;
1535}
1536
1537/*
1538 * According to the datasheets, all Intel ICHs have the GPIO bar 5:1
1539 * strapped to zero. From some mobile ICH9 version on, this becomes
1540 * 6:1. The mask below catches all.
1541 */
1542base = pci_read_word(dev, intel_ich_gpio_table[i].base_reg) & 0xFFC0;
1543
1544/* Check whether the line is allowed. */
1545if (gpio < 32)
1546allowed = (intel_ich_gpio_table[i].bank0 >> gpio) & 0x01;
1547else if (gpio < 64)
1548allowed = (intel_ich_gpio_table[i].bank1 >> (gpio - 32)) & 0x01;
1549else
1550allowed = (intel_ich_gpio_table[i].bank2 >> (gpio - 64)) & 0x01;
1551
1552if (!allowed) {
1553msg_perr("\nERROR: This Intel LPC bridge does not allow"
1554 " setting GPIO%02d\n", gpio);
1555return -1;
1556}
1557
1558msg_pdbg("\nIntel ICH LPC bridge: %sing GPIO%02d.\n",
1559 raise ? "Rais" : "Dropp", gpio);
1560
1561if (gpio < 32) {
1562/* Set line to GPIO. */
1563tmp = INL(base);
1564/* ICH/ICH0 multiplexes 27/28 on the line set. */
1565if ((gpio == 28) &&
1566 ((dev->device_id == 0x2410) || (dev->device_id == 0x2420)))
1567tmp |= 1 << 27;
1568else
1569tmp |= 1 << gpio;
1570OUTL(tmp, base);
1571
1572/* As soon as we are talking to ICH8 and above, this register
1573 decides whether we can set the gpio or not. */
1574if (dev->device_id > 0x2800) {
1575tmp = INL(base);
1576if (!(tmp & (1 << gpio))) {
1577msg_perr("\nERROR: This Intel LPC bridge"
1578" does not allow setting GPIO%02d\n",
1579gpio);
1580return -1;
1581}
1582}
1583
1584/* Set GPIO to OUTPUT. */
1585tmp = INL(base + 0x04);
1586tmp &= ~(1 << gpio);
1587OUTL(tmp, base + 0x04);
1588
1589/* Raise GPIO line. */
1590tmp = INL(base + 0x0C);
1591if (raise)
1592tmp |= 1 << gpio;
1593else
1594tmp &= ~(1 << gpio);
1595OUTL(tmp, base + 0x0C);
1596} else if (gpio < 64) {
1597gpio -= 32;
1598
1599/* Set line to GPIO. */
1600tmp = INL(base + 0x30);
1601tmp |= 1 << gpio;
1602OUTL(tmp, base + 0x30);
1603
1604/* As soon as we are talking to ICH8 and above, this register
1605 decides whether we can set the gpio or not. */
1606if (dev->device_id > 0x2800) {
1607tmp = INL(base + 30);
1608if (!(tmp & (1 << gpio))) {
1609msg_perr("\nERROR: This Intel LPC bridge"
1610" does not allow setting GPIO%02d\n",
1611gpio + 32);
1612return -1;
1613}
1614}
1615
1616/* Set GPIO to OUTPUT. */
1617tmp = INL(base + 0x34);
1618tmp &= ~(1 << gpio);
1619OUTL(tmp, base + 0x34);
1620
1621/* Raise GPIO line. */
1622tmp = INL(base + 0x38);
1623if (raise)
1624tmp |= 1 << gpio;
1625else
1626tmp &= ~(1 << gpio);
1627OUTL(tmp, base + 0x38);
1628} else {
1629gpio -= 64;
1630
1631/* Set line to GPIO. */
1632tmp = INL(base + 0x40);
1633tmp |= 1 << gpio;
1634OUTL(tmp, base + 0x40);
1635
1636tmp = INL(base + 40);
1637if (!(tmp & (1 << gpio))) {
1638msg_perr("\nERROR: This Intel LPC bridge does "
1639"not allow setting GPIO%02d\n", gpio + 64);
1640return -1;
1641}
1642
1643/* Set GPIO to OUTPUT. */
1644tmp = INL(base + 0x44);
1645tmp &= ~(1 << gpio);
1646OUTL(tmp, base + 0x44);
1647
1648/* Raise GPIO line. */
1649tmp = INL(base + 0x48);
1650if (raise)
1651tmp |= 1 << gpio;
1652else
1653tmp &= ~(1 << gpio);
1654OUTL(tmp, base + 0x48);
1655}
1656
1657return 0;
1658}
1659
1660/*
1661 * Suited for:
1662 * - abit IP35: Intel P35 + ICH9R
1663 * - abit IP35 Pro: Intel P35 + ICH9R
1664 * - ASUS P5LD2
1665 * - ASUS P5LD2-MQ
1666 * - ASUS P5LD2-VM
1667 * - ASUS P5LD2-VM DH
1668 */
1669static int intel_ich_gpio16_raise(void)
1670{
1671return intel_ich_gpio_set(16, 1);
1672}
1673
1674/*
1675 * Suited for:
1676 * - HP Puffer2-UL8E (ASUS PTGD-LA OEM): LGA775 + 915 + ICH6
1677 */
1678static int intel_ich_gpio18_raise(void)
1679{
1680return intel_ich_gpio_set(18, 1);
1681}
1682
1683/*
1684 * Suited for:
1685 * - MSI MS-7046: LGA775 + 915P + ICH6
1686 */
1687static int intel_ich_gpio19_raise(void)
1688{
1689return intel_ich_gpio_set(19, 1);
1690}
1691
1692/*
1693 * Suited for:
1694 * - ASUS P5BV-R: LGA775 + 3200 + ICH7
1695 */
1696static int intel_ich_gpio20_raise(void)
1697{
1698return intel_ich_gpio_set(20, 1);
1699}
1700
1701/*
1702 * Suited for:
1703 * - ASUS CUSL2-C: Intel socket370 + 815 + ICH2
1704 * - ASUS P4B266LM (Sony Vaio PCV-RX650): socket478 + 845D + ICH2
1705 * - ASUS P4C800-E Deluxe: socket478 + 875P + ICH5
1706 * - ASUS P4P800: Intel socket478 + 865PE + ICH5R
1707 * - ASUS P4P800-E Deluxe: Intel socket478 + 865PE + ICH5R
1708 * - ASUS P4P800-VM: Intel socket478 + 865PE + ICH5R
1709 * - ASUS P4P800-X: Intel socket478 + 865PE + ICH5R
1710 * - ASUS P5GD1 Pro: Intel LGA 775 + 915P + ICH6R
1711 * - ASUS P5GD2 Premium: Intel LGA775 + 915G + ICH6R
1712 * - ASUS P5GDC Deluxe: Intel socket775 + 915P + ICH6R
1713 * - ASUS P5PE-VM: Intel LGA775 + 865G + ICH5
1714 * - ASUS TUSL2-C: Intel socket370 + 815 + ICH2
1715 * - Samsung Polaris 32: socket478 + 865P + ICH5
1716 */
1717static int intel_ich_gpio21_raise(void)
1718{
1719return intel_ich_gpio_set(21, 1);
1720}
1721
1722/*
1723 * Suited for:
1724 * - ASUS P4B266: socket478 + Intel 845D + ICH2
1725 * - ASUS P4B533-E: socket478 + 845E + ICH4
1726 * - ASUS P4B-MX variant in HP Vectra VL420 SFF: socket478 + 845D + ICH2
1727 * - TriGem Anaheim-3: socket370 + Intel 810 + ICH
1728 */
1729static int intel_ich_gpio22_raise(void)
1730{
1731return intel_ich_gpio_set(22, 1);
1732}
1733
1734/*
1735 * Suited for:
1736 * - ASUS A8Jm (laptop): Intel 945 + ICH7
1737 * - ASUS P5LP-LE used in ...
1738 * - HP Media Center m7270.fr Desktop PC as "Lithium-UL8E"
1739 * - Epson Endeavor MT7700
1740 */
1741static int intel_ich_gpio34_raise(void)
1742{
1743return intel_ich_gpio_set(34, 1);
1744}
1745
1746/*
1747 * Suited for:
1748 * - AOpen i945GMx-VFX: Intel 945GM + ICH7-M used in ...
1749 * - FSC ESPRIMO Q5010 (SMBIOS: D2544-B1)
1750 */
1751static int intel_ich_gpio38_raise(void)
1752{
1753return intel_ich_gpio_set(38, 1);
1754}
1755
1756/*
1757 * Suited for:
1758 * - ASUS M6Ne (laptop): socket 479M (guessed) + Intel 855PM + ICH4-M
1759 */
1760static int intel_ich_gpio43_raise(void)
1761{
1762return intel_ich_gpio_set(43, 1);
1763}
1764
1765/*
1766 * Suited for:
1767 * - HP Vectra VL400: 815 + ICH + PC87360
1768 */
1769static int board_hp_vl400(void)
1770{
1771int ret;
1772ret = intel_ich_gpio_set(25, 1);/* Master write enable ? */
1773if (!ret)
1774ret = pc8736x_gpio_set(PC87360_ID, 0x09, 1);/* #WP ? */
1775if (!ret)
1776ret = pc8736x_gpio_set(PC87360_ID, 0x27, 1);/* #TBL */
1777return ret;
1778}
1779
1780/*
1781 * Suited for:
1782 * - HP e-Vectra P2706T: 810E + ICH + PC87364
1783 */
1784static int board_hp_p2706t(void)
1785{
1786int ret;
1787ret = pc8736x_gpio_set(PC87364_ID, 0x25, 1);
1788if (!ret)
1789ret = pc8736x_gpio_set(PC87364_ID, 0x26, 1);
1790return ret;
1791}
1792
1793/*
1794 * Suited for:
1795 * - Dell PowerEdge 1850: Intel PPGA604 + E7520 + ICH5R
1796 * - ASRock P4i65GV: Intel Socket478 + 865GV + ICH5R
1797 * - ASRock 775i65G: Intel LGA 775 + 865G + ICH5
1798 * - MSI MS-6391 (845 Pro4): Intel Socket478 + 845 + ICH2
1799 */
1800static int intel_ich_gpio23_raise(void)
1801{
1802return intel_ich_gpio_set(23, 1);
1803}
1804
1805/*
1806 * Suited for:
1807 * - GIGABYTE GA-6IEM: Intel Socket370 + i815 + ICH2
1808 * - GIGABYTE GA-8IRML: Intel Socket478 + i845 + ICH2
1809 */
1810static int intel_ich_gpio25_raise(void)
1811{
1812return intel_ich_gpio_set(25, 1);
1813}
1814
1815/*
1816 * Suited for:
1817 * - IBASE MB899: i945GM + ICH7
1818 */
1819static int intel_ich_gpio26_raise(void)
1820{
1821return intel_ich_gpio_set(26, 1);
1822}
1823
1824/*
1825 * Suited for:
1826 * - ASUS DSAN-DX
1827 * - P4SD-LA (HP OEM): i865 + ICH5
1828 * - GIGABYTE GA-8IP775: 865P + ICH5
1829 * - GIGABYTE GA-8PE667 Ultra 2: socket 478 + i845PE + ICH4
1830 * - MSI MS-6788-40 (aka 848P Neo-V)
1831 */
1832static int intel_ich_gpio32_raise(void)
1833{
1834return intel_ich_gpio_set(32, 1);
1835}
1836
1837/*
1838 * Suited for:
1839 * - AOpen i975Xa-YDG: i975X + ICH7 + W83627EHF
1840 */
1841static int board_aopen_i975xa_ydg(void)
1842{
1843int ret;
1844
1845/* Vendor BIOS ends up in LDN6... maybe the board enable is wrong,
1846 * or perhaps it's not needed at all?
1847 * The regs it tries to touch are 0xF0, 0xF1, 0xF2 which means if it
1848 * were in the right LDN, it would have to be GPIO1 or GPIO3.
1849 */
1850/*
1851ret = winbond_gpio_set(0x2e, WINBOND_W83627EHF_ID, x, 0)
1852if (!ret)
1853*/
1854ret = intel_ich_gpio_set(33, 1);
1855
1856return ret;
1857}
1858
1859/*
1860 * Suited for:
1861 * - Acorp 6A815EPD: socket 370 + intel 815 + ICH2
1862 */
1863static int board_acorp_6a815epd(void)
1864{
1865int ret;
1866
1867/* Lower Blocks Lock -- pin 7 of PLCC32 */
1868ret = intel_ich_gpio_set(22, 1);
1869if (!ret) /* Top Block Lock -- pin 8 of PLCC32 */
1870ret = intel_ich_gpio_set(23, 1);
1871
1872return ret;
1873}
1874
1875/*
1876 * Suited for:
1877 * - Kontron 986LCD-M: Socket478 + 915GM + ICH7R
1878 */
1879static int board_kontron_986lcd_m(void)
1880{
1881int ret;
1882
1883ret = intel_ich_gpio_set(34, 1); /* #TBL */
1884if (!ret)
1885ret = intel_ich_gpio_set(35, 1); /* #WP */
1886
1887return ret;
1888}
1889
1890/*
1891 * Suited for:
1892 * - Soyo SY-7VCA: Pro133A + VT82C686
1893 */
1894static int via_apollo_gpo_set(int gpio, int raise)
1895{
1896struct pci_dev *dev;
1897uint32_t base, tmp;
1898
1899/* VT82C686 power management */
1900dev = pci_dev_find(0x1106, 0x3057);
1901if (!dev) {
1902msg_perr("\nERROR: VT82C686 PM device not found.\n");
1903return -1;
1904}
1905
1906msg_pdbg("\nVIA Apollo ACPI: %sing GPIO%02d.\n",
1907 raise ? "Rais" : "Dropp", gpio);
1908
1909/* Select GPO function on multiplexed pins. */
1910tmp = pci_read_byte(dev, 0x54);
1911switch (gpio) {
1912case 0:
1913tmp &= ~0x03;
1914break;
1915case 1:
1916tmp |= 0x04;
1917break;
1918case 2:
1919tmp |= 0x08;
1920break;
1921case 3:
1922tmp |= 0x10;
1923break;
1924}
1925pci_write_byte(dev, 0x54, tmp);
1926
1927/* PM IO base */
1928base = pci_read_long(dev, 0x48) & 0x0000FF00;
1929
1930/* Drop GPO0 */
1931tmp = INL(base + 0x4C);
1932if (raise)
1933tmp |= 1U << gpio;
1934else
1935tmp &= ~(1U << gpio);
1936OUTL(tmp, base + 0x4C);
1937
1938return 0;
1939}
1940
1941/*
1942 * Suited for:
1943 * - abit VT6X4: Pro133x + VT82C686A
1944 * - abit VA6: Pro133x + VT82C686A
1945 */
1946static int via_apollo_gpo4_lower(void)
1947{
1948return via_apollo_gpo_set(4, 0);
1949}
1950
1951/*
1952 * Suited for:
1953 * - Soyo SY-7VCA: Pro133A + VT82C686
1954 */
1955static int via_apollo_gpo0_lower(void)
1956{
1957return via_apollo_gpo_set(0, 0);
1958}
1959
1960/*
1961 * Enable some GPIO pin on SiS southbridge and enables SIO flash writes.
1962 *
1963 * Suited for:
1964 * - MSI 651M-L: SiS651 / SiS962
1965 * - GIGABYTE GA-8SIMLFS 2.0
1966 * - GIGABYTE GA-8SIMLH
1967 */
1968static int sis_gpio0_raise_and_w836xx_memw(void)
1969{
1970struct pci_dev *dev;
1971uint16_t base, temp;
1972
1973dev = pci_dev_find(0x1039, 0x0962);
1974if (!dev) {
1975msg_perr("Expected south bridge not found\n");
1976return 1;
1977}
1978
1979base = pci_read_word(dev, 0x74);
1980temp = INW(base + 0x68);
1981temp &= ~(1 << 0);/* Make pin output? */
1982OUTW(temp, base + 0x68);
1983
1984temp = INW(base + 0x64);
1985temp |= (1 << 0);/* Raise output? */
1986OUTW(temp, base + 0x64);
1987
1988w836xx_memw_enable(0x2E);
1989
1990return 0;
1991}
1992
1993/*
1994 * Find the runtime registers of an SMSC Super I/O, after verifying its
1995 * chip ID.
1996 *
1997 * Returns the base port of the runtime register block, or 0 on error.
1998 */
1999static uint16_t smsc_find_runtime(uint16_t sio_port, uint16_t chip_id,
2000 uint8_t logical_device)
2001{
2002uint16_t rt_port = 0;
2003
2004/* Verify the chip ID. */
2005OUTB(0x55, sio_port); /* Enable configuration. */
2006if (sio_read(sio_port, 0x20) != chip_id) {
2007msg_perr("\nERROR: SMSC Super I/O not found.\n");
2008goto out;
2009}
2010
2011/* If the runtime block is active, get its address. */
2012sio_write(sio_port, 0x07, logical_device);
2013if (sio_read(sio_port, 0x30) & 1) {
2014rt_port = (sio_read(sio_port, 0x60) << 8)
2015 | sio_read(sio_port, 0x61);
2016}
2017
2018if (rt_port == 0) {
2019msg_perr("\nERROR: "
2020"Super I/O runtime interface not available.\n");
2021}
2022out:
2023OUTB(0xaa, sio_port); /* Disable configuration. */
2024return rt_port;
2025}
2026
2027/*
2028 * Disable write protection on the Mitac 6513WU. WP# on the FWH is
2029 * connected to GP30 on the Super I/O, and TBL# is always high.
2030 */
2031static int board_mitac_6513wu(void)
2032{
2033struct pci_dev *dev;
2034uint16_t rt_port;
2035uint8_t val;
2036
2037dev = pci_dev_find(0x8086, 0x2410);/* Intel 82801AA ISA bridge */
2038if (!dev) {
2039msg_perr("\nERROR: Intel 82801AA ISA bridge not found.\n");
2040return -1;
2041}
2042
2043rt_port = smsc_find_runtime(0x4e, 0x54 /* LPC47U33x */, 0xa);
2044if (rt_port == 0)
2045return -1;
2046
2047/* Configure the GPIO pin. */
2048val = INB(rt_port + 0x33); /* GP30 config */
2049val &= ~0x87; /* Output, non-inverted, GPIO, push/pull */
2050OUTB(val, rt_port + 0x33);
2051
2052/* Disable write protection. */
2053val = INB(rt_port + 0x4d); /* GP3 values */
2054val |= 0x01; /* Set GP30 high. */
2055OUTB(val, rt_port + 0x4d);
2056
2057return 0;
2058}
2059
2060/*
2061 * Suited for:
2062 * - abit AV8: Socket939 + K8T800Pro + VT8237
2063 */
2064static int board_abit_av8(void)
2065{
2066uint8_t val;
2067
2068/* Raise GPO pins GP22 & GP23 */
2069val = INB(0x404E);
2070val |= 0xC0;
2071OUTB(val, 0x404E);
2072
2073return 0;
2074}
2075
2076/*
2077 * Suited for:
2078 * - ASUS A7V333: VIA KT333 + VT8233A + IT8703F
2079 * - ASUS A7V8X: VIA KT400 + VT8235 + IT8703F
2080 */
2081static int it8703f_gpio51_raise(void)
2082{
2083uint16_t id, base;
2084uint8_t tmp;
2085
2086/* Find the IT8703F. */
2087w836xx_ext_enter(0x2E);
2088id = (sio_read(0x2E, 0x20) << 8) | sio_read(0x2E, 0x21);
2089w836xx_ext_leave(0x2E);
2090
2091if (id != 0x8701) {
2092msg_perr("\nERROR: IT8703F Super I/O not found.\n");
2093return -1;
2094}
2095
2096/* Get the GP567 I/O base. */
2097w836xx_ext_enter(0x2E);
2098sio_write(0x2E, 0x07, 0x0C);
2099base = (sio_read(0x2E, 0x60) << 8) | sio_read(0x2E, 0x61);
2100w836xx_ext_leave(0x2E);
2101
2102if (!base) {
2103msg_perr("\nERROR: Failed to read IT8703F Super I/O GPIO"
2104" Base.\n");
2105return -1;
2106}
2107
2108/* Raise GP51. */
2109tmp = INB(base);
2110tmp |= 0x02;
2111OUTB(tmp, base);
2112
2113return 0;
2114}
2115
2116/*
2117 * General routine for raising/dropping GPIO lines on the ITE IT87xx.
2118 */
2119static int it87_gpio_set(unsigned int gpio, int raise)
2120{
2121int allowed, sio;
2122unsigned int port;
2123uint16_t base, sioport;
2124uint8_t tmp;
2125
2126/* IT87 GPIO configuration table */
2127static const struct it87cfg {
2128uint16_t id;
2129uint8_t base_reg;
2130uint32_t bank0;
2131uint32_t bank1;
2132uint32_t bank2;
2133} it87_gpio_table[] = {
2134{0x8712, 0x62, 0xCFF3FC00, 0x00FCFF3F, 0},
2135{0x8718, 0x62, 0xCFF37C00, 0xF3FCDF3F, 0x0000000F},
2136{0, 0, 0, 0, 0} /* end marker */
2137};
2138const struct it87cfg *cfg = NULL;
2139
2140/* Find the Super I/O in the probed list */
2141for (sio = 0; sio < superio_count; sio++) {
2142int i;
2143if (superios[sio].vendor != SUPERIO_VENDOR_ITE)
2144continue;
2145
2146/* Is this device in our list? */
2147for (i = 0; it87_gpio_table[i].id; i++)
2148if (superios[sio].model == it87_gpio_table[i].id) {
2149cfg = &it87_gpio_table[i];
2150goto found;
2151}
2152}
2153
2154if (cfg == NULL) {
2155msg_perr("\nERROR: No IT87 Super I/O GPIO configuration "
2156 "found.\n");
2157return -1;
2158}
2159
2160found:
2161/* Check whether the gpio is allowed. */
2162if (gpio < 32)
2163allowed = (cfg->bank0 >> gpio) & 0x01;
2164else if (gpio < 64)
2165allowed = (cfg->bank1 >> (gpio - 32)) & 0x01;
2166else if (gpio < 96)
2167allowed = (cfg->bank2 >> (gpio - 64)) & 0x01;
2168else
2169allowed = 0;
2170
2171if (!allowed) {
2172msg_perr("\nERROR: IT%02X does not allow setting GPIO%02u.\n",
2173 cfg->id, gpio);
2174return -1;
2175}
2176
2177/* Read the Simple I/O Base Address Register */
2178sioport = superios[sio].port;
2179enter_conf_mode_ite(sioport);
2180sio_write(sioport, 0x07, 0x07);
2181base = (sio_read(sioport, cfg->base_reg) << 8) |
2182sio_read(sioport, cfg->base_reg + 1);
2183exit_conf_mode_ite(sioport);
2184
2185if (!base) {
2186msg_perr("\nERROR: Failed to read IT87 Super I/O GPIO Base.\n");
2187return -1;
2188}
2189
2190msg_pdbg("Using IT87 GPIO base 0x%04x\n", base);
2191
2192port = gpio / 10 - 1;
2193gpio %= 10;
2194
2195/* set GPIO. */
2196tmp = INB(base + port);
2197if (raise)
2198tmp |= 1 << gpio;
2199else
2200tmp &= ~(1 << gpio);
2201OUTB(tmp, base + port);
2202
2203return 0;
2204}
2205
2206/*
2207 * Suited for:
2208 * - ASUS A7N8X-VM/400: NVIDIA nForce2 IGP2 + IT8712F
2209 */
2210static int it8712f_gpio12_raise(void)
2211{
2212return it87_gpio_set(12, 1);
2213}
2214
2215/*
2216 * Suited for:
2217 * - ASUS A7V600-X: VIA KT600 + VT8237 + IT8712F
2218 * - ASUS A7V8X-X: VIA KT400 + VT8235 + IT8712F
2219 */
2220static int it8712f_gpio31_raise(void)
2221{
2222return it87_gpio_set(32, 1);
2223}
2224
2225/*
2226 * Suited for:
2227 * - ASUS P5N-D: NVIDIA MCP51 + IT8718F
2228 * - ASUS P5N-E SLI: NVIDIA MCP51 + IT8718F
2229 */
2230static int it8718f_gpio63_raise(void)
2231{
2232return it87_gpio_set(63, 1);
2233}
2234
2235/*
2236 * Suited for all boards with ambiguous DMI chassis information, which should be
2237 * whitelisted because they are known to work:
2238 * - ASRock IMB-A180(-H)
2239 * - Intel D945GCNL
2240 * - MSC Q7 Tunnel Creek Module (Q7-TCTC)
2241 */
2242static int p2_not_a_laptop(void)
2243{
2244/* label this board as not a laptop */
2245is_laptop = 0;
2246msg_pdbg("Laptop detection overridden by P2 board enable.\n");
2247return 0;
2248}
2249
2250/*
2251 * Suited for all laptops, which are known to *not* have interfering embedded controllers.
2252 */
2253static int p2_whitelist_laptop(void)
2254{
2255is_laptop = 1;
2256laptop_ok = 1;
2257msg_pdbg("Whitelisted laptop detected.\n");
2258return 0;
2259}
2260
2261#endif
2262
2263/*
2264 * Below is the list of boards which need a special "board enable" code in
2265 * flashrom before their ROM chip can be accessed/written to.
2266 *
2267 * NOTE: Please add boards that _don't_ need such enables or don't work yet
2268 * to the respective tables in print.c. Thanks!
2269 *
2270 * We use 2 sets of PCI IDs here, you're free to choose which is which. This
2271 * is to provide a very high degree of certainty when matching a board on
2272 * the basis of subsystem/card IDs. As not every vendor handles
2273 * subsystem/card IDs in a sane manner.
2274 *
2275 * Keep the second set NULLed if it should be ignored. Keep the subsystem IDs
2276 * and the dmi identifier NULLed if they don't identify the board fully to disable autodetection.
2277 * But please take care to provide an as complete set of pci ids as possible;
2278 * autodetection is the preferred behaviour and we would like to make sure that
2279 * matches are unique.
2280 *
2281 * If PCI IDs are not sufficient for board matching, the match can be further
2282 * constrained by a string that has to be present in the DMI database for
2283 * the baseboard or the system entry. The pattern is matched by case sensitive
2284 * substring match, unless it is anchored to the beginning (with a ^ in front)
2285 * or the end (with a $ at the end). Both anchors may be specified at the
2286 * same time to match the full field.
2287 *
2288 * When a board is matched through DMI, the first and second main PCI IDs
2289 * and the first subsystem PCI ID have to match as well. If you specify the
2290 * first subsystem ID as 0x0:0x0, the DMI matching code expects that the
2291 * subsystem ID of that device is indeed zero.
2292 *
2293 * The coreboot ids are used two fold. When running with a coreboot firmware,
2294 * the ids uniquely matches the coreboot board identification string. When a
2295 * legacy bios is installed and when autodetection is not possible, these ids
2296 * can be used to identify the board through the -p internal:mainboard=
2297 * programmer parameter.
2298 *
2299 * When a board is identified through its coreboot ids (in both cases), the
2300 * main pci ids are still required to match, as a safeguard.
2301 */
2302
2303/* Please keep this list alphabetically ordered by vendor/board name. */
2304const struct board_match board_matches[] = {
2305
2306/* first pci-id set [4], second pci-id set [4], dmi identifier, coreboot id [2], phase, vendor name, board name max_rom_... OK? flash enable */
2307#if defined(__i386__) || defined(__x86_64__)
2308{0x10DE, 0x0547, 0x147B, 0x1C2F, 0x10DE, 0x0548, 0x147B, 0x1C2F, NULL, NULL, NULL, P3, "abit", "AN-M2", 0, NT, nvidia_mcp_gpio2_raise},
2309{0x1106, 0x0282, 0x147B, 0x1415, 0x1106, 0x3227, 0x147B, 0x1415, "^AV8 ", NULL, NULL, P3, "abit", "AV8", 0, OK, board_abit_av8},
2310{0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, NULL /* "^I440BX-W977$" */, "abit", "bf6", P3, "abit", "BF6", 0, OK, intel_piix4_gpo26_lower},
2311{0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^i440BX-W977 (BM6)$", NULL, NULL, P3, "abit", "BM6", 0, OK, intel_piix4_gpo26_lower},
2312{0x8086, 0x24d3, 0x147b, 0x1014, 0x8086, 0x2578, 0x147b, 0x1014, NULL, NULL, NULL, P3, "abit", "IC7", 0, NT, intel_ich_gpio23_raise},
2313{0x8086, 0x2930, 0x147b, 0x1084, 0x11ab, 0x4364, 0x147b, 0x1084, NULL, NULL, NULL, P3, "abit", "IP35", 0, OK, intel_ich_gpio16_raise},
2314{0x8086, 0x2930, 0x147b, 0x1083, 0x10ec, 0x8167, 0x147b, 0x1083, NULL, NULL, NULL, P3, "abit", "IP35 Pro", 0, OK, intel_ich_gpio16_raise},
2315{0x10de, 0x0050, 0x147b, 0x1c1a, 0x10de, 0x0052, 0x147b, 0x1c1a, NULL, NULL, NULL, P3, "abit", "KN8 Ultra", 0, NT, nvidia_mcp_gpio2_lower},
2316{0x10de, 0x0369, 0x147b, 0x1c20, 0x10de, 0x0360, 0x147b, 0x1c20, "^KN9(NF-MCP55 series)$", NULL, NULL, P3, "abit", "KN9 Ultra", 0, OK, nvidia_mcp_gpio2_lower},
2317{0x10de, 0x01e0, 0x147b, 0x1c00, 0x10de, 0x0060, 0x147B, 0x1c00, NULL, NULL, NULL, P3, "abit", "NF7-S", 0, OK, nvidia_mcp_gpio8_raise},
2318{0x10de, 0x02f0, 0x147b, 0x1c26, 0x10de, 0x0260, 0x147b, 0x1c26, NULL, NULL, NULL, P3, "abit", "NF-M2 nView", 0, OK, nvidia_mcp_gpio4_lower},
2319{0x1106, 0x0691, 0, 0, 0x1106, 0x3057, 0, 0, "(VA6)$", NULL, NULL, P3, "abit", "VA6", 0, OK, via_apollo_gpo4_lower},
2320{0x1106, 0x0691, 0, 0, 0x1106, 0x3057, 0, 0, NULL, "abit", "vt6x4", P3, "abit", "VT6X4", 0, OK, via_apollo_gpo4_lower},
2321{0x105a, 0x0d30, 0x105a, 0x4d33, 0x8086, 0x1130, 0x8086, 0, NULL, NULL, NULL, P3, "Acorp", "6A815EPD", 0, OK, board_acorp_6a815epd},
2322{0x1022, 0x746B, 0, 0, 0x1022, 0x7460, 0, 0, NULL, "AGAMI", "ARUMA", P3, "agami", "Aruma", 0, OK, w83627hf_gpio24_raise_2e},
2323{0x1106, 0x3177, 0x17F2, 0x3177, 0x1106, 0x3148, 0x17F2, 0x3148, NULL, NULL, NULL, P3, "Albatron", "PM266A Pro", 0, OK, w836xx_memw_enable_2e},
2324{0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe61", P3, "Artec Group", "DBE61", 0, OK, board_artecgroup_dbe6x},
2325{0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe62", P3, "Artec Group", "DBE62", 0, OK, board_artecgroup_dbe6x},
2326{0x8086, 0x27b9, 0xa0a0, 0x0632, 0x8086, 0x27da, 0xa0a0, 0x0632, NULL, NULL, NULL, P3, "AOpen", "i945GMx-VFX", 0, OK, intel_ich_gpio38_raise},
2327{0x8086, 0x277c, 0xa0a0, 0x060b, 0x8086, 0x27da, 0xa0a0, 0x060b, NULL, NULL, NULL, P3, "AOpen", "i975Xa-YDG", 0, OK, board_aopen_i975xa_ydg},
2328{0x8086, 0x27A0, 0x8086, 0x7270, 0x8086, 0x27B9, 0x8086, 0x7270, "^MacBook2,1$", NULL, NULL, P2, "Apple", "MacBook2,1", 0, OK, p2_whitelist_laptop},
2329{0x8086, 0x27b8, 0x1849, 0x27b8, 0x8086, 0x27da, 0x1849, 0x27da, "^ConRoeXFire-eSATA2", NULL, NULL, P3, "ASRock", "ConRoeXFire-eSATA2", 0, OK, intel_ich_gpio16_raise},
2330{0x1022, 0x1536, 0x1849, 0x1536, 0x1022, 0x780e, 0x1849, 0x780e, "^Kabini CRB$", NULL, NULL, P2, "ASRock", "IMB-A180(-H)", 0, OK, p2_not_a_laptop},
2331{0x1039, 0x0741, 0x1849, 0x0741, 0x1039, 0x5513, 0x1849, 0x5513, "^K7S41 $", NULL, NULL, P3, "ASRock", "K7S41", 0, OK, w836xx_memw_enable_2e},
2332{0x1039, 0x0741, 0x1849, 0x0741, 0x1039, 0x5513, 0x1849, 0x5513, "^K7S41GX$", NULL, NULL, P3, "ASRock", "K7S41GX", 0, OK, w836xx_memw_enable_2e},
2333{0x8086, 0x24D4, 0x1849, 0x24D0, 0x8086, 0x24D5, 0x1849, 0x9739, NULL, NULL, NULL, P3, "ASRock", "P4i65GV", 0, OK, intel_ich_gpio23_raise},
2334{0x8086, 0x2570, 0x1849, 0x2570, 0x8086, 0x24d3, 0x1849, 0x24d0, NULL, NULL, NULL, P3, "ASRock", "775i65G", 0, OK, intel_ich_gpio23_raise},
2335{0x10DE, 0x0060, 0x1043, 0x80AD, 0x10DE, 0x01E0, 0x1043, 0x80C0, NULL, NULL, NULL, P3, "ASUS", "A7N8X-VM/400", 0, OK, it8712f_gpio12_raise},
2336{0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3065, 0x1043, 0x80ED, NULL, NULL, NULL, P3, "ASUS", "A7V600-X", 0, OK, it8712f_gpio31_raise},
2337{0x1106, 0x3177, 0x1043, 0x80F9, 0x1106, 0x3205, 0x1043, 0x80F9, NULL, NULL, NULL, P3, "ASUS", "A7V8X-MX", 0, OK, w836xx_memw_enable_2e},
2338{0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118, NULL, NULL, NULL, P3, "ASUS", "A7V8X-MX SE", 0, OK, w836xx_memw_enable_2e},
2339{0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x808C, NULL, NULL, NULL, P3, "ASUS", "A7V8X", 0, OK, it8703f_gpio51_raise},
2340{0x1106, 0x3099, 0x1043, 0x807F, 0x1106, 0x3147, 0x1043, 0x808C, NULL, NULL, NULL, P3, "ASUS", "A7V333", 0, OK, it8703f_gpio51_raise},
2341{0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x80A1, NULL, NULL, NULL, P3, "ASUS", "A7V8X-X", 0, OK, it8712f_gpio31_raise},
2342{0x1002, 0x4372, 0x103c, 0x2a26, 0x1002, 0x4377, 0x103c, 0x2a26, NULL, NULL, NULL, P3, "ASUS", "A8AE-LE", 0, OK, amd_sbxxx_gpio9_raise},
2343{0x8086, 0x27A0, 0x1043, 0x1287, 0x8086, 0x27DF, 0x1043, 0x1287, "^A8J", NULL, NULL, P3, "ASUS", "A8Jm", 0, NT, intel_ich_gpio34_raise},
2344{0x10DE, 0x0260, 0x103C, 0x2A34, 0x10DE, 0x0264, 0x103C, 0x2A34, "NODUSM3", NULL, NULL, P3, "ASUS", "A8M2N-LA (NodusM3-GL8E)", 0, OK, nvidia_mcp_gpio0_raise},
2345{0x10DE, 0x0260, 0x103c, 0x2a3e, 0x10DE, 0x0264, 0x103c, 0x2a3e, "NAGAMI2L", NULL, NULL, P3, "ASUS", "A8N-LA (Nagami-GL8E)", 0, OK, nvidia_mcp_gpio0_raise},
2346{0x10de, 0x0264, 0x1043, 0x81bc, 0x10de, 0x02f0, 0x1043, 0x81cd, NULL, NULL, NULL, P3, "ASUS", "A8N-VM CSM", 0, OK, w83627ehf_gpio22_raise_2e},
2347{0x8086, 0x65c0, 0x1043, 0x8301, 0x8086, 0x2916, 0x1043, 0x82a6, "^DSAN-DX$", NULL, NULL, P3, "ASUS", "DSAN-DX", 0, NT, intel_ich_gpio32_raise},
2348{0x10DE, 0x0264, 0x1043, 0x81C0, 0x10DE, 0x0260, 0x1043, 0x81C0, NULL, NULL, NULL, P3, "ASUS", "M2NBP-VM CSM", 0, OK, nvidia_mcp_gpio0_raise},
2349{0x1106, 0x1336, 0x1043, 0x80ed, 0x1106, 0x3288, 0x1043, 0x8249, NULL, NULL, NULL, P3, "ASUS", "M2V-MX", 0, OK, via_vt823x_gpio5_raise},
2350{0x8086, 0x24cc, 0, 0, 0x8086, 0x24c3, 0x1043, 0x1869, "^M6Ne$", NULL, NULL, P3, "ASUS", "M6Ne", 0, NT, intel_ich_gpio43_raise},
2351{0x8086, 0x7180, 0, 0, 0x8086, 0x7110, 0, 0, "^OPLX-M$", NULL, NULL, P3, "ASUS", "OPLX-M", 0, NT, intel_piix4_gpo18_lower},
2352{0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^P2B-N$", NULL, NULL, P3, "ASUS", "P2B-N", 0, OK, intel_piix4_gpo18_lower},
2353{0x8086, 0x1A30, 0x1043, 0x8025, 0x8086, 0x244B, 0x104D, 0x80F0, NULL, NULL, NULL, P3, "ASUS", "P4B266-LM", 0, OK, intel_ich_gpio21_raise},
2354{0x8086, 0x1a30, 0x1043, 0x8070, 0x8086, 0x244b, 0x1043, 0x8028, NULL, NULL, NULL, P3, "ASUS", "P4B266", 0, OK, intel_ich_gpio22_raise},
2355{0x8086, 0x1A30, 0x1043, 0x8088, 0x8086, 0x24C3, 0x1043, 0x8089, NULL, NULL, NULL, P3, "ASUS", "P4B533-E", 0, NT, intel_ich_gpio22_raise},
2356{0x8086, 0x2560, 0x103C, 0x2A00, 0x8086, 0x24C3, 0x103C, 0x2A01, "^Guppy", NULL, NULL, P3, "ASUS", "P4GV-LA (Guppy)", 0, OK, intel_ich_gpio21_raise},
2357{0x8086, 0x24D3, 0x1043, 0x80A6, 0x8086, 0x2578, 0x1043, 0x80F6, NULL, NULL, NULL, P3, "ASUS", "P4C800-E Deluxe", 0, OK, intel_ich_gpio21_raise},
2358{0x8086, 0x2570, 0x1043, 0x80F2, 0x8086, 0x24D5, 0x1043, 0x80F3, NULL, NULL, NULL, P3, "ASUS", "P4P800", 0, NT, intel_ich_gpio21_raise},
2359{0x8086, 0x2570, 0x1043, 0x80f2, 0x8086, 0x24d3, 0x1043, 0x80a6, "^P4P800-E$", NULL, NULL, P3, "ASUS", "P4P800-E Deluxe", 0, OK, intel_ich_gpio21_raise},
2360{0x8086, 0x2570, 0x1043, 0x80a5, 0x8086, 0x24d3, 0x1043, 0x80a6, "^P4P800-VM$", NULL, NULL, P3, "ASUS", "P4P800-VM", 0, OK, intel_ich_gpio21_raise},
2361{0x8086, 0x2570, 0x1043, 0x80f2, 0x8086, 0x24d3, 0x1043, 0x80a6, "^P4P800-X$", NULL, NULL, P3, "ASUS", "P4P800-X", 0, OK, intel_ich_gpio21_raise},
2362{0x8086, 0x2570, 0x1043, 0x80b2, 0x8086, 0x24c3, 0x1043, 0x8089, "^P4PE-X/TE$",NULL, NULL, P3, "ASUS", "P4PE-X/TE", 0, NT, intel_ich_gpio21_raise},
2363{0x1039, 0x0651, 0x1043, 0x8081, 0x1039, 0x0962, 0, 0, NULL, NULL, NULL, P3, "ASUS", "P4SC-E", 0, OK, it8707f_write_enable_2e},
2364{0x8086, 0x2570, 0x1043, 0x80A5, 0x105A, 0x24D3, 0x1043, 0x80A6, NULL, NULL, NULL, P3, "ASUS", "P4SD-LA", 0, NT, intel_ich_gpio32_raise},
2365{0x1039, 0x0661, 0x1043, 0x8113, 0x1039, 0x5513, 0x1043, 0x8087, NULL, NULL, NULL, P3, "ASUS", "P4S800-MX", 512, OK, w836xx_memw_enable_2e},
2366{0x10B9, 0x1541, 0, 0, 0x10B9, 0x1533, 0, 0, "^P5A$", "asus", "p5a", P3, "ASUS", "P5A", 0, OK, board_asus_p5a},
2367{0x8086, 0x27b8, 0x1043, 0x819e, 0x8086, 0x29f0, 0x1043, 0x82a5, "^P5BV-R$", NULL, NULL, P3, "ASUS", "P5BV-R", 0, OK, intel_ich_gpio20_raise},
2368{0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x814e, "^P5GD1 PRO$", NULL, NULL, P3, "ASUS", "P5GD1 Pro", 0, OK, intel_ich_gpio21_raise},
2369{0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x814e, "^P5GD1-VM$", NULL, NULL, P3, "ASUS", "P5GD1-VM/S", 0, OK, intel_ich_gpio21_raise},
2370{0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x814e, NULL, NULL, NULL, P3, "ASUS", "P5GD1(-VM)", 0, NT, intel_ich_gpio21_raise},
2371{0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x813d, "^P5GD2-Premium$", NULL, NULL, P3, "ASUS", "P5GD2 Premium", 0, OK, intel_ich_gpio21_raise},
2372{0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x81a6, "^P5GD2-X$", NULL, NULL, P3, "ASUS", "P5GD2-X", 0, OK, intel_ich_gpio21_raise},
2373{0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x813d, "^P5GDC-V$", NULL, NULL, P3, "ASUS", "P5GDC-V Deluxe", 0, OK, intel_ich_gpio21_raise},
2374{0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x813d, "^P5GDC$", NULL, NULL, P3, "ASUS", "P5GDC Deluxe", 0, OK, intel_ich_gpio21_raise},
2375{0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x813d, NULL, NULL, NULL, P3, "ASUS", "P5GD2/C variants", 0, NT, intel_ich_gpio21_raise},
2376{0x8086, 0x27b8, 0x103c, 0x2a22, 0x8086, 0x2770, 0x103c, 0x2a22, "^LITHIUM$", NULL, NULL, P3, "ASUS", "P5LP-LE (Lithium-UL8E)",0, OK, intel_ich_gpio34_raise},
2377{0x8086, 0x27b8, 0x1043, 0x2a22, 0x8086, 0x2770, 0x1043, 0x2a22, "^P5LP-LE$", NULL, NULL, P3, "ASUS", "P5LP-LE (Epson OEM)", 0, OK, intel_ich_gpio34_raise},
2378{0x8086, 0x27da, 0x1043, 0x8179, 0x8086, 0x27b8, 0x1043, 0x8179, "^P5LD2$", NULL, NULL, P3, "ASUS", "P5LD2", 0, OK, intel_ich_gpio16_raise},
2379{0x8086, 0x27da, 0x1043, 0x8179, 0x8086, 0x27b0, 0x1043, 0x8179, "^P5LD2-MQ$", NULL, NULL, P3, "ASUS", "P5LD2-MQ", 0, OK, intel_ich_gpio16_raise},
2380{0x8086, 0x27da, 0x1043, 0x8179, 0x8086, 0x27b8, 0x1043, 0x8179, "^P5LD2-VM$", NULL, NULL, P3, "ASUS", "P5LD2-VM", 0, OK, intel_ich_gpio16_raise},
2381{0x8086, 0x27b0, 0x1043, 0x8179, 0x8086, 0x2770, 0x1043, 0x817a, "^P5LD2-VM DH$", NULL, NULL, P3, "ASUS", "P5LD2-VM DH", 0, OK, intel_ich_gpio16_raise},
2382{0x10DE, 0x0030, 0x1043, 0x818a, 0x8086, 0x100E, 0x1043, 0x80EE, NULL, NULL, NULL, P3, "ASUS", "P5ND2-SLI Deluxe", 0, OK, nvidia_mcp_gpio10_raise},
2383{0x10DE, 0x0260, 0x1043, 0x81BC, 0x10DE, 0x026C, 0x1043, 0x829E, "^P5N-D$", NULL, NULL, P3, "ASUS", "P5N-D", 0, OK, it8718f_gpio63_raise},
2384{0x10DE, 0x0260, 0x1043, 0x81BC, 0x10DE, 0x026C, 0x1043, 0x8249, "^P5N-E SLI$",NULL, NULL, P3, "ASUS", "P5N-E SLI", 0, NT, it8718f_gpio63_raise},
2385{0x8086, 0x24dd, 0x1043, 0x80a6, 0x8086, 0x2570, 0x1043, 0x8157, NULL, NULL, NULL, P3, "ASUS", "P5PE-VM", 0, OK, intel_ich_gpio21_raise},
2386{0x8086, 0x2443, 0x1043, 0x8027, 0x8086, 0x1130, 0x1043, 0x8027, "^CUSL2-C", NULL, NULL, P3, "ASUS", "CUSL2-C", 0, OK, intel_ich_gpio21_raise},
2387{0x8086, 0x2443, 0x1043, 0x8027, 0x8086, 0x1130, 0x1043, 0x8027, "^TUSL2-C", NULL, NULL, P3, "ASUS", "TUSL2-C", 0, NT, intel_ich_gpio21_raise},
2388{0x1022, 0x780E, 0x1043, 0x1437, 0x1022, 0x780B, 0x1043, 0x1437, "^U38N$", NULL, NULL, P2, "ASUS", "U38N", 0, OK, p2_whitelist_laptop},
2389{0x1106, 0x3059, 0x1106, 0x4161, 0x1106, 0x3065, 0x1106, 0x0102, NULL, NULL, NULL, P3, "Bcom/Clientron", "WinNET P680", 0, OK, w836xx_memw_enable_2e},
2390{0x1106, 0x3177, 0x1106, 0x3177, 0x1106, 0x3116, 0x1106, 0x3116, "^KM266-8235$", "biostar", "m7viq", P3, "Biostar", "M7VIQ", 0, NT, w83697xx_memw_enable_2e},
2391{0x8086, 0x283e, 0x1028, 0x01f9, 0x8086, 0x2a01, 0, 0, "^Latitude D630", NULL, NULL, P2, "Dell", "Latitude D630", 0, OK, p2_whitelist_laptop},
2392{0x10b7, 0x9055, 0x1028, 0x0082, 0x8086, 0x7190, 0, 0, NULL, NULL, NULL, P3, "Dell", "OptiPlex GX1", 0, OK, intel_piix4_gpo30_lower},
2393{0x8086, 0x3590, 0x1028, 0x016c, 0x1000, 0x0030, 0x1028, 0x016c, NULL, NULL, NULL, P3, "Dell", "PowerEdge 1850", 0, OK, intel_ich_gpio23_raise},
2394{0x1106, 0x3189, 0x1106, 0x3189, 0x1106, 0x3177, 0x1106, 0x3177, "^AD77", "dfi", "ad77", P3, "DFI", "AD77", 0, NT, w836xx_memw_enable_2e},
2395{0x1039, 0x6325, 0x1019, 0x0f05, 0x1039, 0x0016, 0, 0, NULL, NULL, NULL, P2, "Elitegroup", "A928", 0, OK, p2_whitelist_laptop},
2396{0x10de, 0x03ea, 0x1019, 0x2602, 0x10de, 0x03e0, 0x1019, 0x2602, NULL, NULL, NULL, P3, "Elitegroup", "GeForce6100SM-M", 0, OK, board_ecs_geforce6100sm_m},
2397{0x1106, 0x3038, 0x1019, 0x0996, 0x1106, 0x3177, 0x1019, 0x0996, NULL, NULL, NULL, P3, "Elitegroup", "K7VTA3", 256, OK, NULL},
2398{0x1106, 0x3177, 0x1106, 0x3177, 0x1106, 0x3059, 0x1695, 0x3005, NULL, NULL, NULL, P3, "EPoX", "EP-8K5A2", 0, OK, w836xx_memw_enable_2e},
2399{0x10DE, 0x005E, 0x1695, 0x1010, 0x10DE, 0x0050, 0x1695, 0x1010, "8NPA7I", NULL, NULL, P3, "EPoX", "EP-8NPA7I", 0, OK, nvidia_mcp_gpio4_raise},
2400{0x10DE, 0x005E, 0x1695, 0x1010, 0x10DE, 0x0050, 0x1695, 0x1010, "9NPA7I", NULL, NULL, P3, "EPoX", "EP-9NPA7I", 0, OK, nvidia_mcp_gpio4_raise},
2401{0x10EC, 0x8139, 0x1695, 0x9001, 0x11C1, 0x5811, 0x1695, 0x9015, NULL, NULL, NULL, P3, "EPoX", "EP-8RDA3+", 0, OK, nvidia_mcp_gpio31_raise},
2402{0x8086, 0x7110, 0, 0, 0x8086, 0x7190, 0, 0, NULL, "epox", "ep-bx3", P3, "EPoX", "EP-BX3", 0, NT, intel_piix4_gpo22_raise},
2403{0x10de, 0x02f0, 0x105b, 0x0d01, 0x10de, 0x0264, 0x105b, 0x0d01, NULL, NULL, NULL, P3, "Foxconn", "6150K8MD-8EKRSH", 0, NT, nvidia_mcp_gpio2_raise},
2404{0x8086, 0x2A40, 0x1734, 0x1148, 0x8086, 0x2930, 0x1734, 0x1148, "^XY680", NULL, NULL, P2, "Fujitsu", "Amilo Xi 3650", 0, OK, p2_whitelist_laptop},
2405{0x8086, 0x2443, 0x8086, 0x2442, 0x8086, 0x1130, 0x8086, 0x1130, "^6IEM ", NULL, NULL, P3, "GIGABYTE", "GA-6IEM", 0, NT, intel_ich_gpio25_raise},
2406{0x1106, 0x0686, 0x1106, 0x0686, 0x1106, 0x3058, 0x1458, 0xa000, NULL, NULL, NULL, P3, "GIGABYTE", "GA-7ZM", 512, OK, NULL},
2407{0x8086, 0x2570, 0x1458, 0x2570, 0x8086, 0x24d0, 0, 0, "^8IP775/-G$",NULL, NULL, P3, "GIGABYTE", "GA-8IP775", 0, OK, intel_ich_gpio32_raise},
2408{0x8086, 0x244b, 0x8086, 0x2442, 0x8086, 0x2445, 0x1458, 0xa002, NULL, NULL, NULL, P3, "GIGABYTE", "GA-8IRML", 0, OK, intel_ich_gpio25_raise},
2409{0x8086, 0x24c3, 0x1458, 0x24c2, 0x8086, 0x24cd, 0x1458, 0x5004, NULL, NULL, NULL, P3, "GIGABYTE", "GA-8PE667 Ultra 2", 0, OK, intel_ich_gpio32_raise},
2410{0x1039, 0x0650, 0x1039, 0x0650, 0x1039, 0x7012, 0x1458, 0xA002, "^GA-8SIMLFS20$", NULL, NULL, P3, "GIGABYTE", "GA-8SIMLFS 2.0", 0, OK, sis_gpio0_raise_and_w836xx_memw},
2411{0x1039, 0x0651, 0x1039, 0x0651, 0x1039, 0x7002, 0x1458, 0x5004, "^GA-8SIMLH$",NULL, NULL, P3, "GIGABYTE", "GA-8SIMLH", 0, OK, sis_gpio0_raise_and_w836xx_memw},
2412{0x10DE, 0x02F1, 0x1458, 0x5000, 0x10DE, 0x0261, 0x1458, 0x5001, NULL, NULL, NULL, P3, "GIGABYTE", "GA-K8N51GMF", 0, OK, nvidia_mcp_gpio3b_raise},
2413{0x10DE, 0x026C, 0x1458, 0xA102, 0x10DE, 0x0260, 0x1458, 0x5001, NULL, NULL, NULL, P3, "GIGABYTE", "GA-K8N51GMF-9", 0, OK, nvidia_mcp_gpio3b_raise},
2414{0x10DE, 0x00E4, 0x1458, 0x0C11, 0x10DE, 0x00E0, 0x1458, 0x0C11, NULL, NULL, NULL, P3, "GIGABYTE", "GA-K8NS", 0, OK, nvidia_mcp_gpio0a_raise},
2415{0x10DE, 0x0050, 0x1458, 0x0C11, 0x10DE, 0x005e, 0x1458, 0x5000, NULL, NULL, NULL, P3, "GIGABYTE", "GA-K8N-SLI", 0, OK, nvidia_mcp_gpio21_raise},
2416{0x8086, 0x2415, 0x103c, 0x1250, 0x10b7, 0x9200, 0x103c, 0x1247, NULL, NULL, NULL, P3, "HP", "e-Vectra P2706T", 0, OK, board_hp_p2706t},
2417{0x1166, 0x0223, 0x103c, 0x320d, 0x14e4, 0x1678, 0x103c, 0x703e, NULL, "hp", "dl145_g3", P3, "HP", "ProLiant DL145 G3", 0, OK, board_hp_dl145_g3_enable},
2418{0x1166, 0x0223, 0x103c, 0x320d, 0x14e4, 0x1648, 0x103c, 0x310f, NULL, "hp", "dl165_g6", P3, "HP", "ProLiant DL165 G6", 0, OK, board_hp_dl165_g6_enable},
2419{0x8086, 0x2580, 0x103c, 0x2a08, 0x8086, 0x2640, 0x103c, 0x2a0a, NULL, NULL, NULL, P3, "HP", "Puffer2-UL8E", 0, OK, intel_ich_gpio18_raise},
2420{0x8086, 0x2415, 0x103c, 0x1249, 0x10b7, 0x9200, 0x103c, 0x1246, NULL, NULL, NULL, P3, "HP", "Vectra VL400", 0, OK, board_hp_vl400},
2421{0x8086, 0x1a30, 0x103c, 0x1a30, 0x8086, 0x2443, 0x103c, 0x2440, "^VL420$", NULL, NULL, P3, "HP", "Vectra VL420 SFF", 0, OK, intel_ich_gpio22_raise},
2422{0x10de, 0x0369, 0x103c, 0x12fe, 0x10de, 0x0364, 0x103c, 0x12fe, NULL, "hp", "xw9400", P3, "HP", "xw9400", 0, OK, nvidia_mcp_gpio5_raise},
2423{0x8086, 0x27A0, 0, 0, 0x8086, 0x27B9, 0, 0, NULL, "ibase", "mb899", P3, "IBASE", "MB899", 0, OK, intel_ich_gpio26_raise},
2424{0x1166, 0x0205, 0x1014, 0x0347, 0x1002, 0x515E, 0x1014, 0x0325, NULL, NULL, NULL, P3, "IBM", "x3455", 0, OK, board_ibm_x3455},
2425{0x1039, 0x5513, 0x8086, 0xd61f, 0x1039, 0x6330, 0x8086, 0xd61f, NULL, NULL, NULL, P3, "Intel", "D201GLY", 0, OK, wbsio_check_for_spi},
2426{0x8086, 0x27b8, 0x8086, 0xd606, 0x8086, 0x2770, 0x8086, 0xd606, "^D945GCNL$", NULL, NULL, P2, "Intel", "D945GCNL", 0, OK, p2_not_a_laptop},
2427{0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^SE440BX-2$", NULL, NULL, P3, "Intel", "SE440BX-2", 0, NT, intel_piix4_gpo27_lower},
2428{0x1022, 0x7468, 0, 0, 0x1022, 0x7460, 0, 0, NULL, "iwill", "dk8_htx", P3, "IWILL", "DK8-HTX", 0, OK, w83627hf_gpio24_raise_2e},
2429{0x8086, 0x27A0, 0x8086, 0x27a0, 0x8086, 0x27b8, 0x8086, 0x27b8, NULL, "kontron", "986lcd-m", P3, "Kontron", "986LCD-M", 0, OK, board_kontron_986lcd_m},
2430{0x8086, 0x2917, 0x17AA, 0x20F5, 0x8086, 0x2930, 0x17AA, 0x20F9, "^ThinkPad T400", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad T400", 0, OK, p2_whitelist_laptop},
2431{0x8086, 0x1E22, 0x17AA, 0x21F6, 0x8086, 0x1E55, 0x17AA, 0x21F6, "^ThinkPad T530", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad T530", 0, OK, p2_whitelist_laptop},
2432{0x8086, 0x27a0, 0x17aa, 0x2015, 0x8086, 0x27b9, 0x17aa, 0x2009, "^ThinkPad T60", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad T60", 0, OK, p2_whitelist_laptop},
2433{0x8086, 0x27a0, 0x17aa, 0x2017, 0x8086, 0x27b9, 0x17aa, 0x2009, "^ThinkPad T60", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad T60(s)", 0, OK, p2_whitelist_laptop},
2434{0x8086, 0x2917, 0x17AA, 0x20F5, 0x8086, 0x2930, 0x17AA, 0x20F9, "^ThinkPad X200", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad X200", 0, OK, p2_whitelist_laptop},
2435{0x8086, 0x3B07, 0x17AA, 0x2166, 0x8086, 0x3B30, 0x17AA, 0x2167, "^Lenovo X201", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad X201", 0, OK, p2_whitelist_laptop},
2436{0x8086, 0x1E22, 0x17AA, 0x21FA, 0x8086, 0x1E55, 0x17AA, 0x21FA, "^ThinkPad X230", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad X230", 0, OK, p2_whitelist_laptop},
2437{0x8086, 0x27A0, 0x17AA, 0x2017, 0x8086, 0x27B9, 0x17AA, 0x2009, "^ThinkPad X60", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad X60(s)", 0, OK, p2_whitelist_laptop},
2438{0x8086, 0x2411, 0x8086, 0x2411, 0x8086, 0x7125, 0x0e11, 0xb165, NULL, NULL, NULL, P3, "Mitac", "6513WU", 0, OK, board_mitac_6513wu},
2439{0x8086, 0x8186, 0x8086, 0x8186, 0x8086, 0x8800, 0, 0, "^MSC Vertriebs GmbH$", NULL, NULL, P2, "MSC", "Q7-TCTC", 0, OK, p2_not_a_laptop},
2440{0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^MS-6163 (i440BX)$", NULL, NULL, P3, "MSI", "MS-6163 (MS-6163 Pro)", 0, OK, intel_piix4_gpo14_raise},
2441{0x8086, 0x244b, 0x1462, 0x3910, 0x8086, 0x2442, 0x1462, 0x3910, NULL, NULL, NULL, P3, "MSI", "MS-6391 (845 Pro4)", 0, OK, intel_ich_gpio23_raise},
2442{0x1039, 0x0745, 0, 0, 0x1039, 0x0018, 0, 0, "^MS-6561", NULL, NULL, P3, "MSI", "MS-6561 (745 Ultra)", 0, OK, w836xx_memw_enable_2e},
2443{0x8086, 0x2560, 0x1462, 0x5770, 0x8086, 0x24C3, 0x1462, 0x5770, NULL, NULL, NULL, P3, "MSI", "MS-6577 (Xenon)", 0, OK, w83627hf_gpio25_raise_2e},
2444{0x13f6, 0x0111, 0x1462, 0x5900, 0x1106, 0x3177, 0x1106, 0, NULL, NULL, NULL, P3, "MSI", "MS-6590 (KT4 Ultra)", 0, OK, board_msi_kt4v},
2445{0x1106, 0x0282, 0x1106, 0x0282, 0x1106, 0x3227, 0x1106, 0x3227, "^MS-7094$", NULL, NULL, P3, "MSI", "MS-7094 (K8T Neo2-F V2.0)", 0, OK, w83627thf_gpio44_raise_2e},
2446{0x1106, 0x0571, 0x1462, 0x7120, 0x1106, 0x3065, 0x1462, 0x7120, NULL, NULL, NULL, P3, "MSI", "MS-6712 (KT4V)", 0, OK, board_msi_kt4v},
2447{0x1106, 0x3148, 0 , 0 , 0x1106, 0x3177, 0 , 0 , NULL, "msi", "ms6787", P3, "MSI", "MS-6787 (P4MAM-V/P4MAM-L)", 0, OK, w836xx_memw_enable_2e},
2448{0x8086, 0x24d3, 0x1462, 0x7880, 0x8086, 0x2570, 0, 0, NULL, NULL, NULL, P3, "MSI", "MS-6788-040 (848P NeoV)", 0, OK, intel_ich_gpio32_raise},
2449{0x1039, 0x7012, 0x1462, 0x0050, 0x1039, 0x6325, 0x1462, 0x0058, NULL, NULL, NULL, P3, "MSI", "MS-7005 (651M-L)", 0, OK, sis_gpio0_raise_and_w836xx_memw},
2450{0x10DE, 0x00E0, 0x1462, 0x0250, 0x10DE, 0x00E1, 0x1462, 0x0250, NULL, NULL, NULL, P3, "MSI", "MS-7025 (K8N Neo2 Platinum)", 0, OK, nvidia_mcp_gpio0c_raise},
2451{0x10DE, 0x00E0, 0x1462, 0x0300, 0x10DE, 0x00E1, 0x1462, 0x0300, NULL, NULL, NULL, P3, "MSI", "MS-7030 (K8N Neo Platinum)", 0, OK, nvidia_mcp_gpio0c_raise},
2452{0x8086, 0x2658, 0x1462, 0x7046, 0x1106, 0x3044, 0x1462, 0x046d, NULL, NULL, NULL, P3, "MSI", "MS-7046", 0, OK, intel_ich_gpio19_raise},
2453{0x1106, 0x3149, 0x1462, 0x7061, 0x1106, 0x3227, 0, 0, NULL, NULL, NULL, P3, "MSI", "MS-7061 (KM4M-V/KM4AM-V)", 0, OK, w836xx_memw_enable_2e},
2454{0x10DE, 0x005E, 0x1462, 0x7125, 0x10DE, 0x0052, 0x1462, 0x7125, NULL, NULL, NULL, P3, "MSI", "MS-7125 (K8N Neo4(-F/-FI/-FX/Platinum))", 0, OK, nvidia_mcp_gpio2_raise},
2455{0x10DE, 0x005E, 0x1462, 0x7135, 0x10DE, 0x0050, 0x1462, 0x7135, NULL, "msi", "k8n-neo3", P3, "MSI", "MS-7135 (K8N Neo3)", 0, OK, w83627thf_gpio44_raise_4e},
2456{0x10DE, 0x0270, 0x1462, 0x7207, 0x10DE, 0x0264, 0x1462, 0x7207, NULL, NULL, NULL, P3, "MSI", "MS-7207 (K8NGM2-L)", 0, NT, nvidia_mcp_gpio2_raise},
2457{0x10DE, 0x0360, 0x1462, 0x7250, 0x10DE, 0x0368, 0x1462, 0x7250, NULL, NULL, NULL, P3, "MSI", "MS-7250 (K9N SLI)", 0, OK, nvidia_mcp_gpio2_raise},
2458{0x1011, 0x0019, 0xaa55, 0xaa55, 0x8086, 0x7190, 0, 0, NULL, NULL, NULL, P3, "Nokia", "IP530", 0, OK, fdc37b787_gpio50_raise_3f0},
2459{0x8086, 0x3B30, 0x1025, 0x0379, 0x8086, 0x3B09, 0x1025, 0x0379, "^EasyNote LM85$", NULL, NULL, P2, "Packard Bell","EasyNote LM85", 0, OK, p2_whitelist_laptop},
2460{0x8086, 0x24d3, 0x144d, 0xb025, 0x8086, 0x1050, 0x144d, 0xb025, NULL, NULL, NULL, P3, "Samsung", "Polaris 32", 0, OK, intel_ich_gpio21_raise},
2461{0x1106, 0x3099, 0, 0, 0x1106, 0x3074, 0, 0, NULL, "shuttle", "ak31", P3, "Shuttle", "AK31", 0, OK, w836xx_memw_enable_2e},
2462{0x1106, 0x3104, 0x1297, 0xa238, 0x1106, 0x3059, 0x1297, 0xc063, NULL, NULL, NULL, P3, "Shuttle", "AK38N", 256, OK, NULL},
2463{0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x3058, 0x15DD, 0x7609, NULL, NULL, NULL, P3, "Soyo", "SY-7VCA", 0, OK, via_apollo_gpo0_lower},
2464{0x10de, 0x0364, 0x108e, 0x6676, 0x10de, 0x0369, 0x108e, 0x6676, "^Sun Ultra 40 M2", NULL, NULL, P3, "Sun", "Ultra 40 M2", 0, OK, board_sun_ultra_40_m2},
2465{0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x0596, 0x1106, 0, NULL, NULL, NULL, P3, "Tekram", "P6Pro-A5", 256, OK, NULL},
2466{0x1106, 0x3123, 0x1106, 0x3123, 0x1106, 0x3059, 0x1106, 0x4161, NULL, NULL, NULL, P3, "Termtek", "TK-3370 (Rev:2.5B)", 0, OK, w836xx_memw_enable_4e},
2467{0x8086, 0x7120, 0x109f, 0x3157, 0x8086, 0x2410, 0, 0, NULL, NULL, NULL, P3, "TriGem", "Anaheim-3", 0, OK, intel_ich_gpio22_raise},
2468{0x8086, 0x1076, 0x8086, 0x1176, 0x1106, 0x3059, 0x10f1, 0x2498, NULL, NULL, NULL, P3, "Tyan", "S2498 (Tomcat K7M)", 0, OK, w836xx_memw_enable_2e},
2469{0x1106, 0x0259, 0x1106, 0xAA07, 0x1106, 0x3227, 0x1106, 0xAA07, NULL, NULL, NULL, P3, "VIA", "EPIA EK", 0, NT, via_vt823x_gpio9_raise},
2470{0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01, NULL, NULL, NULL, P3, "VIA", "EPIA M/MII/...", 0, OK, via_vt823x_gpio15_raise},
2471{0x1106, 0x0259, 0x1106, 0x3227, 0x1106, 0x3065, 0x1106, 0x3149, NULL, NULL, NULL, P3, "VIA", "EPIA-N/NL", 0, OK, via_vt823x_gpio9_raise},
2472#endif
2473{ 0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL, NULL, P3, NULL, NULL, 0, NT, NULL}, /* end marker */
2474};
2475
2476int selfcheck_board_enables(void)
2477{
2478if (board_matches[ARRAY_SIZE(board_matches) - 1].vendor_name != NULL) {
2479msg_gerr("Board enables table miscompilation!\n");
2480return 1;
2481}
2482
2483int ret = 0;
2484unsigned int i;
2485for (i = 0; i < ARRAY_SIZE(board_matches) - 1; i++) {
2486const struct board_match *b = &board_matches[i];
2487if (b->vendor_name == NULL || b->board_name == NULL) {
2488msg_gerr("ERROR: Board enable #%d does not define a vendor and board name.\n"
2489 "Please report a bug at flashrom@flashrom.org\n", i);
2490ret = 1;
2491continue;
2492}
2493if ((b->first_vendor == 0 || b->first_device == 0 ||
2494 b->second_vendor == 0 || b->second_device == 0) ||
2495 ((b->lb_vendor == NULL) ^ (b->lb_part == NULL)) ||
2496 (b->max_rom_decode_parallel == 0 && b->enable == NULL)) {
2497msg_gerr("ERROR: Board enable for %s %s is misdefined.\n"
2498 "Please report a bug at flashrom@flashrom.org\n",
2499 b->vendor_name, b->board_name);
2500ret = 1;
2501}
2502}
2503return ret;
2504}
2505
2506/* Parse the <vendor>:<board> string specified by the user as part of -p internal:mainboard=<vendor>:<board>.
2507 * Parameters vendor and model will be overwritten. Returns 0 on success.
2508 * Note: strtok modifies the original string, so we work on a copy and allocate memory for the results.
2509 */
2510int board_parse_parameter(const char *boardstring, const char **vendor, const char **model)
2511{
2512/* strtok may modify the original string. */
2513char *tempstr = strdup(boardstring);
2514char *tempstr2 = NULL;
2515strtok(tempstr, ":");
2516tempstr2 = strtok(NULL, ":");
2517if (tempstr == NULL || tempstr2 == NULL) {
2518free(tempstr);
2519msg_pinfo("Please supply the board vendor and model name with the "
2520 "-p internal:mainboard=<vendor>:<model> option.\n");
2521return 1;
2522}
2523*vendor = strdup(tempstr);
2524*model = strdup(tempstr2);
2525msg_pspew("-p internal:mainboard: vendor=\"%s\", model=\"%s\"\n", tempstr, tempstr2);
2526free(tempstr);
2527return 0;
2528}
2529
2530/*
2531 * Match boards on vendor and model name.
2532 * The string parameters can come either from the coreboot table or the command line (i.e. the user).
2533 * The boolean needs to be set accordingly to compare them to the right entries of the board enables table.
2534 * Require main PCI IDs to match too as extra safety.
2535 * Parameters vendor and model must be non-NULL!
2536 */
2537static const struct board_match *board_match_name(const char *vendor, const char *model, bool cb)
2538{
2539const struct board_match *board = board_matches;
2540const struct board_match *partmatch = NULL;
2541
2542for (; board->vendor_name; board++) {
2543const char *cur_vendor = cb ? board->lb_vendor : board->vendor_name;
2544const char *cur_model = cb ? board->lb_part : board->board_name;
2545
2546if (!cur_vendor || strcasecmp(cur_vendor, vendor))
2547continue;
2548
2549if (!cur_model || strcasecmp(cur_model, model))
2550continue;
2551
2552if (!pci_dev_find(board->first_vendor, board->first_device)) {
2553msg_pdbg("Odd. Board name \"%s\":\"%s\" matches, but first PCI device %04x:%04x "
2554 "doesn't.\n", vendor, model, board->first_vendor, board->first_device);
2555continue;
2556}
2557
2558if (!pci_dev_find(board->second_vendor, board->second_device)) {
2559msg_pdbg("Odd. Board name \"%s\":\"%s\" matches, but second PCI device %04x:%04x "
2560 "doesn't.\n", vendor, model, board->second_vendor, board->second_device);
2561continue;
2562}
2563
2564if (partmatch) {
2565/* More than one entry has a matching name. */
2566msg_perr("Board name \"%s\":\"%s\" and PCI IDs matched more than one board enable "
2567 "entry. Please report a bug at flashrom@flashrom.org\n", vendor, model);
2568return NULL;
2569}
2570partmatch = board;
2571}
2572
2573if (partmatch)
2574return partmatch;
2575
2576return NULL;
2577}
2578
2579/*
2580 * Match boards on PCI IDs and subsystem IDs.
2581 * Second set of IDs can be either main+subsystem IDs, main IDs or no IDs.
2582 */
2583const static struct board_match *board_match_pci_ids(enum board_match_phase phase)
2584{
2585const struct board_match *board = board_matches;
2586
2587for (; board->vendor_name; board++) {
2588if ((!board->first_card_vendor || !board->first_card_device) &&
2589 !board->dmi_pattern)
2590continue;
2591if (board->phase != phase)
2592continue;
2593
2594if (!pci_card_find(board->first_vendor, board->first_device,
2595 board->first_card_vendor,
2596 board->first_card_device))
2597continue;
2598
2599if (board->second_vendor) {
2600if (board->second_card_vendor) {
2601if (!pci_card_find(board->second_vendor,
2602 board->second_device,
2603 board->second_card_vendor,
2604 board->second_card_device))
2605continue;
2606} else {
2607if (!pci_dev_find(board->second_vendor,
2608 board->second_device))
2609continue;
2610}
2611}
2612
2613#if defined(__i386__) || defined(__x86_64__)
2614if (board->dmi_pattern) {
2615if (!has_dmi_support) {
2616msg_pwarn("Warning: Can't autodetect %s %s, DMI info unavailable.\n",
2617 board->vendor_name, board->board_name);
2618msg_pinfo("Please supply the board vendor and model name with the "
2619 "-p internal:mainboard=<vendor>:<model> option.\n");
2620continue;
2621} else {
2622if (!dmi_match(board->dmi_pattern))
2623continue;
2624}
2625}
2626#endif // defined(__i386__) || defined(__x86_64__)
2627return board;
2628}
2629
2630return NULL;
2631}
2632
2633static int board_enable_safetycheck(const struct board_match *board)
2634{
2635if (!board)
2636return 1;
2637
2638if (board->status == OK)
2639return 0;
2640
2641if (!force_boardenable) {
2642msg_pwarn("Warning: The mainboard-specific code for %s %s has not been tested,\n"
2643 "and thus will not be executed by default. Depending on your hardware,\n"
2644 "erasing, writing or even probing can fail without running this code.\n\n"
2645 "Please see the man page (section PROGRAMMER SPECIFIC INFO, subsection\n"
2646 "\"internal programmer\") for details.\n", board->vendor_name, board->board_name);
2647return 1;
2648}
2649msg_pwarn("NOTE: Running an untested board enable procedure.\n"
2650 "Please report success/failure to flashrom@flashrom.org.\n");
2651return 0;
2652}
2653
2654/* FIXME: Should this be identical to board_flash_enable? */
2655static int board_handle_phase(enum board_match_phase phase)
2656{
2657const struct board_match *board = NULL;
2658
2659board = board_match_pci_ids(phase);
2660
2661if (!board)
2662return 0;
2663
2664if (board_enable_safetycheck(board))
2665return 0;
2666
2667if (!board->enable) {
2668/* Not sure if there is a valid case for this. */
2669msg_perr("Board match found, but nothing to do?\n");
2670return 0;
2671}
2672
2673return board->enable();
2674}
2675
2676void board_handle_before_superio(void)
2677{
2678board_handle_phase(P1);
2679}
2680
2681void board_handle_before_laptop(void)
2682{
2683board_handle_phase(P2);
2684}
2685
2686int board_flash_enable(const char *vendor, const char *model, const char *cb_vendor, const char *cb_model)
2687{
2688const struct board_match *board = NULL;
2689int ret = 0;
2690
2691if (vendor != NULL && model != NULL) {
2692board = board_match_name(vendor, model, false);
2693if (!board) { /* If a board was given by the user it has to match, else we abort here. */
2694msg_perr("No suitable board enable found for vendor=\"%s\", model=\"%s\".\n",
2695 vendor, model);
2696return 1;
2697}
2698}
2699if (board == NULL && cb_vendor != NULL && cb_model != NULL) {
2700board = board_match_name(cb_vendor, cb_model, true);
2701if (!board) { /* Failure is an option here, because many cb boards don't require an enable. */
2702msg_pdbg2("No board enable found matching coreboot IDs vendor=\"%s\", model=\"%s\".\n",
2703 cb_vendor, cb_model);
2704}
2705}
2706if (board == NULL) {
2707board = board_match_pci_ids(P3);
2708if (!board) /* i.e. there is just no board enable available for this board */
2709return 0;
2710}
2711
2712if (board_enable_safetycheck(board))
2713return 1;
2714
2715/* limit the maximum size of the parallel bus */
2716if (board->max_rom_decode_parallel)
2717max_rom_decode.parallel = board->max_rom_decode_parallel * 1024;
2718
2719if (board->enable != NULL) {
2720msg_pinfo("Enabling full flash access for board \"%s %s\"... ",
2721 board->vendor_name, board->board_name);
2722
2723ret = board->enable();
2724if (ret)
2725msg_pinfo("FAILED!\n");
2726else
2727msg_pinfo("OK.\n");
2728}
2729
2730return ret;
2731}

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