| 1 | /*␊ |
| 2 | * This file is part of the flashrom project.␊ |
| 3 | *␊ |
| 4 | * Copyright (C) 2008 coresystems GmbH␊ |
| 5 | * Copyright (C) 2010 Carl-Daniel Hailfinger␊ |
| 6 | *␊ |
| 7 | * This program is free software; you can redistribute it and/or modify␊ |
| 8 | * it under the terms of the GNU General Public License as published by␊ |
| 9 | * the Free Software Foundation; either version 2 of the License, or␊ |
| 10 | * (at your option) any later version.␊ |
| 11 | *␊ |
| 12 | * This program is distributed in the hope that it will be useful,␊ |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of␊ |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the␊ |
| 15 | * GNU General Public License for more details.␊ |
| 16 | *␊ |
| 17 | * You should have received a copy of the GNU General Public License␊ |
| 18 | * along with this program; if not, write to the Free Software␊ |
| 19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA␊ |
| 20 | */␊ |
| 21 | ␊ |
| 22 | #include "flash.h"␊ |
| 23 | ␊ |
| 24 | static int printlock_w39_fwh_block(struct flashctx *flash, unsigned int offset)␊ |
| 25 | {␊ |
| 26 | ␉chipaddr wrprotect = flash->virtual_registers + offset + 2;␊ |
| 27 | ␉uint8_t locking;␊ |
| 28 | ␊ |
| 29 | ␉locking = chip_readb(flash, wrprotect);␊ |
| 30 | ␉msg_cdbg("Lock status of block at 0x%08x is ", offset);␊ |
| 31 | ␉switch (locking & 0x7) {␊ |
| 32 | ␉case 0:␊ |
| 33 | ␉␉msg_cdbg("Full Access.\n");␊ |
| 34 | ␉␉break;␊ |
| 35 | ␉case 1:␊ |
| 36 | ␉␉msg_cdbg("Write Lock (Default State).\n");␊ |
| 37 | ␉␉break;␊ |
| 38 | ␉case 2:␊ |
| 39 | ␉␉msg_cdbg("Locked Open (Full Access, Lock Down).\n");␊ |
| 40 | ␉␉break;␊ |
| 41 | ␉case 3:␊ |
| 42 | ␉␉msg_cerr("Error: Write Lock, Locked Down.\n");␊ |
| 43 | ␉␉break;␊ |
| 44 | ␉case 4:␊ |
| 45 | ␉␉msg_cdbg("Read Lock.\n");␊ |
| 46 | ␉␉break;␊ |
| 47 | ␉case 5:␊ |
| 48 | ␉␉msg_cdbg("Read/Write Lock.\n");␊ |
| 49 | ␉␉break;␊ |
| 50 | ␉case 6:␊ |
| 51 | ␉␉msg_cerr("Error: Read Lock, Locked Down.\n");␊ |
| 52 | ␉␉break;␊ |
| 53 | ␉case 7:␊ |
| 54 | ␉␉msg_cerr("Error: Read/Write Lock, Locked Down.\n");␊ |
| 55 | ␉␉break;␊ |
| 56 | ␉}␊ |
| 57 | ␊ |
| 58 | ␉/* Read or write lock present? */␊ |
| 59 | ␉return (locking & ((1 << 2) | (1 << 0))) ? -1 : 0;␊ |
| 60 | }␊ |
| 61 | ␊ |
| 62 | static int unlock_w39_fwh_block(struct flashctx *flash, unsigned int offset)␊ |
| 63 | {␊ |
| 64 | ␉chipaddr wrprotect = flash->virtual_registers + offset + 2;␊ |
| 65 | ␉uint8_t locking;␊ |
| 66 | ␊ |
| 67 | ␉locking = chip_readb(flash, wrprotect);␊ |
| 68 | ␉/* Read or write lock present? */␊ |
| 69 | ␉if (locking & ((1 << 2) | (1 << 0))) {␊ |
| 70 | ␉␉/* Lockdown active? */␊ |
| 71 | ␉␉if (locking & (1 << 1)) {␊ |
| 72 | ␉␉␉msg_cerr("Can't unlock block at 0x%08x!\n", offset);␊ |
| 73 | ␉␉␉return -1;␊ |
| 74 | ␉␉} else {␊ |
| 75 | ␉␉␉msg_cdbg("Unlocking block at 0x%08x\n", offset);␊ |
| 76 | ␉␉␉chip_writeb(flash, 0, wrprotect);␊ |
| 77 | ␉␉}␊ |
| 78 | ␉}␊ |
| 79 | ␊ |
| 80 | ␉return 0;␊ |
| 81 | }␊ |
| 82 | ␊ |
| 83 | static uint8_t w39_idmode_readb(struct flashctx *flash, unsigned int offset)␊ |
| 84 | {␊ |
| 85 | ␉chipaddr bios = flash->virtual_memory;␊ |
| 86 | ␉uint8_t val;␊ |
| 87 | ␊ |
| 88 | ␉/* Product Identification Entry */␊ |
| 89 | ␉chip_writeb(flash, 0xAA, bios + 0x5555);␊ |
| 90 | ␉chip_writeb(flash, 0x55, bios + 0x2AAA);␊ |
| 91 | ␉chip_writeb(flash, 0x90, bios + 0x5555);␊ |
| 92 | ␉programmer_delay(10);␊ |
| 93 | ␊ |
| 94 | ␉/* Read something, maybe hardware lock bits */␊ |
| 95 | ␉val = chip_readb(flash, bios + offset);␊ |
| 96 | ␊ |
| 97 | ␉/* Product Identification Exit */␊ |
| 98 | ␉chip_writeb(flash, 0xAA, bios + 0x5555);␊ |
| 99 | ␉chip_writeb(flash, 0x55, bios + 0x2AAA);␊ |
| 100 | ␉chip_writeb(flash, 0xF0, bios + 0x5555);␊ |
| 101 | ␉programmer_delay(10);␊ |
| 102 | ␊ |
| 103 | ␉return val;␊ |
| 104 | }␊ |
| 105 | ␊ |
| 106 | static int printlock_w39_tblwp(uint8_t lock)␊ |
| 107 | {␊ |
| 108 | ␉msg_cdbg("Hardware bootblock locking (#TBL) is %sactive.\n",␊ |
| 109 | ␉␉ (lock & (1 << 2)) ? "" : "not ");␊ |
| 110 | ␉msg_cdbg("Hardware remaining chip locking (#WP) is %sactive..\n",␊ |
| 111 | ␉␉(lock & (1 << 3)) ? "" : "not ");␊ |
| 112 | ␉if (lock & ((1 << 2) | (1 << 3)))␊ |
| 113 | ␉␉return -1;␊ |
| 114 | ␊ |
| 115 | ␉return 0;␊ |
| 116 | }␊ |
| 117 | ␊ |
| 118 | static int printlock_w39_bootblock_64k16k(uint8_t lock)␊ |
| 119 | {␊ |
| 120 | ␉msg_cdbg("Software 64 kB bootblock locking is %sactive.\n",␊ |
| 121 | ␉␉ (lock & (1 << 0)) ? "" : "not ");␊ |
| 122 | ␉msg_cdbg("Software 16 kB bootblock locking is %sactive.\n",␊ |
| 123 | ␉␉ (lock & (1 << 1)) ? "" : "not ");␊ |
| 124 | ␉if (lock & ((1 << 1) | (1 << 0)))␊ |
| 125 | ␉␉return -1;␊ |
| 126 | ␊ |
| 127 | ␉return 0;␊ |
| 128 | }␊ |
| 129 | ␊ |
| 130 | static int printlock_w39_common(struct flashctx *flash, unsigned int offset)␊ |
| 131 | {␊ |
| 132 | ␉uint8_t lock;␊ |
| 133 | ␊ |
| 134 | ␉lock = w39_idmode_readb(flash, offset);␊ |
| 135 | ␉msg_cdbg("Lockout bits:\n");␊ |
| 136 | ␉return printlock_w39_tblwp(lock);␊ |
| 137 | }␊ |
| 138 | ␊ |
| 139 | static int printlock_w39_fwh(struct flashctx *flash)␊ |
| 140 | {␊ |
| 141 | ␉unsigned int i, total_size = flash->total_size * 1024;␊ |
| 142 | ␉int ret = 0;␊ |
| 143 | ␉␊ |
| 144 | ␉/* Print lock status of the complete chip */␊ |
| 145 | ␉for (i = 0; i < total_size; i += flash->page_size)␊ |
| 146 | ␉␉ret |= printlock_w39_fwh_block(flash, i);␊ |
| 147 | ␊ |
| 148 | ␉return ret;␊ |
| 149 | }␊ |
| 150 | ␊ |
| 151 | static int unlock_w39_fwh(struct flashctx *flash)␊ |
| 152 | {␊ |
| 153 | ␉unsigned int i, total_size = flash->total_size * 1024;␊ |
| 154 | ␉␊ |
| 155 | ␉/* Unlock the complete chip */␊ |
| 156 | ␉for (i = 0; i < total_size; i += flash->page_size)␊ |
| 157 | ␉␉if (unlock_w39_fwh_block(flash, i))␊ |
| 158 | ␉␉␉return -1;␊ |
| 159 | ␊ |
| 160 | ␉return 0;␊ |
| 161 | }␊ |
| 162 | ␊ |
| 163 | int printlock_w39l040(struct flashctx *flash)␊ |
| 164 | {␊ |
| 165 | ␉uint8_t lock;␊ |
| 166 | ␉int ret;␊ |
| 167 | ␊ |
| 168 | ␉lock = w39_idmode_readb(flash, 0x00002);␊ |
| 169 | ␉msg_cdbg("Bottom boot block:\n");␊ |
| 170 | ␉ret = printlock_w39_bootblock_64k16k(lock);␊ |
| 171 | ␊ |
| 172 | ␉lock = w39_idmode_readb(flash, 0x7fff2);␊ |
| 173 | ␉msg_cdbg("Top boot block:\n");␊ |
| 174 | ␉ret |= printlock_w39_bootblock_64k16k(lock);␊ |
| 175 | ␊ |
| 176 | ␉return ret;␊ |
| 177 | }␊ |
| 178 | ␊ |
| 179 | int printlock_w39v040a(struct flashctx *flash)␊ |
| 180 | {␊ |
| 181 | ␉uint8_t lock;␊ |
| 182 | ␉int ret = 0;␊ |
| 183 | ␊ |
| 184 | ␉/* The W39V040A datasheet contradicts itself on the lock register␊ |
| 185 | ␉ * location: 0x00002 and 0x7fff2 are both mentioned. Pick the one␊ |
| 186 | ␉ * which is similar to the other chips of the same family.␊ |
| 187 | ␉ */␊ |
| 188 | ␉lock = w39_idmode_readb(flash, 0x7fff2);␊ |
| 189 | ␉msg_cdbg("Lockout bits:\n");␊ |
| 190 | ␊ |
| 191 | ␉ret = printlock_w39_tblwp(lock);␊ |
| 192 | ␉ret |= printlock_w39_bootblock_64k16k(lock);␊ |
| 193 | ␊ |
| 194 | ␉return ret;␊ |
| 195 | }␊ |
| 196 | ␊ |
| 197 | int printlock_w39v040b(struct flashctx *flash)␊ |
| 198 | {␊ |
| 199 | ␉return printlock_w39_common(flash, 0x7fff2);␊ |
| 200 | }␊ |
| 201 | ␊ |
| 202 | int printlock_w39v040c(struct flashctx *flash)␊ |
| 203 | {␊ |
| 204 | ␉/* Typo in the datasheet? The other chips use 0x7fff2. */␊ |
| 205 | ␉return printlock_w39_common(flash, 0xfff2);␊ |
| 206 | }␊ |
| 207 | ␊ |
| 208 | int printlock_w39v040fa(struct flashctx *flash)␊ |
| 209 | {␊ |
| 210 | ␉int ret = 0;␊ |
| 211 | ␊ |
| 212 | ␉ret = printlock_w39v040a(flash);␊ |
| 213 | ␉ret |= printlock_w39_fwh(flash);␊ |
| 214 | ␊ |
| 215 | ␉return ret;␊ |
| 216 | }␊ |
| 217 | ␊ |
| 218 | int printlock_w39v040fb(struct flashctx *flash)␊ |
| 219 | {␊ |
| 220 | ␉int ret = 0;␊ |
| 221 | ␊ |
| 222 | ␉ret = printlock_w39v040b(flash);␊ |
| 223 | ␉ret |= printlock_w39_fwh(flash);␊ |
| 224 | ␊ |
| 225 | ␉return ret;␊ |
| 226 | }␊ |
| 227 | ␊ |
| 228 | int printlock_w39v040fc(struct flashctx *flash)␊ |
| 229 | {␊ |
| 230 | ␉int ret = 0;␊ |
| 231 | ␊ |
| 232 | ␉/* W39V040C and W39V040FC use different WP/TBL offsets. */␊ |
| 233 | ␉ret = printlock_w39_common(flash, 0x7fff2);␊ |
| 234 | ␉ret |= printlock_w39_fwh(flash);␊ |
| 235 | ␊ |
| 236 | ␉return ret;␊ |
| 237 | }␊ |
| 238 | ␊ |
| 239 | int printlock_w39v080a(struct flashctx *flash)␊ |
| 240 | {␊ |
| 241 | ␉return printlock_w39_common(flash, 0xffff2);␊ |
| 242 | }␊ |
| 243 | ␊ |
| 244 | int printlock_w39v080fa(struct flashctx *flash)␊ |
| 245 | {␊ |
| 246 | ␉int ret = 0;␊ |
| 247 | ␊ |
| 248 | ␉ret = printlock_w39v080a(flash);␊ |
| 249 | ␉ret |= printlock_w39_fwh(flash);␊ |
| 250 | ␊ |
| 251 | ␉return ret;␊ |
| 252 | }␊ |
| 253 | ␊ |
| 254 | int printlock_w39v080fa_dual(struct flashctx *flash)␊ |
| 255 | {␊ |
| 256 | ␉msg_cinfo("Block locking for W39V080FA in dual mode is "␊ |
| 257 | ␉␉ "undocumented.\n");␊ |
| 258 | ␉/* Better safe than sorry. */␊ |
| 259 | ␉return -1;␊ |
| 260 | }␊ |
| 261 | ␊ |
| 262 | int unlock_w39v040fb(struct flashctx *flash)␊ |
| 263 | {␊ |
| 264 | ␉if (unlock_w39_fwh(flash))␊ |
| 265 | ␉␉return -1;␊ |
| 266 | ␉if (printlock_w39_common(flash, 0x7fff2))␊ |
| 267 | ␉␉return -1;␊ |
| 268 | ␊ |
| 269 | ␉return 0;␊ |
| 270 | }␊ |
| 271 | ␊ |
| 272 | int unlock_w39v080fa(struct flashctx *flash)␊ |
| 273 | {␊ |
| 274 | ␉if (unlock_w39_fwh(flash))␊ |
| 275 | ␉␉return -1;␊ |
| 276 | ␉if (printlock_w39_common(flash, 0xffff2))␊ |
| 277 | ␉␉return -1;␊ |
| 278 | ␊ |
| 279 | ␉return 0;␊ |
| 280 | }␊ |
| 281 | ␊ |
| 282 | int printlock_at49f(struct flashctx *flash)␊ |
| 283 | {␊ |
| 284 | ␉uint8_t lock = w39_idmode_readb(flash, 0x00002);␊ |
| 285 | ␉msg_cdbg("Hardware bootblock lockout is %sactive.\n",␊ |
| 286 | ␉␉ (lock & 0x01) ? "" : "not ");␊ |
| 287 | ␉return 0;␊ |
| 288 | }␊ |
| 289 | |
