| 1 | /*␊ |
| 2 | * This file is part of the flashrom project.␊ |
| 3 | *␊ |
| 4 | * Copyright (C) 2007, 2008, 2009, 2010 Carl-Daniel Hailfinger␊ |
| 5 | * Copyright (C) 2008 coresystems GmbH␊ |
| 6 | *␊ |
| 7 | * This program is free software; you can redistribute it and/or modify␊ |
| 8 | * it under the terms of the GNU General Public License as published by␊ |
| 9 | * the Free Software Foundation; version 2 of the License.␊ |
| 10 | *␊ |
| 11 | * This program is distributed in the hope that it will be useful,␊ |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of␊ |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the␊ |
| 14 | * GNU General Public License for more details.␊ |
| 15 | *␊ |
| 16 | * You should have received a copy of the GNU General Public License␊ |
| 17 | * along with this program; if not, write to the Free Software␊ |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA␊ |
| 19 | */␊ |
| 20 | ␊ |
| 21 | /*␊ |
| 22 | * Contains the common SPI chip driver functions␊ |
| 23 | */␊ |
| 24 | ␊ |
| 25 | #include <string.h>␊ |
| 26 | #include "flash.h"␊ |
| 27 | #include "flashchips.h"␊ |
| 28 | #include "chipdrivers.h"␊ |
| 29 | #include "programmer.h"␊ |
| 30 | #include "spi.h"␊ |
| 31 | ␊ |
| 32 | static int spi_rdid(struct flashctx *flash, unsigned char *readarr, int bytes)␊ |
| 33 | {␊ |
| 34 | ␉static const unsigned char cmd[JEDEC_RDID_OUTSIZE] = { JEDEC_RDID };␊ |
| 35 | ␉int ret;␊ |
| 36 | ␉int i;␊ |
| 37 | ␊ |
| 38 | ␉ret = spi_send_command(flash, sizeof(cmd), bytes, cmd, readarr);␊ |
| 39 | ␉if (ret)␊ |
| 40 | ␉␉return ret;␊ |
| 41 | ␉msg_cspew("RDID returned");␊ |
| 42 | ␉for (i = 0; i < bytes; i++)␊ |
| 43 | ␉␉msg_cspew(" 0x%02x", readarr[i]);␊ |
| 44 | ␉msg_cspew(". ");␊ |
| 45 | ␉return 0;␊ |
| 46 | }␊ |
| 47 | ␊ |
| 48 | static int spi_rems(struct flashctx *flash, unsigned char *readarr)␊ |
| 49 | {␊ |
| 50 | ␉unsigned char cmd[JEDEC_REMS_OUTSIZE] = { JEDEC_REMS, 0, 0, 0 };␊ |
| 51 | ␉uint32_t readaddr;␊ |
| 52 | ␉int ret;␊ |
| 53 | ␊ |
| 54 | ␉ret = spi_send_command(flash, sizeof(cmd), JEDEC_REMS_INSIZE, cmd,␊ |
| 55 | ␉␉␉ readarr);␊ |
| 56 | ␉if (ret == SPI_INVALID_ADDRESS) {␊ |
| 57 | ␉␉/* Find the lowest even address allowed for reads. */␊ |
| 58 | ␉␉readaddr = (spi_get_valid_read_addr(flash) + 1) & ~1;␊ |
| 59 | ␉␉cmd[1] = (readaddr >> 16) & 0xff,␊ |
| 60 | ␉␉cmd[2] = (readaddr >> 8) & 0xff,␊ |
| 61 | ␉␉cmd[3] = (readaddr >> 0) & 0xff,␊ |
| 62 | ␉␉ret = spi_send_command(flash, sizeof(cmd), JEDEC_REMS_INSIZE,␊ |
| 63 | ␉␉␉␉ cmd, readarr);␊ |
| 64 | ␉}␊ |
| 65 | ␉if (ret)␊ |
| 66 | ␉␉return ret;␊ |
| 67 | ␉msg_cspew("REMS returned 0x%02x 0x%02x. ", readarr[0], readarr[1]);␊ |
| 68 | ␉return 0;␊ |
| 69 | }␊ |
| 70 | ␊ |
| 71 | static int spi_res(struct flashctx *flash, unsigned char *readarr, int bytes)␊ |
| 72 | {␊ |
| 73 | ␉unsigned char cmd[JEDEC_RES_OUTSIZE] = { JEDEC_RES, 0, 0, 0 };␊ |
| 74 | ␉uint32_t readaddr;␊ |
| 75 | ␉int ret;␊ |
| 76 | ␉int i;␊ |
| 77 | ␊ |
| 78 | ␉ret = spi_send_command(flash, sizeof(cmd), bytes, cmd, readarr);␊ |
| 79 | ␉if (ret == SPI_INVALID_ADDRESS) {␊ |
| 80 | ␉␉/* Find the lowest even address allowed for reads. */␊ |
| 81 | ␉␉readaddr = (spi_get_valid_read_addr(flash) + 1) & ~1;␊ |
| 82 | ␉␉cmd[1] = (readaddr >> 16) & 0xff,␊ |
| 83 | ␉␉cmd[2] = (readaddr >> 8) & 0xff,␊ |
| 84 | ␉␉cmd[3] = (readaddr >> 0) & 0xff,␊ |
| 85 | ␉␉ret = spi_send_command(flash, sizeof(cmd), bytes, cmd, readarr);␊ |
| 86 | ␉}␊ |
| 87 | ␉if (ret)␊ |
| 88 | ␉␉return ret;␊ |
| 89 | ␉msg_cspew("RES returned");␊ |
| 90 | ␉for (i = 0; i < bytes; i++)␊ |
| 91 | ␉␉msg_cspew(" 0x%02x", readarr[i]);␊ |
| 92 | ␉msg_cspew(". ");␊ |
| 93 | ␉return 0;␊ |
| 94 | }␊ |
| 95 | ␊ |
| 96 | int spi_write_enable(struct flashctx *flash)␊ |
| 97 | {␊ |
| 98 | ␉static const unsigned char cmd[JEDEC_WREN_OUTSIZE] = { JEDEC_WREN };␊ |
| 99 | ␉int result;␊ |
| 100 | ␊ |
| 101 | ␉/* Send WREN (Write Enable) */␊ |
| 102 | ␉result = spi_send_command(flash, sizeof(cmd), 0, cmd, NULL);␊ |
| 103 | ␊ |
| 104 | ␉if (result)␊ |
| 105 | ␉␉msg_cerr("%s failed\n", __func__);␊ |
| 106 | ␊ |
| 107 | ␉return result;␊ |
| 108 | }␊ |
| 109 | ␊ |
| 110 | int spi_write_disable(struct flashctx *flash)␊ |
| 111 | {␊ |
| 112 | ␉static const unsigned char cmd[JEDEC_WRDI_OUTSIZE] = { JEDEC_WRDI };␊ |
| 113 | ␊ |
| 114 | ␉/* Send WRDI (Write Disable) */␊ |
| 115 | ␉return spi_send_command(flash, sizeof(cmd), 0, cmd, NULL);␊ |
| 116 | }␊ |
| 117 | ␊ |
| 118 | static int probe_spi_rdid_generic(struct flashctx *flash, int bytes)␊ |
| 119 | {␊ |
| 120 | ␉unsigned char readarr[4];␊ |
| 121 | ␉uint32_t id1;␊ |
| 122 | ␉uint32_t id2;␊ |
| 123 | ␊ |
| 124 | ␉if (spi_rdid(flash, readarr, bytes)) {␊ |
| 125 | ␉␉return 0;␊ |
| 126 | ␉}␊ |
| 127 | ␊ |
| 128 | ␉if (!oddparity(readarr[0]))␊ |
| 129 | ␉␉msg_cdbg("RDID byte 0 parity violation. ");␊ |
| 130 | ␊ |
| 131 | ␉/* Check if this is a continuation vendor ID.␊ |
| 132 | ␉ * FIXME: Handle continuation device IDs.␊ |
| 133 | ␉ */␊ |
| 134 | ␉if (readarr[0] == 0x7f) {␊ |
| 135 | ␉␉if (!oddparity(readarr[1]))␊ |
| 136 | ␉␉␉msg_cdbg("RDID byte 1 parity violation. ");␊ |
| 137 | ␉␉id1 = (readarr[0] << 8) | readarr[1];␊ |
| 138 | ␉␉id2 = readarr[2];␊ |
| 139 | ␉␉if (bytes > 3) {␊ |
| 140 | ␉␉␉id2 <<= 8;␊ |
| 141 | ␉␉␉id2 |= readarr[3];␊ |
| 142 | ␉␉}␊ |
| 143 | ␉} else {␊ |
| 144 | ␉␉id1 = readarr[0];␊ |
| 145 | ␉␉id2 = (readarr[1] << 8) | readarr[2];␊ |
| 146 | ␉}␊ |
| 147 | ␊ |
| 148 | ␉msg_cdbg("%s: id1 0x%02x, id2 0x%02x\n", __func__, id1, id2);␊ |
| 149 | ␊ |
| 150 | ␉if (id1 == flash->manufacture_id && id2 == flash->model_id) {␊ |
| 151 | ␉␉/* Print the status register to tell the␊ |
| 152 | ␉␉ * user about possible write protection.␊ |
| 153 | ␉␉ */␊ |
| 154 | ␉␉spi_prettyprint_status_register(flash);␊ |
| 155 | ␊ |
| 156 | ␉␉return 1;␊ |
| 157 | ␉}␊ |
| 158 | ␊ |
| 159 | ␉/* Test if this is a pure vendor match. */␊ |
| 160 | ␉if (id1 == flash->manufacture_id &&␊ |
| 161 | ␉ GENERIC_DEVICE_ID == flash->model_id)␊ |
| 162 | ␉␉return 1;␊ |
| 163 | ␊ |
| 164 | ␉/* Test if there is any vendor ID. */␊ |
| 165 | ␉if (GENERIC_MANUF_ID == flash->manufacture_id &&␊ |
| 166 | ␉ id1 != 0xff)␊ |
| 167 | ␉␉return 1;␊ |
| 168 | ␊ |
| 169 | ␉return 0;␊ |
| 170 | }␊ |
| 171 | ␊ |
| 172 | int probe_spi_rdid(struct flashctx *flash)␊ |
| 173 | {␊ |
| 174 | ␉return probe_spi_rdid_generic(flash, 3);␊ |
| 175 | }␊ |
| 176 | ␊ |
| 177 | int probe_spi_rdid4(struct flashctx *flash)␊ |
| 178 | {␊ |
| 179 | ␉/* Some SPI controllers do not support commands with writecnt=1 and␊ |
| 180 | ␉ * readcnt=4.␊ |
| 181 | ␉ */␊ |
| 182 | ␉switch (flash->pgm->spi.type) {␊ |
| 183 | #if CONFIG_INTERNAL == 1␊ |
| 184 | #if defined(__i386__) || defined(__x86_64__)␊ |
| 185 | ␉case SPI_CONTROLLER_IT87XX:␊ |
| 186 | ␉case SPI_CONTROLLER_WBSIO:␊ |
| 187 | ␉␉msg_cinfo("4 byte RDID not supported on this SPI controller\n");␊ |
| 188 | ␉␉return 0;␊ |
| 189 | ␉␉break;␊ |
| 190 | #endif␊ |
| 191 | #endif␊ |
| 192 | ␉default:␊ |
| 193 | ␉␉return probe_spi_rdid_generic(flash, 4);␊ |
| 194 | ␉}␊ |
| 195 | ␊ |
| 196 | ␉return 0;␊ |
| 197 | }␊ |
| 198 | ␊ |
| 199 | int probe_spi_rems(struct flashctx *flash)␊ |
| 200 | {␊ |
| 201 | ␉unsigned char readarr[JEDEC_REMS_INSIZE];␊ |
| 202 | ␉uint32_t id1, id2;␊ |
| 203 | ␊ |
| 204 | ␉if (spi_rems(flash, readarr)) {␊ |
| 205 | ␉␉return 0;␊ |
| 206 | ␉}␊ |
| 207 | ␊ |
| 208 | ␉id1 = readarr[0];␊ |
| 209 | ␉id2 = readarr[1];␊ |
| 210 | ␊ |
| 211 | ␉msg_cdbg("%s: id1 0x%x, id2 0x%x\n", __func__, id1, id2);␊ |
| 212 | ␊ |
| 213 | ␉if (id1 == flash->manufacture_id && id2 == flash->model_id) {␊ |
| 214 | ␉␉/* Print the status register to tell the␊ |
| 215 | ␉␉ * user about possible write protection.␊ |
| 216 | ␉␉ */␊ |
| 217 | ␉␉spi_prettyprint_status_register(flash);␊ |
| 218 | ␊ |
| 219 | ␉␉return 1;␊ |
| 220 | ␉}␊ |
| 221 | ␊ |
| 222 | ␉/* Test if this is a pure vendor match. */␊ |
| 223 | ␉if (id1 == flash->manufacture_id &&␊ |
| 224 | ␉ GENERIC_DEVICE_ID == flash->model_id)␊ |
| 225 | ␉␉return 1;␊ |
| 226 | ␊ |
| 227 | ␉/* Test if there is any vendor ID. */␊ |
| 228 | ␉if (GENERIC_MANUF_ID == flash->manufacture_id &&␊ |
| 229 | ␉ id1 != 0xff)␊ |
| 230 | ␉␉return 1;␊ |
| 231 | ␊ |
| 232 | ␉return 0;␊ |
| 233 | }␊ |
| 234 | ␊ |
| 235 | int probe_spi_res1(struct flashctx *flash)␊ |
| 236 | {␊ |
| 237 | ␉static const unsigned char allff[] = {0xff, 0xff, 0xff};␊ |
| 238 | ␉static const unsigned char all00[] = {0x00, 0x00, 0x00};␊ |
| 239 | ␉unsigned char readarr[3];␊ |
| 240 | ␉uint32_t id2;␊ |
| 241 | ␊ |
| 242 | ␉/* We only want one-byte RES if RDID and REMS are unusable. */␊ |
| 243 | ␊ |
| 244 | ␉/* Check if RDID is usable and does not return 0xff 0xff 0xff or␊ |
| 245 | ␉ * 0x00 0x00 0x00. In that case, RES is pointless.␊ |
| 246 | ␉ */␊ |
| 247 | ␉if (!spi_rdid(flash, readarr, 3) && memcmp(readarr, allff, 3) &&␊ |
| 248 | ␉ memcmp(readarr, all00, 3)) {␊ |
| 249 | ␉␉msg_cdbg("Ignoring RES in favour of RDID.\n");␊ |
| 250 | ␉␉return 0;␊ |
| 251 | ␉}␊ |
| 252 | ␉/* Check if REMS is usable and does not return 0xff 0xff or␊ |
| 253 | ␉ * 0x00 0x00. In that case, RES is pointless.␊ |
| 254 | ␉ */␊ |
| 255 | ␉if (!spi_rems(flash, readarr) &&␊ |
| 256 | ␉ memcmp(readarr, allff, JEDEC_REMS_INSIZE) &&␊ |
| 257 | ␉ memcmp(readarr, all00, JEDEC_REMS_INSIZE)) {␊ |
| 258 | ␉␉msg_cdbg("Ignoring RES in favour of REMS.\n");␊ |
| 259 | ␉␉return 0;␊ |
| 260 | ␉}␊ |
| 261 | ␊ |
| 262 | ␉if (spi_res(flash, readarr, 1)) {␊ |
| 263 | ␉␉return 0;␊ |
| 264 | ␉}␊ |
| 265 | ␊ |
| 266 | ␉id2 = readarr[0];␊ |
| 267 | ␊ |
| 268 | ␉msg_cdbg("%s: id 0x%x\n", __func__, id2);␊ |
| 269 | ␊ |
| 270 | ␉if (id2 != flash->model_id)␊ |
| 271 | ␉␉return 0;␊ |
| 272 | ␊ |
| 273 | ␉/* Print the status register to tell the␊ |
| 274 | ␉ * user about possible write protection.␊ |
| 275 | ␉ */␊ |
| 276 | ␉spi_prettyprint_status_register(flash);␊ |
| 277 | ␉return 1;␊ |
| 278 | }␊ |
| 279 | ␊ |
| 280 | int probe_spi_res2(struct flashctx *flash)␊ |
| 281 | {␊ |
| 282 | ␉unsigned char readarr[2];␊ |
| 283 | ␉uint32_t id1, id2;␊ |
| 284 | ␊ |
| 285 | ␉if (spi_res(flash, readarr, 2)) {␊ |
| 286 | ␉␉return 0;␊ |
| 287 | ␉}␊ |
| 288 | ␊ |
| 289 | ␉id1 = readarr[0];␊ |
| 290 | ␉id2 = readarr[1];␊ |
| 291 | ␊ |
| 292 | ␉msg_cdbg("%s: id1 0x%x, id2 0x%x\n", __func__, id1, id2);␊ |
| 293 | ␊ |
| 294 | ␉if (id1 != flash->manufacture_id || id2 != flash->model_id)␊ |
| 295 | ␉␉return 0;␊ |
| 296 | ␊ |
| 297 | ␉/* Print the status register to tell the␊ |
| 298 | ␉ * user about possible write protection.␊ |
| 299 | ␉ */␊ |
| 300 | ␉spi_prettyprint_status_register(flash);␊ |
| 301 | ␉return 1;␊ |
| 302 | }␊ |
| 303 | ␊ |
| 304 | uint8_t spi_read_status_register(struct flashctx *flash)␊ |
| 305 | {␊ |
| 306 | ␉static const unsigned char cmd[JEDEC_RDSR_OUTSIZE] = { JEDEC_RDSR };␊ |
| 307 | ␉/* FIXME: No workarounds for driver/hardware bugs in generic code. */␊ |
| 308 | ␉unsigned char readarr[2]; /* JEDEC_RDSR_INSIZE=1 but wbsio needs 2 */␊ |
| 309 | ␉int ret;␊ |
| 310 | ␊ |
| 311 | ␉/* Read Status Register */␊ |
| 312 | ␉ret = spi_send_command(flash, sizeof(cmd), sizeof(readarr), cmd,␊ |
| 313 | ␉␉␉ readarr);␊ |
| 314 | ␉if (ret)␊ |
| 315 | ␉␉msg_cerr("RDSR failed!\n");␊ |
| 316 | ␊ |
| 317 | ␉return readarr[0];␊ |
| 318 | }␊ |
| 319 | ␊ |
| 320 | /* Prettyprint the status register. Common definitions. */␊ |
| 321 | void spi_prettyprint_status_register_welwip(uint8_t status)␊ |
| 322 | {␊ |
| 323 | ␉msg_cdbg("Chip status register: Write Enable Latch (WEL) is "␊ |
| 324 | ␉␉ "%sset\n", (status & (1 << 1)) ? "" : "not ");␊ |
| 325 | ␉msg_cdbg("Chip status register: Write In Progress (WIP/BUSY) is "␊ |
| 326 | ␉␉ "%sset\n", (status & (1 << 0)) ? "" : "not ");␊ |
| 327 | }␊ |
| 328 | ␊ |
| 329 | /* Prettyprint the status register. Common definitions. */␊ |
| 330 | void spi_prettyprint_status_register_bp3210(uint8_t status, int bp)␊ |
| 331 | {␊ |
| 332 | ␉switch (bp) {␊ |
| 333 | ␉/* Fall through. */␊ |
| 334 | ␉case 3:␊ |
| 335 | ␉␉msg_cdbg("Chip status register: Bit 5 / Block Protect 3 (BP3) "␊ |
| 336 | ␉␉␉ "is %sset\n", (status & (1 << 5)) ? "" : "not ");␊ |
| 337 | ␉case 2:␊ |
| 338 | ␉␉msg_cdbg("Chip status register: Bit 4 / Block Protect 2 (BP2) "␊ |
| 339 | ␉␉␉ "is %sset\n", (status & (1 << 4)) ? "" : "not ");␊ |
| 340 | ␉case 1:␊ |
| 341 | ␉␉msg_cdbg("Chip status register: Bit 3 / Block Protect 1 (BP1) "␊ |
| 342 | ␉␉␉ "is %sset\n", (status & (1 << 3)) ? "" : "not ");␊ |
| 343 | ␉case 0:␊ |
| 344 | ␉␉msg_cdbg("Chip status register: Bit 2 / Block Protect 0 (BP0) "␊ |
| 345 | ␉␉␉ "is %sset\n", (status & (1 << 2)) ? "" : "not ");␊ |
| 346 | ␉}␊ |
| 347 | }␊ |
| 348 | ␊ |
| 349 | /* Prettyprint the status register. Unnamed bits. */␊ |
| 350 | void spi_prettyprint_status_register_bit(uint8_t status, int bit)␊ |
| 351 | {␊ |
| 352 | ␉msg_cdbg("Chip status register: Bit %i "␊ |
| 353 | ␉␉ "is %sset\n", bit, (status & (1 << bit)) ? "" : "not ");␊ |
| 354 | }␊ |
| 355 | ␊ |
| 356 | static void spi_prettyprint_status_register_common(uint8_t status)␊ |
| 357 | {␊ |
| 358 | ␉spi_prettyprint_status_register_bp3210(status, 3);␊ |
| 359 | ␉spi_prettyprint_status_register_welwip(status);␊ |
| 360 | }␊ |
| 361 | ␊ |
| 362 | /* Prettyprint the status register. Works for␊ |
| 363 | * ST M25P series␊ |
| 364 | * MX MX25L series␊ |
| 365 | */␊ |
| 366 | void spi_prettyprint_status_register_st_m25p(uint8_t status)␊ |
| 367 | {␊ |
| 368 | ␉msg_cdbg("Chip status register: Status Register Write Disable "␊ |
| 369 | ␉␉ "(SRWD) is %sset\n", (status & (1 << 7)) ? "" : "not ");␊ |
| 370 | ␉msg_cdbg("Chip status register: Bit 6 is "␊ |
| 371 | ␉␉ "%sset\n", (status & (1 << 6)) ? "" : "not ");␊ |
| 372 | ␉spi_prettyprint_status_register_common(status);␊ |
| 373 | }␊ |
| 374 | ␊ |
| 375 | void spi_prettyprint_status_register_sst25(uint8_t status)␊ |
| 376 | {␊ |
| 377 | ␉msg_cdbg("Chip status register: Block Protect Write Disable "␊ |
| 378 | ␉␉ "(BPL) is %sset\n", (status & (1 << 7)) ? "" : "not ");␊ |
| 379 | ␉msg_cdbg("Chip status register: Auto Address Increment Programming "␊ |
| 380 | ␉␉ "(AAI) is %sset\n", (status & (1 << 6)) ? "" : "not ");␊ |
| 381 | ␉spi_prettyprint_status_register_common(status);␊ |
| 382 | }␊ |
| 383 | ␊ |
| 384 | /* Prettyprint the status register. Works for␊ |
| 385 | * SST 25VF016␊ |
| 386 | */␊ |
| 387 | void spi_prettyprint_status_register_sst25vf016(uint8_t status)␊ |
| 388 | {␊ |
| 389 | ␉static const char *const bpt[] = {␊ |
| 390 | ␉␉"none",␊ |
| 391 | ␉␉"1F0000H-1FFFFFH",␊ |
| 392 | ␉␉"1E0000H-1FFFFFH",␊ |
| 393 | ␉␉"1C0000H-1FFFFFH",␊ |
| 394 | ␉␉"180000H-1FFFFFH",␊ |
| 395 | ␉␉"100000H-1FFFFFH",␊ |
| 396 | ␉␉"all", "all"␊ |
| 397 | ␉};␊ |
| 398 | ␉spi_prettyprint_status_register_sst25(status);␊ |
| 399 | ␉msg_cdbg("Resulting block protection : %s\n",␊ |
| 400 | ␉␉ bpt[(status & 0x1c) >> 2]);␊ |
| 401 | }␊ |
| 402 | ␊ |
| 403 | void spi_prettyprint_status_register_sst25vf040b(uint8_t status)␊ |
| 404 | {␊ |
| 405 | ␉static const char *const bpt[] = {␊ |
| 406 | ␉␉"none",␊ |
| 407 | ␉␉"0x70000-0x7ffff",␊ |
| 408 | ␉␉"0x60000-0x7ffff",␊ |
| 409 | ␉␉"0x40000-0x7ffff",␊ |
| 410 | ␉␉"all blocks", "all blocks", "all blocks", "all blocks"␊ |
| 411 | ␉};␊ |
| 412 | ␉spi_prettyprint_status_register_sst25(status);␊ |
| 413 | ␉msg_cdbg("Resulting block protection : %s\n",␊ |
| 414 | ␉␉bpt[(status & 0x1c) >> 2]);␊ |
| 415 | }␊ |
| 416 | ␊ |
| 417 | int spi_prettyprint_status_register(struct flashctx *flash)␊ |
| 418 | {␊ |
| 419 | ␉uint8_t status;␊ |
| 420 | ␊ |
| 421 | ␉status = spi_read_status_register(flash);␊ |
| 422 | ␉msg_cdbg("Chip status register is %02x\n", status);␊ |
| 423 | ␉switch (flash->manufacture_id) {␊ |
| 424 | ␉case ST_ID:␊ |
| 425 | ␉␉if (((flash->model_id & 0xff00) == 0x2000) ||␊ |
| 426 | ␉␉ ((flash->model_id & 0xff00) == 0x2500))␊ |
| 427 | ␉␉␉spi_prettyprint_status_register_st_m25p(status);␊ |
| 428 | ␉␉break;␊ |
| 429 | ␉case MACRONIX_ID:␊ |
| 430 | ␉␉if ((flash->model_id & 0xff00) == 0x2000)␊ |
| 431 | ␉␉␉spi_prettyprint_status_register_st_m25p(status);␊ |
| 432 | ␉␉break;␊ |
| 433 | ␉case SST_ID:␊ |
| 434 | ␉␉switch (flash->model_id) {␊ |
| 435 | ␉␉case 0x2541:␊ |
| 436 | ␉␉␉spi_prettyprint_status_register_sst25vf016(status);␊ |
| 437 | ␉␉␉break;␊ |
| 438 | ␉␉case 0x8d:␊ |
| 439 | ␉␉case 0x258d:␊ |
| 440 | ␉␉␉spi_prettyprint_status_register_sst25vf040b(status);␊ |
| 441 | ␉␉␉break;␊ |
| 442 | ␉␉default:␊ |
| 443 | ␉␉␉spi_prettyprint_status_register_sst25(status);␊ |
| 444 | ␉␉␉break;␊ |
| 445 | ␉␉}␊ |
| 446 | ␉␉break;␊ |
| 447 | ␉}␊ |
| 448 | ␉return 0;␊ |
| 449 | }␊ |
| 450 | ␊ |
| 451 | int spi_chip_erase_60(struct flashctx *flash)␊ |
| 452 | {␊ |
| 453 | ␉int result;␊ |
| 454 | ␉struct spi_command cmds[] = {␊ |
| 455 | ␉{␊ |
| 456 | ␉␉.writecnt␉= JEDEC_WREN_OUTSIZE,␊ |
| 457 | ␉␉.writearr␉= (const unsigned char[]){ JEDEC_WREN },␊ |
| 458 | ␉␉.readcnt␉= 0,␊ |
| 459 | ␉␉.readarr␉= NULL,␊ |
| 460 | ␉}, {␊ |
| 461 | ␉␉.writecnt␉= JEDEC_CE_60_OUTSIZE,␊ |
| 462 | ␉␉.writearr␉= (const unsigned char[]){ JEDEC_CE_60 },␊ |
| 463 | ␉␉.readcnt␉= 0,␊ |
| 464 | ␉␉.readarr␉= NULL,␊ |
| 465 | ␉}, {␊ |
| 466 | ␉␉.writecnt␉= 0,␊ |
| 467 | ␉␉.writearr␉= NULL,␊ |
| 468 | ␉␉.readcnt␉= 0,␊ |
| 469 | ␉␉.readarr␉= NULL,␊ |
| 470 | ␉}};␊ |
| 471 | ␉␊ |
| 472 | ␉result = spi_send_multicommand(flash, cmds);␊ |
| 473 | ␉if (result) {␊ |
| 474 | ␉␉msg_cerr("%s failed during command execution\n",␊ |
| 475 | ␉␉␉__func__);␊ |
| 476 | ␉␉return result;␊ |
| 477 | ␉}␊ |
| 478 | ␉/* Wait until the Write-In-Progress bit is cleared.␊ |
| 479 | ␉ * This usually takes 1-85 s, so wait in 1 s steps.␊ |
| 480 | ␉ */␊ |
| 481 | ␉/* FIXME: We assume spi_read_status_register will never fail. */␊ |
| 482 | ␉while (spi_read_status_register(flash) & SPI_SR_WIP)␊ |
| 483 | ␉␉programmer_delay(1000 * 1000);␊ |
| 484 | ␉/* FIXME: Check the status register for errors. */␊ |
| 485 | ␉return 0;␊ |
| 486 | }␊ |
| 487 | ␊ |
| 488 | int spi_chip_erase_c7(struct flashctx *flash)␊ |
| 489 | {␊ |
| 490 | ␉int result;␊ |
| 491 | ␉struct spi_command cmds[] = {␊ |
| 492 | ␉{␊ |
| 493 | ␉␉.writecnt␉= JEDEC_WREN_OUTSIZE,␊ |
| 494 | ␉␉.writearr␉= (const unsigned char[]){ JEDEC_WREN },␊ |
| 495 | ␉␉.readcnt␉= 0,␊ |
| 496 | ␉␉.readarr␉= NULL,␊ |
| 497 | ␉}, {␊ |
| 498 | ␉␉.writecnt␉= JEDEC_CE_C7_OUTSIZE,␊ |
| 499 | ␉␉.writearr␉= (const unsigned char[]){ JEDEC_CE_C7 },␊ |
| 500 | ␉␉.readcnt␉= 0,␊ |
| 501 | ␉␉.readarr␉= NULL,␊ |
| 502 | ␉}, {␊ |
| 503 | ␉␉.writecnt␉= 0,␊ |
| 504 | ␉␉.writearr␉= NULL,␊ |
| 505 | ␉␉.readcnt␉= 0,␊ |
| 506 | ␉␉.readarr␉= NULL,␊ |
| 507 | ␉}};␊ |
| 508 | ␊ |
| 509 | ␉result = spi_send_multicommand(flash, cmds);␊ |
| 510 | ␉if (result) {␊ |
| 511 | ␉␉msg_cerr("%s failed during command execution\n", __func__);␊ |
| 512 | ␉␉return result;␊ |
| 513 | ␉}␊ |
| 514 | ␉/* Wait until the Write-In-Progress bit is cleared.␊ |
| 515 | ␉ * This usually takes 1-85 s, so wait in 1 s steps.␊ |
| 516 | ␉ */␊ |
| 517 | ␉/* FIXME: We assume spi_read_status_register will never fail. */␊ |
| 518 | ␉while (spi_read_status_register(flash) & SPI_SR_WIP)␊ |
| 519 | ␉␉programmer_delay(1000 * 1000);␊ |
| 520 | ␉/* FIXME: Check the status register for errors. */␊ |
| 521 | ␉return 0;␊ |
| 522 | }␊ |
| 523 | ␊ |
| 524 | int spi_block_erase_52(struct flashctx *flash, unsigned int addr,␊ |
| 525 | ␉␉ unsigned int blocklen)␊ |
| 526 | {␊ |
| 527 | ␉int result;␊ |
| 528 | ␉struct spi_command cmds[] = {␊ |
| 529 | ␉{␊ |
| 530 | ␉␉.writecnt␉= JEDEC_WREN_OUTSIZE,␊ |
| 531 | ␉␉.writearr␉= (const unsigned char[]){ JEDEC_WREN },␊ |
| 532 | ␉␉.readcnt␉= 0,␊ |
| 533 | ␉␉.readarr␉= NULL,␊ |
| 534 | ␉}, {␊ |
| 535 | ␉␉.writecnt␉= JEDEC_BE_52_OUTSIZE,␊ |
| 536 | ␉␉.writearr␉= (const unsigned char[]){␊ |
| 537 | ␉␉␉␉␉JEDEC_BE_52,␊ |
| 538 | ␉␉␉␉␉(addr >> 16) & 0xff,␊ |
| 539 | ␉␉␉␉␉(addr >> 8) & 0xff,␊ |
| 540 | ␉␉␉␉␉(addr & 0xff)␊ |
| 541 | ␉␉␉␉},␊ |
| 542 | ␉␉.readcnt␉= 0,␊ |
| 543 | ␉␉.readarr␉= NULL,␊ |
| 544 | ␉}, {␊ |
| 545 | ␉␉.writecnt␉= 0,␊ |
| 546 | ␉␉.writearr␉= NULL,␊ |
| 547 | ␉␉.readcnt␉= 0,␊ |
| 548 | ␉␉.readarr␉= NULL,␊ |
| 549 | ␉}};␊ |
| 550 | ␊ |
| 551 | ␉result = spi_send_multicommand(flash, cmds);␊ |
| 552 | ␉if (result) {␊ |
| 553 | ␉␉msg_cerr("%s failed during command execution at address 0x%x\n",␊ |
| 554 | ␉␉␉__func__, addr);␊ |
| 555 | ␉␉return result;␊ |
| 556 | ␉}␊ |
| 557 | ␉/* Wait until the Write-In-Progress bit is cleared.␊ |
| 558 | ␉ * This usually takes 100-4000 ms, so wait in 100 ms steps.␊ |
| 559 | ␉ */␊ |
| 560 | ␉while (spi_read_status_register(flash) & SPI_SR_WIP)␊ |
| 561 | ␉␉programmer_delay(100 * 1000);␊ |
| 562 | ␉/* FIXME: Check the status register for errors. */␊ |
| 563 | ␉return 0;␊ |
| 564 | }␊ |
| 565 | ␊ |
| 566 | /* Block size is usually␊ |
| 567 | * 64k for Macronix␊ |
| 568 | * 32k for SST␊ |
| 569 | * 4-32k non-uniform for EON␊ |
| 570 | */␊ |
| 571 | int spi_block_erase_d8(struct flashctx *flash, unsigned int addr,␊ |
| 572 | ␉␉ unsigned int blocklen)␊ |
| 573 | {␊ |
| 574 | ␉int result;␊ |
| 575 | ␉struct spi_command cmds[] = {␊ |
| 576 | ␉{␊ |
| 577 | ␉␉.writecnt␉= JEDEC_WREN_OUTSIZE,␊ |
| 578 | ␉␉.writearr␉= (const unsigned char[]){ JEDEC_WREN },␊ |
| 579 | ␉␉.readcnt␉= 0,␊ |
| 580 | ␉␉.readarr␉= NULL,␊ |
| 581 | ␉}, {␊ |
| 582 | ␉␉.writecnt␉= JEDEC_BE_D8_OUTSIZE,␊ |
| 583 | ␉␉.writearr␉= (const unsigned char[]){␊ |
| 584 | ␉␉␉␉␉JEDEC_BE_D8,␊ |
| 585 | ␉␉␉␉␉(addr >> 16) & 0xff,␊ |
| 586 | ␉␉␉␉␉(addr >> 8) & 0xff,␊ |
| 587 | ␉␉␉␉␉(addr & 0xff)␊ |
| 588 | ␉␉␉␉},␊ |
| 589 | ␉␉.readcnt␉= 0,␊ |
| 590 | ␉␉.readarr␉= NULL,␊ |
| 591 | ␉}, {␊ |
| 592 | ␉␉.writecnt␉= 0,␊ |
| 593 | ␉␉.writearr␉= NULL,␊ |
| 594 | ␉␉.readcnt␉= 0,␊ |
| 595 | ␉␉.readarr␉= NULL,␊ |
| 596 | ␉}};␊ |
| 597 | ␊ |
| 598 | ␉result = spi_send_multicommand(flash, cmds);␊ |
| 599 | ␉if (result) {␊ |
| 600 | ␉␉msg_cerr("%s failed during command execution at address 0x%x\n",␊ |
| 601 | ␉␉␉__func__, addr);␊ |
| 602 | ␉␉return result;␊ |
| 603 | ␉}␊ |
| 604 | ␉/* Wait until the Write-In-Progress bit is cleared.␊ |
| 605 | ␉ * This usually takes 100-4000 ms, so wait in 100 ms steps.␊ |
| 606 | ␉ */␊ |
| 607 | ␉while (spi_read_status_register(flash) & SPI_SR_WIP)␊ |
| 608 | ␉␉programmer_delay(100 * 1000);␊ |
| 609 | ␉/* FIXME: Check the status register for errors. */␊ |
| 610 | ␉return 0;␊ |
| 611 | }␊ |
| 612 | ␊ |
| 613 | /* Block size is usually␊ |
| 614 | * 4k for PMC␊ |
| 615 | */␊ |
| 616 | int spi_block_erase_d7(struct flashctx *flash, unsigned int addr,␊ |
| 617 | ␉␉ unsigned int blocklen)␊ |
| 618 | {␊ |
| 619 | ␉int result;␊ |
| 620 | ␉struct spi_command cmds[] = {␊ |
| 621 | ␉{␊ |
| 622 | ␉␉.writecnt␉= JEDEC_WREN_OUTSIZE,␊ |
| 623 | ␉␉.writearr␉= (const unsigned char[]){ JEDEC_WREN },␊ |
| 624 | ␉␉.readcnt␉= 0,␊ |
| 625 | ␉␉.readarr␉= NULL,␊ |
| 626 | ␉}, {␊ |
| 627 | ␉␉.writecnt␉= JEDEC_BE_D7_OUTSIZE,␊ |
| 628 | ␉␉.writearr␉= (const unsigned char[]){␊ |
| 629 | ␉␉␉␉␉JEDEC_BE_D7,␊ |
| 630 | ␉␉␉␉␉(addr >> 16) & 0xff,␊ |
| 631 | ␉␉␉␉␉(addr >> 8) & 0xff,␊ |
| 632 | ␉␉␉␉␉(addr & 0xff)␊ |
| 633 | ␉␉␉␉},␊ |
| 634 | ␉␉.readcnt␉= 0,␊ |
| 635 | ␉␉.readarr␉= NULL,␊ |
| 636 | ␉}, {␊ |
| 637 | ␉␉.writecnt␉= 0,␊ |
| 638 | ␉␉.writearr␉= NULL,␊ |
| 639 | ␉␉.readcnt␉= 0,␊ |
| 640 | ␉␉.readarr␉= NULL,␊ |
| 641 | ␉}};␊ |
| 642 | ␊ |
| 643 | ␉result = spi_send_multicommand(flash, cmds);␊ |
| 644 | ␉if (result) {␊ |
| 645 | ␉␉msg_cerr("%s failed during command execution at address 0x%x\n",␊ |
| 646 | ␉␉␉__func__, addr);␊ |
| 647 | ␉␉return result;␊ |
| 648 | ␉}␊ |
| 649 | ␉/* Wait until the Write-In-Progress bit is cleared.␊ |
| 650 | ␉ * This usually takes 100-4000 ms, so wait in 100 ms steps.␊ |
| 651 | ␉ */␊ |
| 652 | ␉while (spi_read_status_register(flash) & SPI_SR_WIP)␊ |
| 653 | ␉␉programmer_delay(100 * 1000);␊ |
| 654 | ␉/* FIXME: Check the status register for errors. */␊ |
| 655 | ␉return 0;␊ |
| 656 | }␊ |
| 657 | ␊ |
| 658 | /* Sector size is usually 4k, though Macronix eliteflash has 64k */␊ |
| 659 | int spi_block_erase_20(struct flashctx *flash, unsigned int addr,␊ |
| 660 | ␉␉ unsigned int blocklen)␊ |
| 661 | {␊ |
| 662 | ␉int result;␊ |
| 663 | ␉struct spi_command cmds[] = {␊ |
| 664 | ␉{␊ |
| 665 | ␉␉.writecnt␉= JEDEC_WREN_OUTSIZE,␊ |
| 666 | ␉␉.writearr␉= (const unsigned char[]){ JEDEC_WREN },␊ |
| 667 | ␉␉.readcnt␉= 0,␊ |
| 668 | ␉␉.readarr␉= NULL,␊ |
| 669 | ␉}, {␊ |
| 670 | ␉␉.writecnt␉= JEDEC_SE_OUTSIZE,␊ |
| 671 | ␉␉.writearr␉= (const unsigned char[]){␊ |
| 672 | ␉␉␉␉␉JEDEC_SE,␊ |
| 673 | ␉␉␉␉␉(addr >> 16) & 0xff,␊ |
| 674 | ␉␉␉␉␉(addr >> 8) & 0xff,␊ |
| 675 | ␉␉␉␉␉(addr & 0xff)␊ |
| 676 | ␉␉␉␉},␊ |
| 677 | ␉␉.readcnt␉= 0,␊ |
| 678 | ␉␉.readarr␉= NULL,␊ |
| 679 | ␉}, {␊ |
| 680 | ␉␉.writecnt␉= 0,␊ |
| 681 | ␉␉.writearr␉= NULL,␊ |
| 682 | ␉␉.readcnt␉= 0,␊ |
| 683 | ␉␉.readarr␉= NULL,␊ |
| 684 | ␉}};␊ |
| 685 | ␊ |
| 686 | ␉result = spi_send_multicommand(flash, cmds);␊ |
| 687 | ␉if (result) {␊ |
| 688 | ␉␉msg_cerr("%s failed during command execution at address 0x%x\n",␊ |
| 689 | ␉␉␉__func__, addr);␊ |
| 690 | ␉␉return result;␊ |
| 691 | ␉}␊ |
| 692 | ␉/* Wait until the Write-In-Progress bit is cleared.␊ |
| 693 | ␉ * This usually takes 15-800 ms, so wait in 10 ms steps.␊ |
| 694 | ␉ */␊ |
| 695 | ␉while (spi_read_status_register(flash) & SPI_SR_WIP)␊ |
| 696 | ␉␉programmer_delay(10 * 1000);␊ |
| 697 | ␉/* FIXME: Check the status register for errors. */␊ |
| 698 | ␉return 0;␊ |
| 699 | }␊ |
| 700 | ␊ |
| 701 | int spi_block_erase_60(struct flashctx *flash, unsigned int addr,␊ |
| 702 | ␉␉ unsigned int blocklen)␊ |
| 703 | {␊ |
| 704 | ␉if ((addr != 0) || (blocklen != flash->total_size * 1024)) {␊ |
| 705 | ␉␉msg_cerr("%s called with incorrect arguments\n",␊ |
| 706 | ␉␉␉__func__);␊ |
| 707 | ␉␉return -1;␊ |
| 708 | ␉}␊ |
| 709 | ␉return spi_chip_erase_60(flash);␊ |
| 710 | }␊ |
| 711 | ␊ |
| 712 | int spi_block_erase_c7(struct flashctx *flash, unsigned int addr,␊ |
| 713 | ␉␉ unsigned int blocklen)␊ |
| 714 | {␊ |
| 715 | ␉if ((addr != 0) || (blocklen != flash->total_size * 1024)) {␊ |
| 716 | ␉␉msg_cerr("%s called with incorrect arguments\n",␊ |
| 717 | ␉␉␉__func__);␊ |
| 718 | ␉␉return -1;␊ |
| 719 | ␉}␊ |
| 720 | ␉return spi_chip_erase_c7(flash);␊ |
| 721 | }␊ |
| 722 | ␊ |
| 723 | erasefunc_t *spi_get_erasefn_from_opcode(uint8_t opcode)␊ |
| 724 | {␊ |
| 725 | ␉switch(opcode){␊ |
| 726 | ␉case 0xff:␊ |
| 727 | ␉case 0x00:␊ |
| 728 | ␉␉/* Not specified, assuming "not supported". */␊ |
| 729 | ␉␉return NULL;␊ |
| 730 | ␉case 0x20:␊ |
| 731 | ␉␉return &spi_block_erase_20;␊ |
| 732 | ␉case 0x52:␊ |
| 733 | ␉␉return &spi_block_erase_52;␊ |
| 734 | ␉case 0x60:␊ |
| 735 | ␉␉return &spi_block_erase_60;␊ |
| 736 | ␉case 0xc7:␊ |
| 737 | ␉␉return &spi_block_erase_c7;␊ |
| 738 | ␉case 0xd7:␊ |
| 739 | ␉␉return &spi_block_erase_d7;␊ |
| 740 | ␉case 0xd8:␊ |
| 741 | ␉␉return &spi_block_erase_d8;␊ |
| 742 | ␉default:␊ |
| 743 | ␉␉msg_cinfo("%s: unknown erase opcode (0x%02x). Please report "␊ |
| 744 | ␉␉␉ "this at flashrom@flashrom.org\n", __func__, opcode);␊ |
| 745 | ␉␉return NULL;␊ |
| 746 | ␉}␊ |
| 747 | }␊ |
| 748 | ␊ |
| 749 | int spi_write_status_enable(struct flashctx *flash)␊ |
| 750 | {␊ |
| 751 | ␉static const unsigned char cmd[JEDEC_EWSR_OUTSIZE] = { JEDEC_EWSR };␊ |
| 752 | ␉int result;␊ |
| 753 | ␊ |
| 754 | ␉/* Send EWSR (Enable Write Status Register). */␊ |
| 755 | ␉result = spi_send_command(flash, sizeof(cmd), JEDEC_EWSR_INSIZE, cmd, NULL);␊ |
| 756 | ␊ |
| 757 | ␉if (result)␊ |
| 758 | ␉␉msg_cerr("%s failed\n", __func__);␊ |
| 759 | ␊ |
| 760 | ␉return result;␊ |
| 761 | }␊ |
| 762 | ␊ |
| 763 | /*␊ |
| 764 | * This is according the SST25VF016 datasheet, who knows it is more␊ |
| 765 | * generic that this...␊ |
| 766 | */␊ |
| 767 | static int spi_write_status_register_flag(struct flashctx *flash, int status, const unsigned char enable_opcode)␊ |
| 768 | {␊ |
| 769 | ␉int result;␊ |
| 770 | ␉int i = 0;␊ |
| 771 | ␉/*␊ |
| 772 | ␉ * WRSR requires either EWSR or WREN depending on chip type.␊ |
| 773 | ␉ * The code below relies on the fact hat EWSR and WREN have the same␊ |
| 774 | ␉ * INSIZE and OUTSIZE.␊ |
| 775 | ␉ */␊ |
| 776 | ␉struct spi_command cmds[] = {␊ |
| 777 | ␉{␊ |
| 778 | ␉␉.writecnt␉= JEDEC_WREN_OUTSIZE,␊ |
| 779 | ␉␉.writearr␉= (const unsigned char[]){ enable_opcode },␊ |
| 780 | ␉␉.readcnt␉= 0,␊ |
| 781 | ␉␉.readarr␉= NULL,␊ |
| 782 | ␉}, {␊ |
| 783 | ␉␉.writecnt␉= JEDEC_WRSR_OUTSIZE,␊ |
| 784 | ␉␉.writearr␉= (const unsigned char[]){ JEDEC_WRSR, (unsigned char) status },␊ |
| 785 | ␉␉.readcnt␉= 0,␊ |
| 786 | ␉␉.readarr␉= NULL,␊ |
| 787 | ␉}, {␊ |
| 788 | ␉␉.writecnt␉= 0,␊ |
| 789 | ␉␉.writearr␉= NULL,␊ |
| 790 | ␉␉.readcnt␉= 0,␊ |
| 791 | ␉␉.readarr␉= NULL,␊ |
| 792 | ␉}};␊ |
| 793 | ␊ |
| 794 | ␉result = spi_send_multicommand(flash, cmds);␊ |
| 795 | ␉if (result) {␊ |
| 796 | ␉␉msg_cerr("%s failed during command execution\n", __func__);␊ |
| 797 | ␉␉/* No point in waiting for the command to complete if execution␊ |
| 798 | ␉␉ * failed.␊ |
| 799 | ␉␉ */␊ |
| 800 | ␉␉return result;␊ |
| 801 | ␉}␊ |
| 802 | ␉/* WRSR performs a self-timed erase before the changes take effect.␊ |
| 803 | ␉ * This may take 50-85 ms in most cases, and some chips apparently␊ |
| 804 | ␉ * allow running RDSR only once. Therefore pick an initial delay of␊ |
| 805 | ␉ * 100 ms, then wait in 10 ms steps until a total of 5 s have elapsed.␊ |
| 806 | ␉ */␊ |
| 807 | ␉programmer_delay(100 * 1000);␊ |
| 808 | ␉while (spi_read_status_register(flash) & SPI_SR_WIP) {␊ |
| 809 | ␉␉if (++i > 490) {␊ |
| 810 | ␉␉␉msg_cerr("Error: WIP bit after WRSR never cleared\n");␊ |
| 811 | ␉␉␉return TIMEOUT_ERROR;␊ |
| 812 | ␉␉}␊ |
| 813 | ␉␉programmer_delay(10 * 1000);␊ |
| 814 | ␉}␊ |
| 815 | ␉return 0;␊ |
| 816 | }␊ |
| 817 | ␊ |
| 818 | int spi_write_status_register(struct flashctx *flash, int status)␊ |
| 819 | {␊ |
| 820 | ␉int feature_bits = flash->feature_bits;␊ |
| 821 | ␉int ret = 1;␊ |
| 822 | ␊ |
| 823 | ␉if (!(feature_bits & (FEATURE_WRSR_WREN | FEATURE_WRSR_EWSR))) {␊ |
| 824 | ␉␉msg_cdbg("Missing status register write definition, assuming "␊ |
| 825 | ␉␉␉ "EWSR is needed\n");␊ |
| 826 | ␉␉feature_bits |= FEATURE_WRSR_EWSR;␊ |
| 827 | ␉}␊ |
| 828 | ␉if (feature_bits & FEATURE_WRSR_WREN)␊ |
| 829 | ␉␉ret = spi_write_status_register_flag(flash, status, JEDEC_WREN);␊ |
| 830 | ␉if (ret && (feature_bits & FEATURE_WRSR_EWSR))␊ |
| 831 | ␉␉ret = spi_write_status_register_flag(flash, status, JEDEC_EWSR);␊ |
| 832 | ␉return ret;␊ |
| 833 | }␊ |
| 834 | ␊ |
| 835 | int spi_byte_program(struct flashctx *flash, unsigned int addr,␊ |
| 836 | ␉␉ uint8_t databyte)␊ |
| 837 | {␊ |
| 838 | ␉int result;␊ |
| 839 | ␉struct spi_command cmds[] = {␊ |
| 840 | ␉{␊ |
| 841 | ␉␉.writecnt␉= JEDEC_WREN_OUTSIZE,␊ |
| 842 | ␉␉.writearr␉= (const unsigned char[]){ JEDEC_WREN },␊ |
| 843 | ␉␉.readcnt␉= 0,␊ |
| 844 | ␉␉.readarr␉= NULL,␊ |
| 845 | ␉}, {␊ |
| 846 | ␉␉.writecnt␉= JEDEC_BYTE_PROGRAM_OUTSIZE,␊ |
| 847 | ␉␉.writearr␉= (const unsigned char[]){␊ |
| 848 | ␉␉␉␉␉JEDEC_BYTE_PROGRAM,␊ |
| 849 | ␉␉␉␉␉(addr >> 16) & 0xff,␊ |
| 850 | ␉␉␉␉␉(addr >> 8) & 0xff,␊ |
| 851 | ␉␉␉␉␉(addr & 0xff),␊ |
| 852 | ␉␉␉␉␉databyte␊ |
| 853 | ␉␉␉␉},␊ |
| 854 | ␉␉.readcnt␉= 0,␊ |
| 855 | ␉␉.readarr␉= NULL,␊ |
| 856 | ␉}, {␊ |
| 857 | ␉␉.writecnt␉= 0,␊ |
| 858 | ␉␉.writearr␉= NULL,␊ |
| 859 | ␉␉.readcnt␉= 0,␊ |
| 860 | ␉␉.readarr␉= NULL,␊ |
| 861 | ␉}};␊ |
| 862 | ␊ |
| 863 | ␉result = spi_send_multicommand(flash, cmds);␊ |
| 864 | ␉if (result) {␊ |
| 865 | ␉␉msg_cerr("%s failed during command execution at address 0x%x\n",␊ |
| 866 | ␉␉␉__func__, addr);␊ |
| 867 | ␉}␊ |
| 868 | ␉return result;␊ |
| 869 | }␊ |
| 870 | ␊ |
| 871 | int spi_nbyte_program(struct flashctx *flash, unsigned int addr, uint8_t *bytes,␊ |
| 872 | ␉␉ unsigned int len)␊ |
| 873 | {␊ |
| 874 | ␉int result;␊ |
| 875 | ␉/* FIXME: Switch to malloc based on len unless that kills speed. */␊ |
| 876 | ␉unsigned char cmd[JEDEC_BYTE_PROGRAM_OUTSIZE - 1 + 256] = {␊ |
| 877 | ␉␉JEDEC_BYTE_PROGRAM,␊ |
| 878 | ␉␉(addr >> 16) & 0xff,␊ |
| 879 | ␉␉(addr >> 8) & 0xff,␊ |
| 880 | ␉␉(addr >> 0) & 0xff,␊ |
| 881 | ␉};␊ |
| 882 | ␉struct spi_command cmds[] = {␊ |
| 883 | ␉{␊ |
| 884 | ␉␉.writecnt␉= JEDEC_WREN_OUTSIZE,␊ |
| 885 | ␉␉.writearr␉= (const unsigned char[]){ JEDEC_WREN },␊ |
| 886 | ␉␉.readcnt␉= 0,␊ |
| 887 | ␉␉.readarr␉= NULL,␊ |
| 888 | ␉}, {␊ |
| 889 | ␉␉.writecnt␉= JEDEC_BYTE_PROGRAM_OUTSIZE - 1 + len,␊ |
| 890 | ␉␉.writearr␉= cmd,␊ |
| 891 | ␉␉.readcnt␉= 0,␊ |
| 892 | ␉␉.readarr␉= NULL,␊ |
| 893 | ␉}, {␊ |
| 894 | ␉␉.writecnt␉= 0,␊ |
| 895 | ␉␉.writearr␉= NULL,␊ |
| 896 | ␉␉.readcnt␉= 0,␊ |
| 897 | ␉␉.readarr␉= NULL,␊ |
| 898 | ␉}};␊ |
| 899 | ␊ |
| 900 | ␉if (!len) {␊ |
| 901 | ␉␉msg_cerr("%s called for zero-length write\n", __func__);␊ |
| 902 | ␉␉return 1;␊ |
| 903 | ␉}␊ |
| 904 | ␉if (len > 256) {␊ |
| 905 | ␉␉msg_cerr("%s called for too long a write\n", __func__);␊ |
| 906 | ␉␉return 1;␊ |
| 907 | ␉}␊ |
| 908 | ␊ |
| 909 | ␉memcpy(&cmd[4], bytes, len);␊ |
| 910 | ␊ |
| 911 | ␉result = spi_send_multicommand(flash, cmds);␊ |
| 912 | ␉if (result) {␊ |
| 913 | ␉␉msg_cerr("%s failed during command execution at address 0x%x\n",␊ |
| 914 | ␉␉␉__func__, addr);␊ |
| 915 | ␉}␊ |
| 916 | ␉return result;␊ |
| 917 | }␊ |
| 918 | ␊ |
| 919 | /* A generic brute-force block protection disable works like this:␊ |
| 920 | * Write 0x00 to the status register. Check if any locks are still set (that␊ |
| 921 | * part is chip specific). Repeat once.␊ |
| 922 | */␊ |
| 923 | int spi_disable_blockprotect(struct flashctx *flash)␊ |
| 924 | {␊ |
| 925 | ␉uint8_t status;␊ |
| 926 | ␉int result;␊ |
| 927 | ␊ |
| 928 | ␉status = spi_read_status_register(flash);␊ |
| 929 | ␉/* If block protection is disabled, stop here. */␊ |
| 930 | ␉if ((status & 0x3c) == 0)␊ |
| 931 | ␉␉return 0;␊ |
| 932 | ␊ |
| 933 | ␉msg_cdbg("Some block protection in effect, disabling\n");␊ |
| 934 | ␉result = spi_write_status_register(flash, status & ~0x3c);␊ |
| 935 | ␉if (result) {␊ |
| 936 | ␉␉msg_cerr("spi_write_status_register failed\n");␊ |
| 937 | ␉␉return result;␊ |
| 938 | ␉}␊ |
| 939 | ␉status = spi_read_status_register(flash);␊ |
| 940 | ␉if ((status & 0x3c) != 0) {␊ |
| 941 | ␉␉msg_cerr("Block protection could not be disabled!\n");␊ |
| 942 | ␉␉return 1;␊ |
| 943 | ␉}␊ |
| 944 | ␉return 0;␊ |
| 945 | }␊ |
| 946 | ␊ |
| 947 | int spi_nbyte_read(struct flashctx *flash, unsigned int address, uint8_t *bytes,␊ |
| 948 | ␉␉ unsigned int len)␊ |
| 949 | {␊ |
| 950 | ␉const unsigned char cmd[JEDEC_READ_OUTSIZE] = {␊ |
| 951 | ␉␉JEDEC_READ,␊ |
| 952 | ␉␉(address >> 16) & 0xff,␊ |
| 953 | ␉␉(address >> 8) & 0xff,␊ |
| 954 | ␉␉(address >> 0) & 0xff,␊ |
| 955 | ␉};␊ |
| 956 | ␊ |
| 957 | ␉/* Send Read */␊ |
| 958 | ␉return spi_send_command(flash, sizeof(cmd), len, cmd, bytes);␊ |
| 959 | }␊ |
| 960 | ␊ |
| 961 | /*␊ |
| 962 | * Read a part of the flash chip.␊ |
| 963 | * FIXME: Use the chunk code from Michael Karcher instead.␊ |
| 964 | * Each page is read separately in chunks with a maximum size of chunksize.␊ |
| 965 | */␊ |
| 966 | int spi_read_chunked(struct flashctx *flash, uint8_t *buf, unsigned int start,␊ |
| 967 | ␉␉ unsigned int len, unsigned int chunksize)␊ |
| 968 | {␊ |
| 969 | ␉int rc = 0;␊ |
| 970 | ␉unsigned int i, j, starthere, lenhere, toread;␊ |
| 971 | ␉unsigned int page_size = flash->page_size;␊ |
| 972 | ␊ |
| 973 | ␉/* Warning: This loop has a very unusual condition and body.␊ |
| 974 | ␉ * The loop needs to go through each page with at least one affected␊ |
| 975 | ␉ * byte. The lowest page number is (start / page_size) since that␊ |
| 976 | ␉ * division rounds down. The highest page number we want is the page␊ |
| 977 | ␉ * where the last byte of the range lives. That last byte has the␊ |
| 978 | ␉ * address (start + len - 1), thus the highest page number is␊ |
| 979 | ␉ * (start + len - 1) / page_size. Since we want to include that last␊ |
| 980 | ␉ * page as well, the loop condition uses <=.␊ |
| 981 | ␉ */␊ |
| 982 | ␉for (i = start / page_size; i <= (start + len - 1) / page_size; i++) {␊ |
| 983 | ␉␉/* Byte position of the first byte in the range in this page. */␊ |
| 984 | ␉␉/* starthere is an offset to the base address of the chip. */␊ |
| 985 | ␉␉starthere = max(start, i * page_size);␊ |
| 986 | ␉␉/* Length of bytes in the range in this page. */␊ |
| 987 | ␉␉lenhere = min(start + len, (i + 1) * page_size) - starthere;␊ |
| 988 | ␉␉for (j = 0; j < lenhere; j += chunksize) {␊ |
| 989 | ␉␉␉toread = min(chunksize, lenhere - j);␊ |
| 990 | ␉␉␉rc = spi_nbyte_read(flash, starthere + j, buf + starthere - start + j, toread);␊ |
| 991 | ␉␉␉if (rc)␊ |
| 992 | ␉␉␉␉break;␊ |
| 993 | ␉␉}␊ |
| 994 | ␉␉if (rc)␊ |
| 995 | ␉␉␉break;␊ |
| 996 | ␉}␊ |
| 997 | ␊ |
| 998 | ␉return rc;␊ |
| 999 | }␊ |
| 1000 | ␊ |
| 1001 | /*␊ |
| 1002 | * Write a part of the flash chip.␊ |
| 1003 | * FIXME: Use the chunk code from Michael Karcher instead.␊ |
| 1004 | * Each page is written separately in chunks with a maximum size of chunksize.␊ |
| 1005 | */␊ |
| 1006 | int spi_write_chunked(struct flashctx *flash, uint8_t *buf, unsigned int start,␊ |
| 1007 | ␉␉ unsigned int len, unsigned int chunksize)␊ |
| 1008 | {␊ |
| 1009 | ␉int rc = 0;␊ |
| 1010 | ␉unsigned int i, j, starthere, lenhere, towrite;␊ |
| 1011 | ␉/* FIXME: page_size is the wrong variable. We need max_writechunk_size␊ |
| 1012 | ␉ * in struct flashctx to do this properly. All chips using␊ |
| 1013 | ␉ * spi_chip_write_256 have page_size set to max_writechunk_size, so␊ |
| 1014 | ␉ * we're OK for now.␊ |
| 1015 | ␉ */␊ |
| 1016 | ␉unsigned int page_size = flash->page_size;␊ |
| 1017 | ␊ |
| 1018 | ␉/* Warning: This loop has a very unusual condition and body.␊ |
| 1019 | ␉ * The loop needs to go through each page with at least one affected␊ |
| 1020 | ␉ * byte. The lowest page number is (start / page_size) since that␊ |
| 1021 | ␉ * division rounds down. The highest page number we want is the page␊ |
| 1022 | ␉ * where the last byte of the range lives. That last byte has the␊ |
| 1023 | ␉ * address (start + len - 1), thus the highest page number is␊ |
| 1024 | ␉ * (start + len - 1) / page_size. Since we want to include that last␊ |
| 1025 | ␉ * page as well, the loop condition uses <=.␊ |
| 1026 | ␉ */␊ |
| 1027 | ␉for (i = start / page_size; i <= (start + len - 1) / page_size; i++) {␊ |
| 1028 | ␉␉/* Byte position of the first byte in the range in this page. */␊ |
| 1029 | ␉␉/* starthere is an offset to the base address of the chip. */␊ |
| 1030 | ␉␉starthere = max(start, i * page_size);␊ |
| 1031 | ␉␉/* Length of bytes in the range in this page. */␊ |
| 1032 | ␉␉lenhere = min(start + len, (i + 1) * page_size) - starthere;␊ |
| 1033 | ␉␉for (j = 0; j < lenhere; j += chunksize) {␊ |
| 1034 | ␉␉␉towrite = min(chunksize, lenhere - j);␊ |
| 1035 | ␉␉␉rc = spi_nbyte_program(flash, starthere + j, buf + starthere - start + j, towrite);␊ |
| 1036 | ␉␉␉if (rc)␊ |
| 1037 | ␉␉␉␉break;␊ |
| 1038 | ␉␉␉while (spi_read_status_register(flash) & SPI_SR_WIP)␊ |
| 1039 | ␉␉␉␉programmer_delay(10);␊ |
| 1040 | ␉␉}␊ |
| 1041 | ␉␉if (rc)␊ |
| 1042 | ␉␉␉break;␊ |
| 1043 | ␉}␊ |
| 1044 | ␊ |
| 1045 | ␉return rc;␊ |
| 1046 | }␊ |
| 1047 | ␊ |
| 1048 | /*␊ |
| 1049 | * Program chip using byte programming. (SLOW!)␊ |
| 1050 | * This is for chips which can only handle one byte writes␊ |
| 1051 | * and for chips where memory mapped programming is impossible␊ |
| 1052 | * (e.g. due to size constraints in IT87* for over 512 kB)␊ |
| 1053 | */␊ |
| 1054 | /* real chunksize is 1, logical chunksize is 1 */␊ |
| 1055 | int spi_chip_write_1(struct flashctx *flash, uint8_t *buf, unsigned int start,␊ |
| 1056 | ␉␉ unsigned int len)␊ |
| 1057 | {␊ |
| 1058 | ␉unsigned int i;␊ |
| 1059 | ␉int result = 0;␊ |
| 1060 | ␊ |
| 1061 | ␉for (i = start; i < start + len; i++) {␊ |
| 1062 | ␉␉result = spi_byte_program(flash, i, buf[i - start]);␊ |
| 1063 | ␉␉if (result)␊ |
| 1064 | ␉␉␉return 1;␊ |
| 1065 | ␉␉while (spi_read_status_register(flash) & SPI_SR_WIP)␊ |
| 1066 | ␉␉␉programmer_delay(10);␊ |
| 1067 | ␉}␊ |
| 1068 | ␊ |
| 1069 | ␉return 0;␊ |
| 1070 | }␊ |
| 1071 | ␊ |
| 1072 | int spi_aai_write(struct flashctx *flash, uint8_t *buf, unsigned int start,␊ |
| 1073 | ␉␉ unsigned int len)␊ |
| 1074 | {␊ |
| 1075 | ␉uint32_t pos = start;␊ |
| 1076 | ␉int result;␊ |
| 1077 | ␉unsigned char cmd[JEDEC_AAI_WORD_PROGRAM_CONT_OUTSIZE] = {␊ |
| 1078 | ␉␉JEDEC_AAI_WORD_PROGRAM,␊ |
| 1079 | ␉};␊ |
| 1080 | ␉struct spi_command cmds[] = {␊ |
| 1081 | ␉{␊ |
| 1082 | ␉␉.writecnt␉= JEDEC_WREN_OUTSIZE,␊ |
| 1083 | ␉␉.writearr␉= (const unsigned char[]){ JEDEC_WREN },␊ |
| 1084 | ␉␉.readcnt␉= 0,␊ |
| 1085 | ␉␉.readarr␉= NULL,␊ |
| 1086 | ␉}, {␊ |
| 1087 | ␉␉.writecnt␉= JEDEC_AAI_WORD_PROGRAM_OUTSIZE,␊ |
| 1088 | ␉␉.writearr␉= (const unsigned char[]){␊ |
| 1089 | ␉␉␉␉␉JEDEC_AAI_WORD_PROGRAM,␊ |
| 1090 | ␉␉␉␉␉(start >> 16) & 0xff,␊ |
| 1091 | ␉␉␉␉␉(start >> 8) & 0xff,␊ |
| 1092 | ␉␉␉␉␉(start & 0xff),␊ |
| 1093 | ␉␉␉␉␉buf[0],␊ |
| 1094 | ␉␉␉␉␉buf[1]␊ |
| 1095 | ␉␉␉␉},␊ |
| 1096 | ␉␉.readcnt␉= 0,␊ |
| 1097 | ␉␉.readarr␉= NULL,␊ |
| 1098 | ␉}, {␊ |
| 1099 | ␉␉.writecnt␉= 0,␊ |
| 1100 | ␉␉.writearr␉= NULL,␊ |
| 1101 | ␉␉.readcnt␉= 0,␊ |
| 1102 | ␉␉.readarr␉= NULL,␊ |
| 1103 | ␉}};␊ |
| 1104 | ␊ |
| 1105 | ␉switch (flash->pgm->spi.type) {␊ |
| 1106 | #if CONFIG_INTERNAL == 1␊ |
| 1107 | #if defined(__i386__) || defined(__x86_64__)␊ |
| 1108 | ␉case SPI_CONTROLLER_IT87XX:␊ |
| 1109 | ␉case SPI_CONTROLLER_WBSIO:␊ |
| 1110 | ␉␉msg_perr("%s: impossible with this SPI controller,"␊ |
| 1111 | ␉␉␉␉" degrading to byte program\n", __func__);␊ |
| 1112 | ␉␉return spi_chip_write_1(flash, buf, start, len);␊ |
| 1113 | #endif␊ |
| 1114 | #endif␊ |
| 1115 | ␉default:␊ |
| 1116 | ␉␉break;␊ |
| 1117 | ␉}␊ |
| 1118 | ␊ |
| 1119 | ␉/* The even start address and even length requirements can be either␊ |
| 1120 | ␉ * honored outside this function, or we can call spi_byte_program␊ |
| 1121 | ␉ * for the first and/or last byte and use AAI for the rest.␊ |
| 1122 | ␉ * FIXME: Move this to generic code.␊ |
| 1123 | ␉ */␊ |
| 1124 | ␉/* The data sheet requires a start address with the low bit cleared. */␊ |
| 1125 | ␉if (start % 2) {␊ |
| 1126 | ␉␉msg_cerr("%s: start address not even! Please report a bug at "␊ |
| 1127 | ␉␉␉ "flashrom@flashrom.org\n", __func__);␊ |
| 1128 | ␉␉if (spi_chip_write_1(flash, buf, start, start % 2))␊ |
| 1129 | ␉␉␉return SPI_GENERIC_ERROR;␊ |
| 1130 | ␉␉pos += start % 2;␊ |
| 1131 | ␉␉cmds[1].writearr = (const unsigned char[]){␊ |
| 1132 | ␉␉␉␉␉JEDEC_AAI_WORD_PROGRAM,␊ |
| 1133 | ␉␉␉␉␉(pos >> 16) & 0xff,␊ |
| 1134 | ␉␉␉␉␉(pos >> 8) & 0xff,␊ |
| 1135 | ␉␉␉␉␉(pos & 0xff),␊ |
| 1136 | ␉␉␉␉␉buf[pos - start],␊ |
| 1137 | ␉␉␉␉␉buf[pos - start + 1]␊ |
| 1138 | ␉␉␉␉};␊ |
| 1139 | ␉␉/* Do not return an error for now. */␊ |
| 1140 | ␉␉//return SPI_GENERIC_ERROR;␊ |
| 1141 | ␉}␊ |
| 1142 | ␉/* The data sheet requires total AAI write length to be even. */␊ |
| 1143 | ␉if (len % 2) {␊ |
| 1144 | ␉␉msg_cerr("%s: total write length not even! Please report a "␊ |
| 1145 | ␉␉␉ "bug at flashrom@flashrom.org\n", __func__);␊ |
| 1146 | ␉␉/* Do not return an error for now. */␊ |
| 1147 | ␉␉//return SPI_GENERIC_ERROR;␊ |
| 1148 | ␉}␊ |
| 1149 | ␊ |
| 1150 | ␊ |
| 1151 | ␉result = spi_send_multicommand(flash, cmds);␊ |
| 1152 | ␉if (result) {␊ |
| 1153 | ␉␉msg_cerr("%s failed during start command execution\n",␊ |
| 1154 | ␉␉␉ __func__);␊ |
| 1155 | ␉␉/* FIXME: Should we send WRDI here as well to make sure the chip␊ |
| 1156 | ␉␉ * is not in AAI mode?␊ |
| 1157 | ␉␉ */␊ |
| 1158 | ␉␉return result;␊ |
| 1159 | ␉}␊ |
| 1160 | ␉while (spi_read_status_register(flash) & SPI_SR_WIP)␊ |
| 1161 | ␉␉programmer_delay(10);␊ |
| 1162 | ␊ |
| 1163 | ␉/* We already wrote 2 bytes in the multicommand step. */␊ |
| 1164 | ␉pos += 2;␊ |
| 1165 | ␊ |
| 1166 | ␉/* Are there at least two more bytes to write? */␊ |
| 1167 | ␉while (pos < start + len - 1) {␊ |
| 1168 | ␉␉cmd[1] = buf[pos++ - start];␊ |
| 1169 | ␉␉cmd[2] = buf[pos++ - start];␊ |
| 1170 | ␉␉spi_send_command(flash, JEDEC_AAI_WORD_PROGRAM_CONT_OUTSIZE, 0,␊ |
| 1171 | ␉␉␉␉ cmd, NULL);␊ |
| 1172 | ␉␉while (spi_read_status_register(flash) & SPI_SR_WIP)␊ |
| 1173 | ␉␉␉programmer_delay(10);␊ |
| 1174 | ␉}␊ |
| 1175 | ␊ |
| 1176 | ␉/* Use WRDI to exit AAI mode. This needs to be done before issuing any␊ |
| 1177 | ␉ * other non-AAI command.␊ |
| 1178 | ␉ */␊ |
| 1179 | ␉spi_write_disable(flash);␊ |
| 1180 | ␊ |
| 1181 | ␉/* Write remaining byte (if any). */␊ |
| 1182 | ␉if (pos < start + len) {␊ |
| 1183 | ␉␉if (spi_chip_write_1(flash, buf + pos - start, pos, pos % 2))␊ |
| 1184 | ␉␉␉return SPI_GENERIC_ERROR;␊ |
| 1185 | ␉␉pos += pos % 2;␊ |
| 1186 | ␉}␊ |
| 1187 | ␊ |
| 1188 | ␉return 0;␊ |
| 1189 | }␊ |
| 1190 | |
