| 1 | /*␊ |
| 2 | * This file is part of the flashrom project.␊ |
| 3 | *␊ |
| 4 | * Copyright (C) 2009 Rudolf Marek <r.marek@assembler.cz>␊ |
| 5 | *␊ |
| 6 | * This program is free software; you can redistribute it and/or modify␊ |
| 7 | * it under the terms of the GNU General Public License as published by␊ |
| 8 | * the Free Software Foundation; either version 2 of the License, or␊ |
| 9 | * (at your option) any later version.␊ |
| 10 | *␊ |
| 11 | * This program is distributed in the hope that it will be useful,␊ |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of␊ |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the␊ |
| 14 | * GNU General Public License for more details.␊ |
| 15 | *␊ |
| 16 | * You should have received a copy of the GNU General Public License␊ |
| 17 | * along with this program; if not, write to the Free Software␊ |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA␊ |
| 19 | */␊ |
| 20 | ␊ |
| 21 | /* Datasheets can be found on http://www.siliconimage.com. Great thanks! */␊ |
| 22 | ␊ |
| 23 | #include <stdlib.h>␊ |
| 24 | #include "flash.h"␊ |
| 25 | #include "programmer.h"␊ |
| 26 | ␊ |
| 27 | #define PCI_VENDOR_ID_SII␉0x1095␊ |
| 28 | ␊ |
| 29 | #define SATASII_MEMMAP_SIZE␉0x100␊ |
| 30 | ␊ |
| 31 | uint8_t *sii_bar;␊ |
| 32 | static uint16_t id;␊ |
| 33 | ␊ |
| 34 | const struct pcidev_status satas_sii[] = {␊ |
| 35 | ␉{0x1095, 0x0680, OK, "Silicon Image", "PCI0680 Ultra ATA-133 Host Ctrl"},␊ |
| 36 | ␉{0x1095, 0x3112, OK, "Silicon Image", "SiI 3112 [SATALink/SATARaid] SATA Ctrl"},␊ |
| 37 | ␉{0x1095, 0x3114, OK, "Silicon Image", "SiI 3114 [SATALink/SATARaid] SATA Ctrl"},␊ |
| 38 | ␉{0x1095, 0x3124, OK, "Silicon Image", "SiI 3124 PCI-X SATA Ctrl"},␊ |
| 39 | ␉{0x1095, 0x3132, OK, "Silicon Image", "SiI 3132 SATA Raid II Ctrl"},␊ |
| 40 | ␉{0x1095, 0x3512, OK, "Silicon Image", "SiI 3512 [SATALink/SATARaid] SATA Ctrl"},␊ |
| 41 | ␊ |
| 42 | ␉{},␊ |
| 43 | };␊ |
| 44 | ␊ |
| 45 | static void satasii_chip_writeb(const struct flashctx *flash, uint8_t val,␊ |
| 46 | ␉␉␉␉chipaddr addr);␊ |
| 47 | static uint8_t satasii_chip_readb(const struct flashctx *flash,␊ |
| 48 | ␉␉␉␉ const chipaddr addr);␊ |
| 49 | static const struct par_programmer par_programmer_satasii = {␊ |
| 50 | ␉␉.chip_readb␉␉= satasii_chip_readb,␊ |
| 51 | ␉␉.chip_readw␉␉= fallback_chip_readw,␊ |
| 52 | ␉␉.chip_readl␉␉= fallback_chip_readl,␊ |
| 53 | ␉␉.chip_readn␉␉= fallback_chip_readn,␊ |
| 54 | ␉␉.chip_writeb␉␉= satasii_chip_writeb,␊ |
| 55 | ␉␉.chip_writew␉␉= fallback_chip_writew,␊ |
| 56 | ␉␉.chip_writel␉␉= fallback_chip_writel,␊ |
| 57 | ␉␉.chip_writen␉␉= fallback_chip_writen,␊ |
| 58 | };␊ |
| 59 | ␊ |
| 60 | static int satasii_shutdown(void *data)␊ |
| 61 | {␊ |
| 62 | ␉physunmap(sii_bar, SATASII_MEMMAP_SIZE);␊ |
| 63 | ␉pci_cleanup(pacc);␊ |
| 64 | ␉release_io_perms();␊ |
| 65 | ␉return 0;␊ |
| 66 | }␊ |
| 67 | ␊ |
| 68 | int satasii_init(void)␊ |
| 69 | {␊ |
| 70 | ␉uint32_t addr;␊ |
| 71 | ␉uint16_t reg_offset;␊ |
| 72 | ␊ |
| 73 | ␉get_io_perms();␊ |
| 74 | ␊ |
| 75 | ␉pcidev_init(PCI_BASE_ADDRESS_0, satas_sii);␊ |
| 76 | ␊ |
| 77 | ␉id = pcidev_dev->device_id;␊ |
| 78 | ␊ |
| 79 | ␉if ((id == 0x3132) || (id == 0x3124)) {␊ |
| 80 | ␉␉addr = pci_read_long(pcidev_dev, PCI_BASE_ADDRESS_0) & ~0x07;␊ |
| 81 | ␉␉reg_offset = 0x70;␊ |
| 82 | ␉} else {␊ |
| 83 | ␉␉addr = pci_read_long(pcidev_dev, PCI_BASE_ADDRESS_5) & ~0x07;␊ |
| 84 | ␉␉reg_offset = 0x50;␊ |
| 85 | ␉}␊ |
| 86 | ␊ |
| 87 | ␉sii_bar = physmap("SATA SIL registers", addr, SATASII_MEMMAP_SIZE) +␊ |
| 88 | ␉␉ reg_offset;␊ |
| 89 | ␊ |
| 90 | ␉/* Check if ROM cycle are OK. */␊ |
| 91 | ␉if ((id != 0x0680) && (!(pci_mmio_readl(sii_bar) & (1 << 26))))␊ |
| 92 | ␉␉msg_pinfo("Warning: Flash seems unconnected.\n");␊ |
| 93 | ␊ |
| 94 | ␉if (register_shutdown(satasii_shutdown, NULL))␊ |
| 95 | ␉␉return 1;␊ |
| 96 | ␊ |
| 97 | ␉register_par_programmer(&par_programmer_satasii, BUS_PARALLEL);␊ |
| 98 | ␊ |
| 99 | ␉return 0;␊ |
| 100 | }␊ |
| 101 | ␊ |
| 102 | static void satasii_chip_writeb(const struct flashctx *flash, uint8_t val,␊ |
| 103 | ␉␉␉␉chipaddr addr)␊ |
| 104 | {␊ |
| 105 | ␉uint32_t ctrl_reg, data_reg;␊ |
| 106 | ␊ |
| 107 | ␉while ((ctrl_reg = pci_mmio_readl(sii_bar)) & (1 << 25)) ;␊ |
| 108 | ␊ |
| 109 | ␉/* Mask out unused/reserved bits, set writes and start transaction. */␊ |
| 110 | ␉ctrl_reg &= 0xfcf80000;␊ |
| 111 | ␉ctrl_reg |= (1 << 25) | (0 << 24) | ((uint32_t) addr & 0x7ffff);␊ |
| 112 | ␊ |
| 113 | ␉data_reg = (pci_mmio_readl((sii_bar + 4)) & ~0xff) | val;␊ |
| 114 | ␉pci_mmio_writel(data_reg, (sii_bar + 4));␊ |
| 115 | ␉pci_mmio_writel(ctrl_reg, sii_bar);␊ |
| 116 | ␊ |
| 117 | ␉while (pci_mmio_readl(sii_bar) & (1 << 25)) ;␊ |
| 118 | }␊ |
| 119 | ␊ |
| 120 | static uint8_t satasii_chip_readb(const struct flashctx *flash,␊ |
| 121 | ␉␉␉␉ const chipaddr addr)␊ |
| 122 | {␊ |
| 123 | ␉uint32_t ctrl_reg;␊ |
| 124 | ␊ |
| 125 | ␉while ((ctrl_reg = pci_mmio_readl(sii_bar)) & (1 << 25)) ;␊ |
| 126 | ␊ |
| 127 | ␉/* Mask out unused/reserved bits, set reads and start transaction. */␊ |
| 128 | ␉ctrl_reg &= 0xfcf80000;␊ |
| 129 | ␉ctrl_reg |= (1 << 25) | (1 << 24) | ((uint32_t) addr & 0x7ffff);␊ |
| 130 | ␊ |
| 131 | ␉pci_mmio_writel(ctrl_reg, sii_bar);␊ |
| 132 | ␊ |
| 133 | ␉while (pci_mmio_readl(sii_bar) & (1 << 25)) ;␊ |
| 134 | ␊ |
| 135 | ␉return (pci_mmio_readl(sii_bar + 4)) & 0xff;␊ |
| 136 | }␊ |
| 137 | |
