| 1 | /*␊ |
| 2 | * This file is part of the flashrom project.␊ |
| 3 | *␊ |
| 4 | * Copyright (C) 2010,2011 Carl-Daniel Hailfinger␊ |
| 5 | * Written by Carl-Daniel Hailfinger for Angelbird Ltd.␊ |
| 6 | *␊ |
| 7 | * This program is free software; you can redistribute it and/or modify␊ |
| 8 | * it under the terms of the GNU General Public License as published by␊ |
| 9 | * the Free Software Foundation; version 2 of the License.␊ |
| 10 | *␊ |
| 11 | * This program is distributed in the hope that it will be useful,␊ |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of␊ |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the␊ |
| 14 | * GNU General Public License for more details.␊ |
| 15 | *␊ |
| 16 | * You should have received a copy of the GNU General Public License␊ |
| 17 | * along with this program; if not, write to the Free Software␊ |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA␊ |
| 19 | */␊ |
| 20 | ␊ |
| 21 | /* Datasheets are not public (yet?) */␊ |
| 22 | #if defined(__i386__) || defined(__x86_64__)␊ |
| 23 | ␊ |
| 24 | #include <stdlib.h>␊ |
| 25 | #include "flash.h"␊ |
| 26 | #include "programmer.h"␊ |
| 27 | ␊ |
| 28 | uint8_t *mv_bar;␊ |
| 29 | uint16_t mv_iobar;␊ |
| 30 | ␊ |
| 31 | const struct pcidev_status satas_mv[] = {␊ |
| 32 | ␉/* 88SX6041 and 88SX6042 are the same according to the datasheet. */␊ |
| 33 | ␉{0x11ab, 0x7042, OK, "Marvell", "88SX7042 PCI-e 4-port SATA-II"},␊ |
| 34 | ␊ |
| 35 | ␉{},␊ |
| 36 | };␊ |
| 37 | ␊ |
| 38 | #define NVRAM_PARAM␉␉␉0x1045c␊ |
| 39 | #define FLASH_PARAM␉␉␉0x1046c␊ |
| 40 | #define EXPANSION_ROM_BAR_CONTROL␉0x00d2c␊ |
| 41 | #define PCI_BAR2_CONTROL␉␉0x00c08␊ |
| 42 | #define GPIO_PORT_CONTROL␉␉0x104f0␊ |
| 43 | ␊ |
| 44 | static void satamv_chip_writeb(const struct flashctx *flash, uint8_t val,␊ |
| 45 | ␉␉␉ chipaddr addr);␊ |
| 46 | static uint8_t satamv_chip_readb(const struct flashctx *flash,␊ |
| 47 | ␉␉␉␉ const chipaddr addr);␊ |
| 48 | static const struct par_programmer par_programmer_satamv = {␊ |
| 49 | ␉␉.chip_readb␉␉= satamv_chip_readb,␊ |
| 50 | ␉␉.chip_readw␉␉= fallback_chip_readw,␊ |
| 51 | ␉␉.chip_readl␉␉= fallback_chip_readl,␊ |
| 52 | ␉␉.chip_readn␉␉= fallback_chip_readn,␊ |
| 53 | ␉␉.chip_writeb␉␉= satamv_chip_writeb,␊ |
| 54 | ␉␉.chip_writew␉␉= fallback_chip_writew,␊ |
| 55 | ␉␉.chip_writel␉␉= fallback_chip_writel,␊ |
| 56 | ␉␉.chip_writen␉␉= fallback_chip_writen,␊ |
| 57 | };␊ |
| 58 | ␊ |
| 59 | static int satamv_shutdown(void *data)␊ |
| 60 | {␊ |
| 61 | ␉physunmap(mv_bar, 0x20000);␊ |
| 62 | ␉pci_cleanup(pacc);␊ |
| 63 | ␉release_io_perms();␊ |
| 64 | ␉return 0;␊ |
| 65 | }␊ |
| 66 | ␊ |
| 67 | /*␊ |
| 68 | * Random notes:␊ |
| 69 | * FCE#␉␉Flash Chip Enable␊ |
| 70 | * FWE#␉␉Flash Write Enable␊ |
| 71 | * FOE#␉␉Flash Output Enable␊ |
| 72 | * FALE[1:0]␉Flash Address Latch Enable␊ |
| 73 | * FAD[7:0]␉Flash Multiplexed Address/Data Bus␊ |
| 74 | * FA[2:0]␉Flash Address Low␊ |
| 75 | *␊ |
| 76 | * GPIO[15,2]␉GPIO Port Mode␊ |
| 77 | * GPIO[4:3]␉Flash Size␊ |
| 78 | *␊ |
| 79 | * 0xd2c␉Expansion ROM BAR Control␊ |
| 80 | * 0xc08␉PCI BAR2 (Flash/NVRAM) Control␊ |
| 81 | * 0x1046c␉Flash Parameters␊ |
| 82 | */␊ |
| 83 | int satamv_init(void)␊ |
| 84 | {␊ |
| 85 | ␉uintptr_t addr;␊ |
| 86 | ␉uint32_t tmp;␊ |
| 87 | ␊ |
| 88 | ␉get_io_perms();␊ |
| 89 | ␊ |
| 90 | ␉/* BAR0 has all internal registers memory mapped. */␊ |
| 91 | ␉/* No need to check for errors, pcidev_init() will not return in case␊ |
| 92 | ␉ * of errors.␊ |
| 93 | ␉ */␊ |
| 94 | ␉addr = pcidev_init(PCI_BASE_ADDRESS_0, satas_mv);␊ |
| 95 | ␊ |
| 96 | ␉mv_bar = physmap("Marvell 88SX7042 registers", addr, 0x20000);␊ |
| 97 | ␉if (mv_bar == ERROR_PTR)␊ |
| 98 | ␉␉goto error_out;␊ |
| 99 | ␊ |
| 100 | ␉if (register_shutdown(satamv_shutdown, NULL))␊ |
| 101 | ␉␉return 1;␊ |
| 102 | ␊ |
| 103 | ␉tmp = pci_mmio_readl(mv_bar + FLASH_PARAM);␊ |
| 104 | ␉msg_pspew("Flash Parameters:\n");␊ |
| 105 | ␉msg_pspew("TurnOff=0x%01x\n", (tmp >> 0) & 0x7);␊ |
| 106 | ␉msg_pspew("Acc2First=0x%01x\n", (tmp >> 3) & 0xf);␊ |
| 107 | ␉msg_pspew("Acc2Next=0x%01x\n", (tmp >> 7) & 0xf);␊ |
| 108 | ␉msg_pspew("ALE2Wr=0x%01x\n", (tmp >> 11) & 0x7);␊ |
| 109 | ␉msg_pspew("WrLow=0x%01x\n", (tmp >> 14) & 0x7);␊ |
| 110 | ␉msg_pspew("WrHigh=0x%01x\n", (tmp >> 17) & 0x7);␊ |
| 111 | ␉msg_pspew("Reserved[21:20]=0x%01x\n", (tmp >> 20) & 0x3);␊ |
| 112 | ␉msg_pspew("TurnOffExt=0x%01x\n", (tmp >> 22) & 0x1);␊ |
| 113 | ␉msg_pspew("Acc2FirstExt=0x%01x\n", (tmp >> 23) & 0x1);␊ |
| 114 | ␉msg_pspew("Acc2NextExt=0x%01x\n", (tmp >> 24) & 0x1);␊ |
| 115 | ␉msg_pspew("ALE2WrExt=0x%01x\n", (tmp >> 25) & 0x1);␊ |
| 116 | ␉msg_pspew("WrLowExt=0x%01x\n", (tmp >> 26) & 0x1);␊ |
| 117 | ␉msg_pspew("WrHighExt=0x%01x\n", (tmp >> 27) & 0x1);␊ |
| 118 | ␉msg_pspew("Reserved[31:28]=0x%01x\n", (tmp >> 28) & 0xf);␊ |
| 119 | ␊ |
| 120 | ␉tmp = pci_mmio_readl(mv_bar + EXPANSION_ROM_BAR_CONTROL);␊ |
| 121 | ␉msg_pspew("Expansion ROM BAR Control:\n");␊ |
| 122 | ␉msg_pspew("ExpROMSz=0x%01x\n", (tmp >> 19) & 0x7);␊ |
| 123 | ␊ |
| 124 | ␉/* Enable BAR2 mapping to flash */␊ |
| 125 | ␉tmp = pci_mmio_readl(mv_bar + PCI_BAR2_CONTROL);␊ |
| 126 | ␉msg_pspew("PCI BAR2 (Flash/NVRAM) Control:\n");␊ |
| 127 | ␉msg_pspew("Bar2En=0x%01x\n", (tmp >> 0) & 0x1);␊ |
| 128 | ␉msg_pspew("BAR2TransAttr=0x%01x\n", (tmp >> 1) & 0x1f);␊ |
| 129 | ␉msg_pspew("BAR2Sz=0x%01x\n", (tmp >> 19) & 0x7);␊ |
| 130 | ␉tmp &= 0xffffffc0;␊ |
| 131 | ␉tmp |= 0x0000001f;␊ |
| 132 | ␉pci_rmmio_writel(tmp, mv_bar + PCI_BAR2_CONTROL);␊ |
| 133 | ␊ |
| 134 | ␉/* Enable flash: GPIO Port Control Register 0x104f0 */␊ |
| 135 | ␉tmp = pci_mmio_readl(mv_bar + GPIO_PORT_CONTROL);␊ |
| 136 | ␉msg_pspew("GPIOPortMode=0x%01x\n", (tmp >> 0) & 0x3);␊ |
| 137 | ␉if (((tmp >> 0) & 0x3) != 0x2)␊ |
| 138 | ␉␉msg_pinfo("Warning! Either the straps are incorrect or you "␊ |
| 139 | ␉␉␉ "have no flash or someone overwrote the strap "␊ |
| 140 | ␉␉␉ "values!\n");␊ |
| 141 | ␉tmp &= 0xfffffffc;␊ |
| 142 | ␉tmp |= 0x2;␊ |
| 143 | ␉pci_rmmio_writel(tmp, mv_bar + GPIO_PORT_CONTROL);␊ |
| 144 | ␊ |
| 145 | ␉/* Get I/O BAR location. */␊ |
| 146 | ␉tmp = pci_read_long(pcidev_dev, PCI_BASE_ADDRESS_2) &␊ |
| 147 | ␉ PCI_BASE_ADDRESS_IO_MASK;␊ |
| 148 | ␉/* Truncate to reachable range.␊ |
| 149 | ␉ * FIXME: Check if the I/O BAR is actually reachable.␊ |
| 150 | ␉ * This is an arch specific check.␊ |
| 151 | ␉ */␊ |
| 152 | ␉mv_iobar = tmp & 0xffff;␊ |
| 153 | ␉msg_pspew("Activating I/O BAR at 0x%04x\n", mv_iobar);␊ |
| 154 | ␊ |
| 155 | ␉/* 512 kByte with two 8-bit latches, and␊ |
| 156 | ␉ * 4 MByte with additional 3-bit latch. */␊ |
| 157 | ␉max_rom_decode.parallel = 4 * 1024 * 1024;␊ |
| 158 | ␉register_par_programmer(&par_programmer_satamv, BUS_PARALLEL);␊ |
| 159 | ␊ |
| 160 | ␉return 0;␊ |
| 161 | ␊ |
| 162 | error_out:␊ |
| 163 | ␉pci_cleanup(pacc);␊ |
| 164 | ␉release_io_perms();␊ |
| 165 | ␉return 1;␊ |
| 166 | }␊ |
| 167 | ␊ |
| 168 | /* BAR2 (MEM) can map NVRAM and flash. We set it to flash in the init function.␊ |
| 169 | * If BAR2 is disabled, it still can be accessed indirectly via BAR1 (I/O).␊ |
| 170 | * This code only supports indirect accesses for now.␊ |
| 171 | */␊ |
| 172 | ␊ |
| 173 | /* Indirect access to via the I/O BAR1. */␊ |
| 174 | static void satamv_indirect_chip_writeb(uint8_t val, chipaddr addr)␊ |
| 175 | {␊ |
| 176 | ␉/* 0x80000000 selects BAR2 for remapping. */␊ |
| 177 | ␉OUTL(((uint32_t)addr | 0x80000000) & 0xfffffffc, mv_iobar);␊ |
| 178 | ␉OUTB(val, mv_iobar + 0x80 + (addr & 0x3));␊ |
| 179 | }␊ |
| 180 | ␊ |
| 181 | /* Indirect access to via the I/O BAR1. */␊ |
| 182 | static uint8_t satamv_indirect_chip_readb(const chipaddr addr)␊ |
| 183 | {␊ |
| 184 | ␉/* 0x80000000 selects BAR2 for remapping. */␊ |
| 185 | ␉OUTL(((uint32_t)addr | 0x80000000) & 0xfffffffc, mv_iobar);␊ |
| 186 | ␉return INB(mv_iobar + 0x80 + (addr & 0x3));␊ |
| 187 | }␊ |
| 188 | ␊ |
| 189 | /* FIXME: Prefer direct access to BAR2 if BAR2 is active. */␊ |
| 190 | static void satamv_chip_writeb(const struct flashctx *flash, uint8_t val,␊ |
| 191 | ␉␉␉ chipaddr addr)␊ |
| 192 | {␊ |
| 193 | ␉satamv_indirect_chip_writeb(val, addr);␊ |
| 194 | }␊ |
| 195 | ␊ |
| 196 | /* FIXME: Prefer direct access to BAR2 if BAR2 is active. */␊ |
| 197 | static uint8_t satamv_chip_readb(const struct flashctx *flash,␊ |
| 198 | ␉␉␉␉ const chipaddr addr)␊ |
| 199 | {␊ |
| 200 | ␉return satamv_indirect_chip_readb(addr);␊ |
| 201 | }␊ |
| 202 | ␊ |
| 203 | #else␊ |
| 204 | #error PCI port I/O access is not supported on this architecture yet.␊ |
| 205 | #endif␊ |
| 206 | |
