| 1 | /*␊ |
| 2 | * This file is part of the flashrom project.␊ |
| 3 | *␊ |
| 4 | * Copyright (C) 2009,2010 Carl-Daniel Hailfinger␊ |
| 5 | *␊ |
| 6 | * This program is free software; you can redistribute it and/or modify␊ |
| 7 | * it under the terms of the GNU General Public License as published by␊ |
| 8 | * the Free Software Foundation; version 2 of the License.␊ |
| 9 | *␊ |
| 10 | * This program is distributed in the hope that it will be useful,␊ |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of␊ |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the␊ |
| 13 | * GNU General Public License for more details.␊ |
| 14 | *␊ |
| 15 | * You should have received a copy of the GNU General Public License␊ |
| 16 | * along with this program; if not, write to the Free Software␊ |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA␊ |
| 18 | */␊ |
| 19 | ␊ |
| 20 | /* Driver for the SPIPGM hardware by "RayeR" Martin Rehak.␊ |
| 21 | * See http://rayer.ic.cz/elektro/spipgm.htm for schematics and instructions.␊ |
| 22 | */␊ |
| 23 | ␊ |
| 24 | /* This driver uses non-portable direct I/O port accesses which won't work on␊ |
| 25 | * any non-x86 platform, and even on x86 there is a high chance there will be␊ |
| 26 | * collisions with any loaded parallel port drivers.␊ |
| 27 | * The big advantage of direct port I/O is OS independence and speed because␊ |
| 28 | * most OS parport drivers will perform many unnecessary accesses although␊ |
| 29 | * this driver just treats the parallel port as a GPIO set.␊ |
| 30 | */␊ |
| 31 | #if defined(__i386__) || defined(__x86_64__)␊ |
| 32 | ␊ |
| 33 | #include <stdlib.h>␊ |
| 34 | #include <string.h>␊ |
| 35 | #include "flash.h"␊ |
| 36 | #include "programmer.h"␊ |
| 37 | ␊ |
| 38 | enum rayer_type {␊ |
| 39 | ␉TYPE_RAYER,␊ |
| 40 | ␉TYPE_XILINX_DLC5,␊ |
| 41 | };␊ |
| 42 | ␊ |
| 43 | /* We have two sets of pins, out and in. The numbers for both sets are␊ |
| 44 | * independent and are bitshift values, not real pin numbers.␊ |
| 45 | * Default settings are for the RayeR hardware.␊ |
| 46 | */␊ |
| 47 | /* Pins for master->slave direction */␊ |
| 48 | static int rayer_cs_bit = 5;␊ |
| 49 | static int rayer_sck_bit = 6;␊ |
| 50 | static int rayer_mosi_bit = 7;␊ |
| 51 | /* Pins for slave->master direction */␊ |
| 52 | static int rayer_miso_bit = 6;␊ |
| 53 | ␊ |
| 54 | static uint16_t lpt_iobase;␊ |
| 55 | ␊ |
| 56 | /* Cached value of last byte sent. */␊ |
| 57 | static uint8_t lpt_outbyte;␊ |
| 58 | ␊ |
| 59 | static void rayer_bitbang_set_cs(int val)␊ |
| 60 | {␊ |
| 61 | ␉lpt_outbyte &= ~(1 << rayer_cs_bit);␊ |
| 62 | ␉lpt_outbyte |= (val << rayer_cs_bit);␊ |
| 63 | ␉OUTB(lpt_outbyte, lpt_iobase);␊ |
| 64 | }␊ |
| 65 | ␊ |
| 66 | static void rayer_bitbang_set_sck(int val)␊ |
| 67 | {␊ |
| 68 | ␉lpt_outbyte &= ~(1 << rayer_sck_bit);␊ |
| 69 | ␉lpt_outbyte |= (val << rayer_sck_bit);␊ |
| 70 | ␉OUTB(lpt_outbyte, lpt_iobase);␊ |
| 71 | }␊ |
| 72 | ␊ |
| 73 | static void rayer_bitbang_set_mosi(int val)␊ |
| 74 | {␊ |
| 75 | ␉lpt_outbyte &= ~(1 << rayer_mosi_bit);␊ |
| 76 | ␉lpt_outbyte |= (val << rayer_mosi_bit);␊ |
| 77 | ␉OUTB(lpt_outbyte, lpt_iobase);␊ |
| 78 | }␊ |
| 79 | ␊ |
| 80 | static int rayer_bitbang_get_miso(void)␊ |
| 81 | {␊ |
| 82 | ␉uint8_t tmp;␊ |
| 83 | ␊ |
| 84 | ␉tmp = INB(lpt_iobase + 1);␊ |
| 85 | ␉tmp = (tmp >> rayer_miso_bit) & 0x1;␊ |
| 86 | ␉return tmp;␊ |
| 87 | }␊ |
| 88 | ␊ |
| 89 | static const struct bitbang_spi_master bitbang_spi_master_rayer = {␊ |
| 90 | ␉.type = BITBANG_SPI_MASTER_RAYER,␊ |
| 91 | ␉.set_cs = rayer_bitbang_set_cs,␊ |
| 92 | ␉.set_sck = rayer_bitbang_set_sck,␊ |
| 93 | ␉.set_mosi = rayer_bitbang_set_mosi,␊ |
| 94 | ␉.get_miso = rayer_bitbang_get_miso,␊ |
| 95 | ␉.half_period = 0,␊ |
| 96 | };␊ |
| 97 | ␊ |
| 98 | int rayer_spi_init(void)␊ |
| 99 | {␊ |
| 100 | ␉char *arg = NULL;␊ |
| 101 | ␉enum rayer_type rayer_type = TYPE_RAYER;␊ |
| 102 | ␊ |
| 103 | ␉/* Non-default port requested? */␊ |
| 104 | ␉arg = extract_programmer_param("iobase");␊ |
| 105 | ␉if (arg) {␊ |
| 106 | ␉␉char *endptr = NULL;␊ |
| 107 | ␉␉unsigned long tmp;␊ |
| 108 | ␉␉tmp = strtoul(arg, &endptr, 0);␊ |
| 109 | ␉␉/* Port 0, port >0x10000, unaligned ports and garbage strings␊ |
| 110 | ␉␉ * are rejected.␊ |
| 111 | ␉␉ */␊ |
| 112 | ␉␉if (!tmp || (tmp >= 0x10000) || (tmp & 0x3) ||␊ |
| 113 | ␉␉ (*endptr != '\0')) {␊ |
| 114 | ␉␉␉/* Using ports below 0x100 is a really bad idea, and␊ |
| 115 | ␉␉␉ * should only be done if no port between 0x100 and␊ |
| 116 | ␉␉␉ * 0xfffc works due to routing issues.␊ |
| 117 | ␉␉␉ */␊ |
| 118 | ␉␉␉msg_perr("Error: iobase= specified, but the I/O base "␊ |
| 119 | ␉␉␉␉ "given was invalid.\nIt must be a multiple of "␊ |
| 120 | ␉␉␉␉ "0x4 and lie between 0x100 and 0xfffc.\n");␊ |
| 121 | ␉␉␉free(arg);␊ |
| 122 | ␉␉␉return 1;␊ |
| 123 | ␉␉} else {␊ |
| 124 | ␉␉␉lpt_iobase = (uint16_t)tmp;␊ |
| 125 | ␉␉␉msg_pinfo("Non-default I/O base requested. This will "␊ |
| 126 | ␉␉␉␉ "not change the hardware settings.\n");␊ |
| 127 | ␉␉}␊ |
| 128 | ␉} else {␊ |
| 129 | ␉␉/* Pick a default value for the I/O base. */␊ |
| 130 | ␉␉lpt_iobase = 0x378;␊ |
| 131 | ␉}␊ |
| 132 | ␉free(arg);␊ |
| 133 | ␉␊ |
| 134 | ␉msg_pdbg("Using address 0x%x as I/O base for parallel port access.\n",␊ |
| 135 | ␉␉ lpt_iobase);␊ |
| 136 | ␊ |
| 137 | ␉arg = extract_programmer_param("type");␊ |
| 138 | ␉if (arg) {␊ |
| 139 | ␉␉if (!strcasecmp(arg, "rayer")) {␊ |
| 140 | ␉␉␉rayer_type = TYPE_RAYER;␊ |
| 141 | ␉␉} else if (!strcasecmp(arg, "xilinx")) {␊ |
| 142 | ␉␉␉rayer_type = TYPE_XILINX_DLC5;␊ |
| 143 | ␉␉} else {␊ |
| 144 | ␉␉␉msg_perr("Error: Invalid device type specified.\n");␊ |
| 145 | ␉␉␉free(arg);␊ |
| 146 | ␉␉␉return 1;␊ |
| 147 | ␉␉}␊ |
| 148 | ␉}␊ |
| 149 | ␉free(arg);␊ |
| 150 | ␉switch (rayer_type) {␊ |
| 151 | ␉case TYPE_RAYER:␊ |
| 152 | ␉␉msg_pdbg("Using RayeR SPIPGM pinout.\n");␊ |
| 153 | ␉␉/* Bits for master->slave direction */␊ |
| 154 | ␉␉rayer_cs_bit = 5;␊ |
| 155 | ␉␉rayer_sck_bit = 6;␊ |
| 156 | ␉␉rayer_mosi_bit = 7;␊ |
| 157 | ␉␉/* Bits for slave->master direction */␊ |
| 158 | ␉␉rayer_miso_bit = 6;␊ |
| 159 | ␉␉break;␊ |
| 160 | ␉case TYPE_XILINX_DLC5:␊ |
| 161 | ␉␉msg_pdbg("Using Xilinx Parallel Cable III (DLC 5) pinout.\n");␊ |
| 162 | ␉␉/* Bits for master->slave direction */␊ |
| 163 | ␉␉rayer_cs_bit = 2;␊ |
| 164 | ␉␉rayer_sck_bit = 1;␊ |
| 165 | ␉␉rayer_mosi_bit = 0;␊ |
| 166 | ␉␉/* Bits for slave->master direction */␊ |
| 167 | ␉␉rayer_miso_bit = 4;␊ |
| 168 | ␉}␊ |
| 169 | ␊ |
| 170 | ␉get_io_perms();␊ |
| 171 | ␊ |
| 172 | ␉/* Get the initial value before writing to any line. */␊ |
| 173 | ␉lpt_outbyte = INB(lpt_iobase);␊ |
| 174 | ␊ |
| 175 | ␉if (bitbang_spi_init(&bitbang_spi_master_rayer))␊ |
| 176 | ␉␉return 1;␊ |
| 177 | ␊ |
| 178 | ␉return 0;␊ |
| 179 | }␊ |
| 180 | ␊ |
| 181 | #else␊ |
| 182 | #error PCI port I/O access is not supported on this architecture yet.␊ |
| 183 | #endif␊ |
| 184 | |
