| 1 | /*␊ |
| 2 | * This file is part of the flashrom project.␊ |
| 3 | *␊ |
| 4 | * Copyright (C) 2000 Silicon Integrated System Corporation␊ |
| 5 | * Copyright (C) 2000 Ronald G. Minnich <rminnich@gmail.com>␊ |
| 6 | * Copyright (C) 2005-2009 coresystems GmbH␊ |
| 7 | * Copyright (C) 2006-2009 Carl-Daniel Hailfinger␊ |
| 8 | *␊ |
| 9 | * This program is free software; you can redistribute it and/or modify␊ |
| 10 | * it under the terms of the GNU General Public License as published by␊ |
| 11 | * the Free Software Foundation; either version 2 of the License, or␊ |
| 12 | * (at your option) any later version.␊ |
| 13 | *␊ |
| 14 | * This program is distributed in the hope that it will be useful,␊ |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of␊ |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the␊ |
| 17 | * GNU General Public License for more details.␊ |
| 18 | *␊ |
| 19 | * You should have received a copy of the GNU General Public License␊ |
| 20 | * along with this program; if not, write to the Free Software␊ |
| 21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA␊ |
| 22 | */␊ |
| 23 | ␊ |
| 24 | #ifndef __PROGRAMMER_H__␊ |
| 25 | #define __PROGRAMMER_H__ 1␊ |
| 26 | ␊ |
| 27 | #include "flash.h"␉/* for chipaddr and flashctx */␊ |
| 28 | ␊ |
| 29 | enum programmer {␊ |
| 30 | #if CONFIG_INTERNAL == 1␊ |
| 31 | ␉PROGRAMMER_INTERNAL,␊ |
| 32 | #endif␊ |
| 33 | #if CONFIG_DUMMY == 1␊ |
| 34 | ␉PROGRAMMER_DUMMY,␊ |
| 35 | #endif␊ |
| 36 | #if CONFIG_NIC3COM == 1␊ |
| 37 | ␉PROGRAMMER_NIC3COM,␊ |
| 38 | #endif␊ |
| 39 | #if CONFIG_NICREALTEK == 1␊ |
| 40 | ␉PROGRAMMER_NICREALTEK,␊ |
| 41 | #endif␊ |
| 42 | #if CONFIG_NICNATSEMI == 1␊ |
| 43 | ␉PROGRAMMER_NICNATSEMI,␊ |
| 44 | #endif␊ |
| 45 | #if CONFIG_GFXNVIDIA == 1␊ |
| 46 | ␉PROGRAMMER_GFXNVIDIA,␊ |
| 47 | #endif␊ |
| 48 | #if CONFIG_DRKAISER == 1␊ |
| 49 | ␉PROGRAMMER_DRKAISER,␊ |
| 50 | #endif␊ |
| 51 | #if CONFIG_SATASII == 1␊ |
| 52 | ␉PROGRAMMER_SATASII,␊ |
| 53 | #endif␊ |
| 54 | #if CONFIG_ATAHPT == 1␊ |
| 55 | ␉PROGRAMMER_ATAHPT,␊ |
| 56 | #endif␊ |
| 57 | #if CONFIG_FT2232_SPI == 1␊ |
| 58 | ␉PROGRAMMER_FT2232_SPI,␊ |
| 59 | #endif␊ |
| 60 | #if CONFIG_SERPROG == 1␊ |
| 61 | ␉PROGRAMMER_SERPROG,␊ |
| 62 | #endif␊ |
| 63 | #if CONFIG_BUSPIRATE_SPI == 1␊ |
| 64 | ␉PROGRAMMER_BUSPIRATE_SPI,␊ |
| 65 | #endif␊ |
| 66 | #if CONFIG_DEDIPROG == 1␊ |
| 67 | ␉PROGRAMMER_DEDIPROG,␊ |
| 68 | #endif␊ |
| 69 | #if CONFIG_RAYER_SPI == 1␊ |
| 70 | ␉PROGRAMMER_RAYER_SPI,␊ |
| 71 | #endif␊ |
| 72 | #if CONFIG_PONY_SPI == 1␊ |
| 73 | ␉PROGRAMMER_PONY_SPI,␊ |
| 74 | #endif␊ |
| 75 | #if CONFIG_NICINTEL == 1␊ |
| 76 | ␉PROGRAMMER_NICINTEL,␊ |
| 77 | #endif␊ |
| 78 | #if CONFIG_NICINTEL_SPI == 1␊ |
| 79 | ␉PROGRAMMER_NICINTEL_SPI,␊ |
| 80 | #endif␊ |
| 81 | #if CONFIG_OGP_SPI == 1␊ |
| 82 | ␉PROGRAMMER_OGP_SPI,␊ |
| 83 | #endif␊ |
| 84 | #if CONFIG_SATAMV == 1␊ |
| 85 | ␉PROGRAMMER_SATAMV,␊ |
| 86 | #endif␊ |
| 87 | #if CONFIG_LINUX_SPI == 1␊ |
| 88 | ␉PROGRAMMER_LINUX_SPI,␊ |
| 89 | #endif␊ |
| 90 | ␉PROGRAMMER_INVALID /* This must always be the last entry. */␊ |
| 91 | };␊ |
| 92 | ␊ |
| 93 | struct programmer_entry {␊ |
| 94 | ␉const char *vendor;␊ |
| 95 | ␉const char *name;␊ |
| 96 | ␊ |
| 97 | ␉int (*init) (void);␊ |
| 98 | ␊ |
| 99 | ␉void *(*map_flash_region) (const char *descr, unsigned long phys_addr,␊ |
| 100 | ␉␉␉␉ size_t len);␊ |
| 101 | ␉void (*unmap_flash_region) (void *virt_addr, size_t len);␊ |
| 102 | ␊ |
| 103 | ␉void (*delay) (int usecs);␊ |
| 104 | };␊ |
| 105 | ␊ |
| 106 | extern const struct programmer_entry programmer_table[];␊ |
| 107 | ␊ |
| 108 | int programmer_init(enum programmer prog, char *param);␊ |
| 109 | int programmer_shutdown(void);␊ |
| 110 | ␊ |
| 111 | enum bitbang_spi_master_type {␊ |
| 112 | ␉BITBANG_SPI_INVALID␉= 0, /* This must always be the first entry. */␊ |
| 113 | #if CONFIG_RAYER_SPI == 1␊ |
| 114 | ␉BITBANG_SPI_MASTER_RAYER,␊ |
| 115 | #endif␊ |
| 116 | #if CONFIG_PONY_SPI == 1␊ |
| 117 | ␉BITBANG_SPI_MASTER_PONY,␊ |
| 118 | #endif␊ |
| 119 | #if CONFIG_NICINTEL_SPI == 1␊ |
| 120 | ␉BITBANG_SPI_MASTER_NICINTEL,␊ |
| 121 | #endif␊ |
| 122 | #if CONFIG_INTERNAL == 1␊ |
| 123 | #if defined(__i386__) || defined(__x86_64__)␊ |
| 124 | ␉BITBANG_SPI_MASTER_MCP,␊ |
| 125 | #endif␊ |
| 126 | #endif␊ |
| 127 | #if CONFIG_OGP_SPI == 1␊ |
| 128 | ␉BITBANG_SPI_MASTER_OGP,␊ |
| 129 | #endif␊ |
| 130 | };␊ |
| 131 | ␊ |
| 132 | struct bitbang_spi_master {␊ |
| 133 | ␉enum bitbang_spi_master_type type;␊ |
| 134 | ␊ |
| 135 | ␉/* Note that CS# is active low, so val=0 means the chip is active. */␊ |
| 136 | ␉void (*set_cs) (int val);␊ |
| 137 | ␉void (*set_sck) (int val);␊ |
| 138 | ␉void (*set_mosi) (int val);␊ |
| 139 | ␉int (*get_miso) (void);␊ |
| 140 | ␉void (*request_bus) (void);␊ |
| 141 | ␉void (*release_bus) (void);␊ |
| 142 | ␉/* Length of half a clock period in usecs. */␊ |
| 143 | ␉unsigned int half_period;␊ |
| 144 | };␊ |
| 145 | ␊ |
| 146 | #if CONFIG_INTERNAL == 1␊ |
| 147 | struct penable {␊ |
| 148 | ␉uint16_t vendor_id;␊ |
| 149 | ␉uint16_t device_id;␊ |
| 150 | ␉int status; /* OK=0 and NT=1 are defines only. Beware! */␊ |
| 151 | ␉const char *vendor_name;␊ |
| 152 | ␉const char *device_name;␊ |
| 153 | ␉int (*doit) (struct pci_dev *dev, const char *name);␊ |
| 154 | };␊ |
| 155 | ␊ |
| 156 | extern const struct penable chipset_enables[];␊ |
| 157 | ␊ |
| 158 | enum board_match_phase {␊ |
| 159 | ␉P1,␊ |
| 160 | ␉P2,␊ |
| 161 | ␉P3␊ |
| 162 | };␊ |
| 163 | ␊ |
| 164 | struct board_match {␊ |
| 165 | ␉/* Any device, but make it sensible, like the ISA bridge. */␊ |
| 166 | ␉uint16_t first_vendor;␊ |
| 167 | ␉uint16_t first_device;␊ |
| 168 | ␉uint16_t first_card_vendor;␊ |
| 169 | ␉uint16_t first_card_device;␊ |
| 170 | ␊ |
| 171 | ␉/* Any device, but make it sensible, like␊ |
| 172 | ␉ * the host bridge. May be NULL.␊ |
| 173 | ␉ */␊ |
| 174 | ␉uint16_t second_vendor;␊ |
| 175 | ␉uint16_t second_device;␊ |
| 176 | ␉uint16_t second_card_vendor;␊ |
| 177 | ␉uint16_t second_card_device;␊ |
| 178 | ␊ |
| 179 | ␉/* Pattern to match DMI entries. May be NULL. */␊ |
| 180 | ␉const char *dmi_pattern;␊ |
| 181 | ␊ |
| 182 | ␉/* The vendor / part name from the coreboot table. May be NULL. */␊ |
| 183 | ␉const char *lb_vendor;␊ |
| 184 | ␉const char *lb_part;␊ |
| 185 | ␊ |
| 186 | ␉enum board_match_phase phase;␊ |
| 187 | ␊ |
| 188 | ␉const char *vendor_name;␊ |
| 189 | ␉const char *board_name;␊ |
| 190 | ␊ |
| 191 | ␉int max_rom_decode_parallel;␊ |
| 192 | ␉int status;␊ |
| 193 | ␉int (*enable) (void); /* May be NULL. */␊ |
| 194 | };␊ |
| 195 | ␊ |
| 196 | extern const struct board_match board_matches[];␊ |
| 197 | ␊ |
| 198 | struct board_info {␊ |
| 199 | ␉const char *vendor;␊ |
| 200 | ␉const char *name;␊ |
| 201 | ␉const int working;␊ |
| 202 | #ifdef CONFIG_PRINT_WIKI␊ |
| 203 | ␉const char *url;␊ |
| 204 | ␉const char *note;␊ |
| 205 | #endif␊ |
| 206 | };␊ |
| 207 | ␊ |
| 208 | extern const struct board_info boards_known[];␊ |
| 209 | extern const struct board_info laptops_known[];␊ |
| 210 | #endif␊ |
| 211 | ␊ |
| 212 | /* udelay.c */␊ |
| 213 | void myusec_delay(int usecs);␊ |
| 214 | void myusec_calibrate_delay(void);␊ |
| 215 | void internal_delay(int usecs);␊ |
| 216 | ␊ |
| 217 | #if NEED_PCI == 1␊ |
| 218 | /* pcidev.c */␊ |
| 219 | // FIXME: These need to be local, not global␊ |
| 220 | extern uint32_t io_base_addr;␊ |
| 221 | extern struct pci_access *pacc;␊ |
| 222 | extern struct pci_dev *pcidev_dev;␊ |
| 223 | struct pcidev_status {␊ |
| 224 | ␉uint16_t vendor_id;␊ |
| 225 | ␉uint16_t device_id;␊ |
| 226 | ␉int status;␊ |
| 227 | ␉const char *vendor_name;␊ |
| 228 | ␉const char *device_name;␊ |
| 229 | };␊ |
| 230 | uintptr_t pcidev_validate(struct pci_dev *dev, int bar, const struct pcidev_status *devs);␊ |
| 231 | uintptr_t pcidev_init(int bar, const struct pcidev_status *devs);␊ |
| 232 | /* rpci_write_* are reversible writes. The original PCI config space register␊ |
| 233 | * contents will be restored on shutdown.␊ |
| 234 | */␊ |
| 235 | int rpci_write_byte(struct pci_dev *dev, int reg, uint8_t data);␊ |
| 236 | int rpci_write_word(struct pci_dev *dev, int reg, uint16_t data);␊ |
| 237 | int rpci_write_long(struct pci_dev *dev, int reg, uint32_t data);␊ |
| 238 | #endif␊ |
| 239 | ␊ |
| 240 | /* print.c */␊ |
| 241 | #if CONFIG_NIC3COM+CONFIG_NICREALTEK+CONFIG_NICNATSEMI+CONFIG_GFXNVIDIA+CONFIG_DRKAISER+CONFIG_SATASII+CONFIG_ATAHPT+CONFIG_NICINTEL+CONFIG_NICINTEL_SPI+CONFIG_OGP_SPI+CONFIG_SATAMV >= 1␊ |
| 242 | void print_supported_pcidevs(const struct pcidev_status *devs);␊ |
| 243 | #endif␊ |
| 244 | ␊ |
| 245 | #if CONFIG_INTERNAL == 1␊ |
| 246 | /* board_enable.c */␊ |
| 247 | void w836xx_ext_enter(uint16_t port);␊ |
| 248 | void w836xx_ext_leave(uint16_t port);␊ |
| 249 | void probe_superio_winbond(void);␊ |
| 250 | int it8705f_write_enable(uint8_t port);␊ |
| 251 | uint8_t sio_read(uint16_t port, uint8_t reg);␊ |
| 252 | void sio_write(uint16_t port, uint8_t reg, uint8_t data);␊ |
| 253 | void sio_mask(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask);␊ |
| 254 | void board_handle_before_superio(void);␊ |
| 255 | void board_handle_before_laptop(void);␊ |
| 256 | int board_flash_enable(const char *vendor, const char *part);␊ |
| 257 | ␊ |
| 258 | /* chipset_enable.c */␊ |
| 259 | int chipset_flash_enable(void);␊ |
| 260 | ␊ |
| 261 | /* processor_enable.c */␊ |
| 262 | int processor_flash_enable(void);␊ |
| 263 | #endif␊ |
| 264 | ␊ |
| 265 | /* physmap.c */␊ |
| 266 | void *physmap(const char *descr, unsigned long phys_addr, size_t len);␊ |
| 267 | void *physmap_try_ro(const char *descr, unsigned long phys_addr, size_t len);␊ |
| 268 | void physunmap(void *virt_addr, size_t len);␊ |
| 269 | #if CONFIG_INTERNAL == 1␊ |
| 270 | int setup_cpu_msr(int cpu);␊ |
| 271 | void cleanup_cpu_msr(void);␊ |
| 272 | ␊ |
| 273 | /* cbtable.c */␊ |
| 274 | void lb_vendor_dev_from_string(const char *boardstring);␊ |
| 275 | int coreboot_init(void);␊ |
| 276 | extern char *lb_part, *lb_vendor;␊ |
| 277 | extern int partvendor_from_cbtable;␊ |
| 278 | ␊ |
| 279 | /* dmi.c */␊ |
| 280 | extern int has_dmi_support;␊ |
| 281 | void dmi_init(void);␊ |
| 282 | int dmi_match(const char *pattern);␊ |
| 283 | ␊ |
| 284 | /* internal.c */␊ |
| 285 | struct superio {␊ |
| 286 | ␉uint16_t vendor;␊ |
| 287 | ␉uint16_t port;␊ |
| 288 | ␉uint16_t model;␊ |
| 289 | };␊ |
| 290 | extern struct superio superios[];␊ |
| 291 | extern int superio_count;␊ |
| 292 | #define SUPERIO_VENDOR_NONE␉0x0␊ |
| 293 | #define SUPERIO_VENDOR_ITE␉0x1␊ |
| 294 | #define SUPERIO_VENDOR_WINBOND␉0x2␊ |
| 295 | #endif␊ |
| 296 | #if NEED_PCI == 1␊ |
| 297 | struct pci_dev *pci_dev_find_filter(struct pci_filter filter);␊ |
| 298 | struct pci_dev *pci_dev_find_vendorclass(uint16_t vendor, uint16_t devclass);␊ |
| 299 | struct pci_dev *pci_dev_find(uint16_t vendor, uint16_t device);␊ |
| 300 | struct pci_dev *pci_card_find(uint16_t vendor, uint16_t device,␊ |
| 301 | ␉␉␉ uint16_t card_vendor, uint16_t card_device);␊ |
| 302 | #endif␊ |
| 303 | void get_io_perms(void);␊ |
| 304 | void release_io_perms(void);␊ |
| 305 | #if CONFIG_INTERNAL == 1␊ |
| 306 | extern int is_laptop;␊ |
| 307 | extern int laptop_ok;␊ |
| 308 | extern int force_boardenable;␊ |
| 309 | extern int force_boardmismatch;␊ |
| 310 | void probe_superio(void);␊ |
| 311 | int register_superio(struct superio s);␊ |
| 312 | extern enum chipbustype internal_buses_supported;␊ |
| 313 | int internal_init(void);␊ |
| 314 | #endif␊ |
| 315 | ␊ |
| 316 | /* hwaccess.c */␊ |
| 317 | void mmio_writeb(uint8_t val, void *addr);␊ |
| 318 | void mmio_writew(uint16_t val, void *addr);␊ |
| 319 | void mmio_writel(uint32_t val, void *addr);␊ |
| 320 | uint8_t mmio_readb(void *addr);␊ |
| 321 | uint16_t mmio_readw(void *addr);␊ |
| 322 | uint32_t mmio_readl(void *addr);␊ |
| 323 | void mmio_readn(void *addr, uint8_t *buf, size_t len);␊ |
| 324 | void mmio_le_writeb(uint8_t val, void *addr);␊ |
| 325 | void mmio_le_writew(uint16_t val, void *addr);␊ |
| 326 | void mmio_le_writel(uint32_t val, void *addr);␊ |
| 327 | uint8_t mmio_le_readb(void *addr);␊ |
| 328 | uint16_t mmio_le_readw(void *addr);␊ |
| 329 | uint32_t mmio_le_readl(void *addr);␊ |
| 330 | #define pci_mmio_writeb mmio_le_writeb␊ |
| 331 | #define pci_mmio_writew mmio_le_writew␊ |
| 332 | #define pci_mmio_writel mmio_le_writel␊ |
| 333 | #define pci_mmio_readb mmio_le_readb␊ |
| 334 | #define pci_mmio_readw mmio_le_readw␊ |
| 335 | #define pci_mmio_readl mmio_le_readl␊ |
| 336 | void rmmio_writeb(uint8_t val, void *addr);␊ |
| 337 | void rmmio_writew(uint16_t val, void *addr);␊ |
| 338 | void rmmio_writel(uint32_t val, void *addr);␊ |
| 339 | void rmmio_le_writeb(uint8_t val, void *addr);␊ |
| 340 | void rmmio_le_writew(uint16_t val, void *addr);␊ |
| 341 | void rmmio_le_writel(uint32_t val, void *addr);␊ |
| 342 | #define pci_rmmio_writeb rmmio_le_writeb␊ |
| 343 | #define pci_rmmio_writew rmmio_le_writew␊ |
| 344 | #define pci_rmmio_writel rmmio_le_writel␊ |
| 345 | void rmmio_valb(void *addr);␊ |
| 346 | void rmmio_valw(void *addr);␊ |
| 347 | void rmmio_vall(void *addr);␊ |
| 348 | ␊ |
| 349 | /* dummyflasher.c */␊ |
| 350 | #if CONFIG_DUMMY == 1␊ |
| 351 | int dummy_init(void);␊ |
| 352 | void *dummy_map(const char *descr, unsigned long phys_addr, size_t len);␊ |
| 353 | void dummy_unmap(void *virt_addr, size_t len);␊ |
| 354 | #endif␊ |
| 355 | ␊ |
| 356 | /* nic3com.c */␊ |
| 357 | #if CONFIG_NIC3COM == 1␊ |
| 358 | int nic3com_init(void);␊ |
| 359 | extern const struct pcidev_status nics_3com[];␊ |
| 360 | #endif␊ |
| 361 | ␊ |
| 362 | /* gfxnvidia.c */␊ |
| 363 | #if CONFIG_GFXNVIDIA == 1␊ |
| 364 | int gfxnvidia_init(void);␊ |
| 365 | extern const struct pcidev_status gfx_nvidia[];␊ |
| 366 | #endif␊ |
| 367 | ␊ |
| 368 | /* drkaiser.c */␊ |
| 369 | #if CONFIG_DRKAISER == 1␊ |
| 370 | int drkaiser_init(void);␊ |
| 371 | extern const struct pcidev_status drkaiser_pcidev[];␊ |
| 372 | #endif␊ |
| 373 | ␊ |
| 374 | /* nicrealtek.c */␊ |
| 375 | #if CONFIG_NICREALTEK == 1␊ |
| 376 | int nicrealtek_init(void);␊ |
| 377 | extern const struct pcidev_status nics_realtek[];␊ |
| 378 | #endif␊ |
| 379 | ␊ |
| 380 | /* nicnatsemi.c */␊ |
| 381 | #if CONFIG_NICNATSEMI == 1␊ |
| 382 | int nicnatsemi_init(void);␊ |
| 383 | extern const struct pcidev_status nics_natsemi[];␊ |
| 384 | #endif␊ |
| 385 | ␊ |
| 386 | /* nicintel.c */␊ |
| 387 | #if CONFIG_NICINTEL == 1␊ |
| 388 | int nicintel_init(void);␊ |
| 389 | extern const struct pcidev_status nics_intel[];␊ |
| 390 | #endif␊ |
| 391 | ␊ |
| 392 | /* nicintel_spi.c */␊ |
| 393 | #if CONFIG_NICINTEL_SPI == 1␊ |
| 394 | int nicintel_spi_init(void);␊ |
| 395 | extern const struct pcidev_status nics_intel_spi[];␊ |
| 396 | #endif␊ |
| 397 | ␊ |
| 398 | /* ogp_spi.c */␊ |
| 399 | #if CONFIG_OGP_SPI == 1␊ |
| 400 | int ogp_spi_init(void);␊ |
| 401 | extern const struct pcidev_status ogp_spi[];␊ |
| 402 | #endif␊ |
| 403 | ␊ |
| 404 | /* satamv.c */␊ |
| 405 | #if CONFIG_SATAMV == 1␊ |
| 406 | int satamv_init(void);␊ |
| 407 | extern const struct pcidev_status satas_mv[];␊ |
| 408 | #endif␊ |
| 409 | ␊ |
| 410 | /* satasii.c */␊ |
| 411 | #if CONFIG_SATASII == 1␊ |
| 412 | int satasii_init(void);␊ |
| 413 | extern const struct pcidev_status satas_sii[];␊ |
| 414 | #endif␊ |
| 415 | ␊ |
| 416 | /* atahpt.c */␊ |
| 417 | #if CONFIG_ATAHPT == 1␊ |
| 418 | int atahpt_init(void);␊ |
| 419 | extern const struct pcidev_status ata_hpt[];␊ |
| 420 | #endif␊ |
| 421 | ␊ |
| 422 | /* ft2232_spi.c */␊ |
| 423 | #if CONFIG_FT2232_SPI == 1␊ |
| 424 | struct usbdev_status {␊ |
| 425 | ␉uint16_t vendor_id;␊ |
| 426 | ␉uint16_t device_id;␊ |
| 427 | ␉int status;␊ |
| 428 | ␉const char *vendor_name;␊ |
| 429 | ␉const char *device_name;␊ |
| 430 | };␊ |
| 431 | int ft2232_spi_init(void);␊ |
| 432 | extern const struct usbdev_status devs_ft2232spi[];␊ |
| 433 | void print_supported_usbdevs(const struct usbdev_status *devs);␊ |
| 434 | #endif␊ |
| 435 | ␊ |
| 436 | /* rayer_spi.c */␊ |
| 437 | #if CONFIG_RAYER_SPI == 1␊ |
| 438 | int rayer_spi_init(void);␊ |
| 439 | #endif␊ |
| 440 | ␊ |
| 441 | /* pony_spi.c */␊ |
| 442 | #if CONFIG_PONY_SPI == 1␊ |
| 443 | int pony_spi_init(void);␊ |
| 444 | #endif␊ |
| 445 | ␊ |
| 446 | /* bitbang_spi.c */␊ |
| 447 | int bitbang_spi_init(const struct bitbang_spi_master *master);␊ |
| 448 | ␊ |
| 449 | /* buspirate_spi.c */␊ |
| 450 | #if CONFIG_BUSPIRATE_SPI == 1␊ |
| 451 | int buspirate_spi_init(void);␊ |
| 452 | #endif␊ |
| 453 | ␊ |
| 454 | /* linux_spi.c */␊ |
| 455 | #if CONFIG_LINUX_SPI == 1␊ |
| 456 | int linux_spi_init(void);␊ |
| 457 | #endif␊ |
| 458 | ␊ |
| 459 | /* dediprog.c */␊ |
| 460 | #if CONFIG_DEDIPROG == 1␊ |
| 461 | int dediprog_init(void);␊ |
| 462 | #endif␊ |
| 463 | ␊ |
| 464 | /* flashrom.c */␊ |
| 465 | struct decode_sizes {␊ |
| 466 | ␉uint32_t parallel;␊ |
| 467 | ␉uint32_t lpc;␊ |
| 468 | ␉uint32_t fwh;␊ |
| 469 | ␉uint32_t spi;␊ |
| 470 | };␊ |
| 471 | // FIXME: These need to be local, not global␊ |
| 472 | extern struct decode_sizes max_rom_decode;␊ |
| 473 | extern int programmer_may_write;␊ |
| 474 | extern unsigned long flashbase;␊ |
| 475 | void check_chip_supported(const struct flashctx *flash);␊ |
| 476 | int check_max_decode(enum chipbustype buses, uint32_t size);␊ |
| 477 | char *extract_programmer_param(const char *param_name);␊ |
| 478 | ␊ |
| 479 | /* layout.c */␊ |
| 480 | int show_id(uint8_t *bios, int size, int force);␊ |
| 481 | ␊ |
| 482 | /* spi.c */␊ |
| 483 | enum spi_controller {␊ |
| 484 | ␉SPI_CONTROLLER_NONE,␊ |
| 485 | #if CONFIG_INTERNAL == 1␊ |
| 486 | #if defined(__i386__) || defined(__x86_64__)␊ |
| 487 | ␉SPI_CONTROLLER_ICH7,␊ |
| 488 | ␉SPI_CONTROLLER_ICH9,␊ |
| 489 | ␉SPI_CONTROLLER_IT85XX,␊ |
| 490 | ␉SPI_CONTROLLER_IT87XX,␊ |
| 491 | ␉SPI_CONTROLLER_SB600,␊ |
| 492 | ␉SPI_CONTROLLER_VIA,␊ |
| 493 | ␉SPI_CONTROLLER_WBSIO,␊ |
| 494 | #endif␊ |
| 495 | #endif␊ |
| 496 | #if CONFIG_FT2232_SPI == 1␊ |
| 497 | ␉SPI_CONTROLLER_FT2232,␊ |
| 498 | #endif␊ |
| 499 | #if CONFIG_DUMMY == 1␊ |
| 500 | ␉SPI_CONTROLLER_DUMMY,␊ |
| 501 | #endif␊ |
| 502 | #if CONFIG_BUSPIRATE_SPI == 1␊ |
| 503 | ␉SPI_CONTROLLER_BUSPIRATE,␊ |
| 504 | #endif␊ |
| 505 | #if CONFIG_DEDIPROG == 1␊ |
| 506 | ␉SPI_CONTROLLER_DEDIPROG,␊ |
| 507 | #endif␊ |
| 508 | #if CONFIG_OGP_SPI == 1 || CONFIG_NICINTEL_SPI == 1 || CONFIG_RAYER_SPI == 1 || CONFIG_PONY_SPI == 1 || (CONFIG_INTERNAL == 1 && (defined(__i386__) || defined(__x86_64__)))␊ |
| 509 | ␉SPI_CONTROLLER_BITBANG,␊ |
| 510 | #endif␊ |
| 511 | #if CONFIG_LINUX_SPI == 1␊ |
| 512 | ␉SPI_CONTROLLER_LINUX,␊ |
| 513 | #endif␊ |
| 514 | #if CONFIG_SERPROG == 1␊ |
| 515 | ␉SPI_CONTROLLER_SERPROG,␊ |
| 516 | #endif␊ |
| 517 | };␊ |
| 518 | ␊ |
| 519 | #define MAX_DATA_UNSPECIFIED 0␊ |
| 520 | #define MAX_DATA_READ_UNLIMITED 64 * 1024␊ |
| 521 | #define MAX_DATA_WRITE_UNLIMITED 256␊ |
| 522 | struct spi_programmer {␊ |
| 523 | ␉enum spi_controller type;␊ |
| 524 | ␉unsigned int max_data_read;␊ |
| 525 | ␉unsigned int max_data_write;␊ |
| 526 | ␉int (*command)(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt,␊ |
| 527 | ␉␉ const unsigned char *writearr, unsigned char *readarr);␊ |
| 528 | ␉int (*multicommand)(struct flashctx *flash, struct spi_command *cmds);␊ |
| 529 | ␊ |
| 530 | ␉/* Optimized functions for this programmer */␊ |
| 531 | ␉int (*read)(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len);␊ |
| 532 | ␉int (*write_256)(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len);␊ |
| 533 | ␉const void *data;␊ |
| 534 | };␊ |
| 535 | ␊ |
| 536 | int default_spi_send_command(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt,␊ |
| 537 | ␉␉␉ const unsigned char *writearr, unsigned char *readarr);␊ |
| 538 | int default_spi_send_multicommand(struct flashctx *flash, struct spi_command *cmds);␊ |
| 539 | int default_spi_read(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len);␊ |
| 540 | int default_spi_write_256(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len);␊ |
| 541 | int register_spi_programmer(const struct spi_programmer *programmer);␊ |
| 542 | ␊ |
| 543 | /* The following enum is needed by ich_descriptor_tool and ich* code. */␊ |
| 544 | enum ich_chipset {␊ |
| 545 | ␉CHIPSET_ICH_UNKNOWN,␊ |
| 546 | ␉CHIPSET_ICH7 = 7,␊ |
| 547 | ␉CHIPSET_ICH8,␊ |
| 548 | ␉CHIPSET_ICH9,␊ |
| 549 | ␉CHIPSET_ICH10,␊ |
| 550 | ␉CHIPSET_5_SERIES_IBEX_PEAK,␊ |
| 551 | ␉CHIPSET_6_SERIES_COUGAR_POINT,␊ |
| 552 | ␉CHIPSET_7_SERIES_PANTHER_POINT,␊ |
| 553 | ␉CHIPSET_8_SERIES_LYNX_POINT␊ |
| 554 | };␊ |
| 555 | ␊ |
| 556 | /* ichspi.c */␊ |
| 557 | #if CONFIG_INTERNAL == 1␊ |
| 558 | extern uint32_t ichspi_bbar;␊ |
| 559 | int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb,␊ |
| 560 | ␉␉ enum ich_chipset ich_generation);␊ |
| 561 | int via_init_spi(struct pci_dev *dev);␊ |
| 562 | ␊ |
| 563 | /* it85spi.c */␊ |
| 564 | int it85xx_spi_init(struct superio s);␊ |
| 565 | ␊ |
| 566 | /* it87spi.c */␊ |
| 567 | void enter_conf_mode_ite(uint16_t port);␊ |
| 568 | void exit_conf_mode_ite(uint16_t port);␊ |
| 569 | void probe_superio_ite(void);␊ |
| 570 | int init_superio_ite(void);␊ |
| 571 | ␊ |
| 572 | /* mcp6x_spi.c */␊ |
| 573 | int mcp6x_spi_init(int want_spi);␊ |
| 574 | ␊ |
| 575 | /* sb600spi.c */␊ |
| 576 | int sb600_probe_spi(struct pci_dev *dev);␊ |
| 577 | ␊ |
| 578 | /* wbsio_spi.c */␊ |
| 579 | int wbsio_check_for_spi(void);␊ |
| 580 | #endif␊ |
| 581 | ␊ |
| 582 | /* opaque.c */␊ |
| 583 | struct opaque_programmer {␊ |
| 584 | ␉int max_data_read;␊ |
| 585 | ␉int max_data_write;␊ |
| 586 | ␉/* Specific functions for this programmer */␊ |
| 587 | ␉int (*probe) (struct flashctx *flash);␊ |
| 588 | ␉int (*read) (struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len);␊ |
| 589 | ␉int (*write) (struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len);␊ |
| 590 | ␉int (*erase) (struct flashctx *flash, unsigned int blockaddr, unsigned int blocklen);␊ |
| 591 | ␉const void *data;␊ |
| 592 | };␊ |
| 593 | int register_opaque_programmer(const struct opaque_programmer *pgm);␊ |
| 594 | ␊ |
| 595 | /* programmer.c */␊ |
| 596 | int noop_shutdown(void);␊ |
| 597 | void *fallback_map(const char *descr, unsigned long phys_addr, size_t len);␊ |
| 598 | void fallback_unmap(void *virt_addr, size_t len);␊ |
| 599 | void noop_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr);␊ |
| 600 | void fallback_chip_writew(const struct flashctx *flash, uint16_t val, chipaddr addr);␊ |
| 601 | void fallback_chip_writel(const struct flashctx *flash, uint32_t val, chipaddr addr);␊ |
| 602 | void fallback_chip_writen(const struct flashctx *flash, uint8_t *buf, chipaddr addr, size_t len);␊ |
| 603 | uint16_t fallback_chip_readw(const struct flashctx *flash, const chipaddr addr);␊ |
| 604 | uint32_t fallback_chip_readl(const struct flashctx *flash, const chipaddr addr);␊ |
| 605 | void fallback_chip_readn(const struct flashctx *flash, uint8_t *buf, const chipaddr addr, size_t len);␊ |
| 606 | struct par_programmer {␊ |
| 607 | ␉void (*chip_writeb) (const struct flashctx *flash, uint8_t val, chipaddr addr);␊ |
| 608 | ␉void (*chip_writew) (const struct flashctx *flash, uint16_t val, chipaddr addr);␊ |
| 609 | ␉void (*chip_writel) (const struct flashctx *flash, uint32_t val, chipaddr addr);␊ |
| 610 | ␉void (*chip_writen) (const struct flashctx *flash, uint8_t *buf, chipaddr addr, size_t len);␊ |
| 611 | ␉uint8_t (*chip_readb) (const struct flashctx *flash, const chipaddr addr);␊ |
| 612 | ␉uint16_t (*chip_readw) (const struct flashctx *flash, const chipaddr addr);␊ |
| 613 | ␉uint32_t (*chip_readl) (const struct flashctx *flash, const chipaddr addr);␊ |
| 614 | ␉void (*chip_readn) (const struct flashctx *flash, uint8_t *buf, const chipaddr addr, size_t len);␊ |
| 615 | ␉const void *data;␊ |
| 616 | };␊ |
| 617 | int register_par_programmer(const struct par_programmer *pgm, const enum chipbustype buses);␊ |
| 618 | struct registered_programmer {␊ |
| 619 | ␉enum chipbustype buses_supported;␊ |
| 620 | ␉union {␊ |
| 621 | ␉␉struct par_programmer par;␊ |
| 622 | ␉␉struct spi_programmer spi;␊ |
| 623 | ␉␉struct opaque_programmer opaque;␊ |
| 624 | ␉};␊ |
| 625 | };␊ |
| 626 | extern struct registered_programmer registered_programmers[];␊ |
| 627 | extern int registered_programmer_count;␊ |
| 628 | int register_programmer(struct registered_programmer *pgm);␊ |
| 629 | ␊ |
| 630 | /* serprog.c */␊ |
| 631 | #if CONFIG_SERPROG == 1␊ |
| 632 | int serprog_init(void);␊ |
| 633 | void serprog_delay(int usecs);␊ |
| 634 | #endif␊ |
| 635 | ␊ |
| 636 | /* serial.c */␊ |
| 637 | #if _WIN32␊ |
| 638 | typedef HANDLE fdtype;␊ |
| 639 | #else␊ |
| 640 | typedef int fdtype;␊ |
| 641 | #endif␊ |
| 642 | ␊ |
| 643 | void sp_flush_incoming(void);␊ |
| 644 | fdtype sp_openserport(char *dev, unsigned int baud);␊ |
| 645 | void __attribute__((noreturn)) sp_die(char *msg);␊ |
| 646 | extern fdtype sp_fd;␊ |
| 647 | /* expose serialport_shutdown as it's currently used by buspirate */␊ |
| 648 | int serialport_shutdown(void *data);␊ |
| 649 | int serialport_write(unsigned char *buf, unsigned int writecnt);␊ |
| 650 | int serialport_read(unsigned char *buf, unsigned int readcnt);␊ |
| 651 | ␊ |
| 652 | /* Serial port/pin mapping:␊ |
| 653 | ␊ |
| 654 | 1␉CD␉<-␊ |
| 655 | 2␉RXD␉<-␊ |
| 656 | 3␉TXD␉->␊ |
| 657 | 4␉DTR␉->␊ |
| 658 | 5␉GND --␊ |
| 659 | 6␉DSR␉<-␊ |
| 660 | 7␉RTS␉->␊ |
| 661 | 8␉CTS␉<-␊ |
| 662 | 9␉RI␉<-␊ |
| 663 | */␊ |
| 664 | enum SP_PIN {␊ |
| 665 | ␉PIN_CD = 1,␊ |
| 666 | ␉PIN_RXD,␊ |
| 667 | ␉PIN_TXD,␊ |
| 668 | ␉PIN_DTR,␊ |
| 669 | ␉PIN_GND,␊ |
| 670 | ␉PIN_DSR,␊ |
| 671 | ␉PIN_RTS,␊ |
| 672 | ␉PIN_CTS,␊ |
| 673 | ␉PIN_RI,␊ |
| 674 | };␊ |
| 675 | ␊ |
| 676 | void sp_set_pin(enum SP_PIN pin, int val);␊ |
| 677 | int sp_get_pin(enum SP_PIN pin);␊ |
| 678 | ␊ |
| 679 | #endif␉␉␉␉/* !__PROGRAMMER_H__ */␊ |
| 680 | |
