| 1 | /*␊ |
| 2 | * This file is part of the flashrom project.␊ |
| 3 | *␊ |
| 4 | * Copyright (C) 2009 Joerg Fischer <turboj@gmx.de>␊ |
| 5 | *␊ |
| 6 | * This program is free software; you can redistribute it and/or modify␊ |
| 7 | * it under the terms of the GNU General Public License as published by␊ |
| 8 | * the Free Software Foundation; either version 2 of the License, or␊ |
| 9 | * (at your option) any later version.␊ |
| 10 | *␊ |
| 11 | * This program is distributed in the hope that it will be useful,␊ |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of␊ |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the␊ |
| 14 | * GNU General Public License for more details.␊ |
| 15 | *␊ |
| 16 | * You should have received a copy of the GNU General Public License␊ |
| 17 | * along with this program; if not, write to the Free Software␊ |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA␊ |
| 19 | */␊ |
| 20 | ␊ |
| 21 | #if defined(__i386__) || defined(__x86_64__)␊ |
| 22 | ␊ |
| 23 | #include <stdlib.h>␊ |
| 24 | #include "flash.h"␊ |
| 25 | #include "programmer.h"␊ |
| 26 | ␊ |
| 27 | #define PCI_VENDOR_ID_REALTEK␉0x10ec␊ |
| 28 | #define PCI_VENDOR_ID_SMC1211␉0x1113␊ |
| 29 | ␊ |
| 30 | #define BIOS_ROM_ADDR␉␉0xD4␊ |
| 31 | #define BIOS_ROM_DATA␉␉0xD7␊ |
| 32 | ␊ |
| 33 | const struct pcidev_status nics_realtek[] = {␊ |
| 34 | ␉{0x10ec, 0x8139, OK, "Realtek", "RTL8139/8139C/8139C+"},␊ |
| 35 | ␉{0x1113, 0x1211, OK, "SMC2", "1211TX"}, /* RTL8139 clone */␊ |
| 36 | ␉{},␊ |
| 37 | };␊ |
| 38 | ␊ |
| 39 | static void nicrealtek_chip_writeb(const struct flashctx *flash, uint8_t val,␊ |
| 40 | ␉␉␉␉ chipaddr addr);␊ |
| 41 | static uint8_t nicrealtek_chip_readb(const struct flashctx *flash,␊ |
| 42 | ␉␉␉␉ const chipaddr addr);␊ |
| 43 | static const struct par_programmer par_programmer_nicrealtek = {␊ |
| 44 | ␉␉.chip_readb␉␉= nicrealtek_chip_readb,␊ |
| 45 | ␉␉.chip_readw␉␉= fallback_chip_readw,␊ |
| 46 | ␉␉.chip_readl␉␉= fallback_chip_readl,␊ |
| 47 | ␉␉.chip_readn␉␉= fallback_chip_readn,␊ |
| 48 | ␉␉.chip_writeb␉␉= nicrealtek_chip_writeb,␊ |
| 49 | ␉␉.chip_writew␉␉= fallback_chip_writew,␊ |
| 50 | ␉␉.chip_writel␉␉= fallback_chip_writel,␊ |
| 51 | ␉␉.chip_writen␉␉= fallback_chip_writen,␊ |
| 52 | };␊ |
| 53 | ␊ |
| 54 | static int nicrealtek_shutdown(void *data)␊ |
| 55 | {␊ |
| 56 | ␉/* FIXME: We forgot to disable software access again. */␊ |
| 57 | ␉pci_cleanup(pacc);␊ |
| 58 | ␉release_io_perms();␊ |
| 59 | ␉return 0;␊ |
| 60 | }␊ |
| 61 | ␊ |
| 62 | int nicrealtek_init(void)␊ |
| 63 | {␊ |
| 64 | ␉get_io_perms();␊ |
| 65 | ␊ |
| 66 | ␉io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, nics_realtek);␊ |
| 67 | ␊ |
| 68 | ␉if (register_shutdown(nicrealtek_shutdown, NULL))␊ |
| 69 | ␉␉return 1;␊ |
| 70 | ␊ |
| 71 | ␉register_par_programmer(&par_programmer_nicrealtek, BUS_PARALLEL);␊ |
| 72 | ␊ |
| 73 | ␉return 0;␊ |
| 74 | }␊ |
| 75 | ␊ |
| 76 | static void nicrealtek_chip_writeb(const struct flashctx *flash, uint8_t val,␊ |
| 77 | ␉␉␉␉ chipaddr addr)␊ |
| 78 | {␊ |
| 79 | ␉/* Output addr and data, set WE to 0, set OE to 1, set CS to 0,␊ |
| 80 | ␉ * enable software access.␊ |
| 81 | ␉ */␊ |
| 82 | ␉OUTL(((uint32_t)addr & 0x01FFFF) | 0x0A0000 | (val << 24),␊ |
| 83 | ␉ io_base_addr + BIOS_ROM_ADDR);␊ |
| 84 | ␉/* Output addr and data, set WE to 1, set OE to 1, set CS to 1,␊ |
| 85 | ␉ * enable software access.␊ |
| 86 | ␉ */␊ |
| 87 | ␉OUTL(((uint32_t)addr & 0x01FFFF) | 0x1E0000 | (val << 24),␊ |
| 88 | ␉ io_base_addr + BIOS_ROM_ADDR);␊ |
| 89 | }␊ |
| 90 | ␊ |
| 91 | static uint8_t nicrealtek_chip_readb(const struct flashctx *flash,␊ |
| 92 | ␉␉␉␉ const chipaddr addr)␊ |
| 93 | {␊ |
| 94 | ␉uint8_t val;␊ |
| 95 | ␊ |
| 96 | ␉/* FIXME: Can we skip reading the old data and simply use 0? */␊ |
| 97 | ␉/* Read old data. */␊ |
| 98 | ␉val = INB(io_base_addr + BIOS_ROM_DATA);␊ |
| 99 | ␉/* Output new addr and old data, set WE to 1, set OE to 0, set CS to 0,␊ |
| 100 | ␉ * enable software access.␊ |
| 101 | ␉ */␊ |
| 102 | ␉OUTL(((uint32_t)addr & 0x01FFFF) | 0x060000 | (val << 24),␊ |
| 103 | ␉ io_base_addr + BIOS_ROM_ADDR);␊ |
| 104 | ␊ |
| 105 | ␉/* Read new data. */␊ |
| 106 | ␉val = INB(io_base_addr + BIOS_ROM_DATA);␊ |
| 107 | ␉/* Output addr and new data, set WE to 1, set OE to 1, set CS to 1,␊ |
| 108 | ␉ * enable software access.␊ |
| 109 | ␉ */␊ |
| 110 | ␉OUTL(((uint32_t)addr & 0x01FFFF) | 0x1E0000 | (val << 24),␊ |
| 111 | ␉ io_base_addr + BIOS_ROM_ADDR);␊ |
| 112 | ␊ |
| 113 | ␉return val;␊ |
| 114 | }␊ |
| 115 | ␊ |
| 116 | #else␊ |
| 117 | #error PCI port I/O access is not supported on this architecture yet.␊ |
| 118 | #endif␊ |
| 119 | |
