| 1 | /*␊ |
| 2 | * This file is part of the flashrom project.␊ |
| 3 | *␊ |
| 4 | * Copyright (C) 2010 Andrew Morgan <ziltro@ziltro.com>␊ |
| 5 | *␊ |
| 6 | * This program is free software; you can redistribute it and/or modify␊ |
| 7 | * it under the terms of the GNU General Public License as published by␊ |
| 8 | * the Free Software Foundation; either version 2 of the License, or␊ |
| 9 | * (at your option) any later version.␊ |
| 10 | *␊ |
| 11 | * This program is distributed in the hope that it will be useful,␊ |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of␊ |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the␊ |
| 14 | * GNU General Public License for more details.␊ |
| 15 | *␊ |
| 16 | * You should have received a copy of the GNU General Public License␊ |
| 17 | * along with this program; if not, write to the Free Software␊ |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA␊ |
| 19 | */␊ |
| 20 | ␊ |
| 21 | #if defined(__i386__) || defined(__x86_64__)␊ |
| 22 | ␊ |
| 23 | #include <stdlib.h>␊ |
| 24 | #include "flash.h"␊ |
| 25 | #include "programmer.h"␊ |
| 26 | ␊ |
| 27 | #define PCI_VENDOR_ID_NATSEMI␉0x100b␊ |
| 28 | ␊ |
| 29 | #define BOOT_ROM_ADDR␉␉0x50␊ |
| 30 | #define BOOT_ROM_DATA␉␉0x54␊ |
| 31 | ␊ |
| 32 | const struct pcidev_status nics_natsemi[] = {␊ |
| 33 | ␉{0x100b, 0x0020, NT, "National Semiconductor", "DP83815/DP83816"},␊ |
| 34 | ␉{0x100b, 0x0022, NT, "National Semiconductor", "DP83820"},␊ |
| 35 | ␉{},␊ |
| 36 | };␊ |
| 37 | ␊ |
| 38 | static void nicnatsemi_chip_writeb(const struct flashctx *flash, uint8_t val,␊ |
| 39 | ␉␉␉␉ chipaddr addr);␊ |
| 40 | static uint8_t nicnatsemi_chip_readb(const struct flashctx *flash,␊ |
| 41 | ␉␉␉␉ const chipaddr addr);␊ |
| 42 | static const struct par_programmer par_programmer_nicnatsemi = {␊ |
| 43 | ␉␉.chip_readb␉␉= nicnatsemi_chip_readb,␊ |
| 44 | ␉␉.chip_readw␉␉= fallback_chip_readw,␊ |
| 45 | ␉␉.chip_readl␉␉= fallback_chip_readl,␊ |
| 46 | ␉␉.chip_readn␉␉= fallback_chip_readn,␊ |
| 47 | ␉␉.chip_writeb␉␉= nicnatsemi_chip_writeb,␊ |
| 48 | ␉␉.chip_writew␉␉= fallback_chip_writew,␊ |
| 49 | ␉␉.chip_writel␉␉= fallback_chip_writel,␊ |
| 50 | ␉␉.chip_writen␉␉= fallback_chip_writen,␊ |
| 51 | };␊ |
| 52 | ␊ |
| 53 | static int nicnatsemi_shutdown(void *data)␊ |
| 54 | {␊ |
| 55 | ␉pci_cleanup(pacc);␊ |
| 56 | ␉release_io_perms();␊ |
| 57 | ␉return 0;␊ |
| 58 | }␊ |
| 59 | ␊ |
| 60 | int nicnatsemi_init(void)␊ |
| 61 | {␊ |
| 62 | ␉get_io_perms();␊ |
| 63 | ␊ |
| 64 | ␉io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, nics_natsemi);␊ |
| 65 | ␊ |
| 66 | ␉if (register_shutdown(nicnatsemi_shutdown, NULL))␊ |
| 67 | ␉␉return 1;␊ |
| 68 | ␊ |
| 69 | ␉/* The datasheet shows address lines MA0-MA16 in one place and MA0-MA15␊ |
| 70 | ␉ * in another. My NIC has MA16 connected to A16 on the boot ROM socket␊ |
| 71 | ␉ * so I'm assuming it is accessible. If not then next line wants to be␊ |
| 72 | ␉ * max_rom_decode.parallel = 65536; and the mask in the read/write␊ |
| 73 | ␉ * functions below wants to be 0x0000FFFF.␊ |
| 74 | ␉ */␊ |
| 75 | ␉max_rom_decode.parallel = 131072;␊ |
| 76 | ␉register_par_programmer(&par_programmer_nicnatsemi, BUS_PARALLEL);␊ |
| 77 | ␊ |
| 78 | ␉return 0;␊ |
| 79 | }␊ |
| 80 | ␊ |
| 81 | static void nicnatsemi_chip_writeb(const struct flashctx *flash, uint8_t val,␊ |
| 82 | ␉␉␉␉ chipaddr addr)␊ |
| 83 | {␊ |
| 84 | ␉OUTL((uint32_t)addr & 0x0001FFFF, io_base_addr + BOOT_ROM_ADDR);␊ |
| 85 | ␉/*␊ |
| 86 | ␉ * The datasheet requires 32 bit accesses to this register, but it seems␊ |
| 87 | ␉ * that requirement might only apply if the register is memory mapped.␊ |
| 88 | ␉ * Bits 8-31 of this register are apparently don't care, and if this␊ |
| 89 | ␉ * register is I/O port mapped, 8 bit accesses to the lowest byte of the␊ |
| 90 | ␉ * register seem to work fine. Due to that, we ignore the advice in the␊ |
| 91 | ␉ * data sheet.␊ |
| 92 | ␉ */␊ |
| 93 | ␉OUTB(val, io_base_addr + BOOT_ROM_DATA);␊ |
| 94 | }␊ |
| 95 | ␊ |
| 96 | static uint8_t nicnatsemi_chip_readb(const struct flashctx *flash,␊ |
| 97 | ␉␉␉␉ const chipaddr addr)␊ |
| 98 | {␊ |
| 99 | ␉OUTL(((uint32_t)addr & 0x0001FFFF), io_base_addr + BOOT_ROM_ADDR);␊ |
| 100 | ␉/*␊ |
| 101 | ␉ * The datasheet requires 32 bit accesses to this register, but it seems␊ |
| 102 | ␉ * that requirement might only apply if the register is memory mapped.␊ |
| 103 | ␉ * Bits 8-31 of this register are apparently don't care, and if this␊ |
| 104 | ␉ * register is I/O port mapped, 8 bit accesses to the lowest byte of the␊ |
| 105 | ␉ * register seem to work fine. Due to that, we ignore the advice in the␊ |
| 106 | ␉ * data sheet.␊ |
| 107 | ␉ */␊ |
| 108 | ␉return INB(io_base_addr + BOOT_ROM_DATA);␊ |
| 109 | }␊ |
| 110 | ␊ |
| 111 | #else␊ |
| 112 | #error PCI port I/O access is not supported on this architecture yet.␊ |
| 113 | #endif␊ |
| 114 | |
