Flashrom

Flashrom Svn Source Tree

Root/trunk/nicintel_spi.c

1/*␊
2 * This file is part of the flashrom project.␊
3 *␊
4 * Copyright (C) 2010 Carl-Daniel Hailfinger␊
5 * Copyright (C) 2010 Idwer Vollering␊
6 *␊
7 * This program is free software; you can redistribute it and/or modify␊
8 * it under the terms of the GNU General Public License as published by␊
9 * the Free Software Foundation; version 2 of the License.␊
10 *␊
11 * This program is distributed in the hope that it will be useful,␊
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of␊
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the␊
14 * GNU General Public License for more details.␊
15 *␊
16 * You should have received a copy of the GNU General Public License␊
17 * along with this program; if not, write to the Free Software␊
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA␊
19 */␊
20␊
21/*␊
22 * Datasheet:␊
23 * PCI/PCI-X Family of Gigabit Ethernet Controllers Software Developer's Manual␊
24 * 82540EP/EM, 82541xx, 82544GC/EI, 82545GM/EM, 82546GB/EB, and 82547xx␊
25 * http://download.intel.com/design/network/manuals/8254x_GBe_SDM.pdf␊
26 */␊
27␊
28#include <stdlib.h>␊
29#include "flash.h"␊
30#include "programmer.h"␊
31␊
32#define PCI_VENDOR_ID_INTEL 0x8086␊
33␊
34#define EECD␉0x10␊
35#define FLA␉0x1c␊
36␊
37/*␊
38 * Register bits of EECD.␊
39 * ␊
40 * Bit 04, 05: FWE (Flash Write Enable Control)␊
41 * 00b = not allowed␊
42 * 01b = flash writes disabled␊
43 * 10b = flash writes enabled␊
44 * 11b = not allowed␊
45 */␊
46#define FLASH_WRITES_DISABLED␉0x10 /* FWE: 10000b */␊
47#define FLASH_WRITES_ENABLED␉0x20 /* FWE: 100000b */␊
48␊
49/* Flash Access register bits */␊
50/* Table 13-9 */␊
51#define FL_SCK␉0␊
52#define FL_CS␉1␊
53#define FL_SI␉2␊
54#define FL_SO␉3␊
55#define FL_REQ␉4␊
56#define FL_GNT␉5␊
57/* Currently unused */␊
58// #define FL_BUSY␉30␊
59// #define FL_ER␉31␊
60␊
61uint8_t *nicintel_spibar;␊
62␊
63const struct pcidev_status nics_intel_spi[] = {␊
64␉{PCI_VENDOR_ID_INTEL, 0x105e, OK, "Intel", "82571EB Gigabit Ethernet Controller"},␊
65␉{PCI_VENDOR_ID_INTEL, 0x1076, OK, "Intel", "82541GI Gigabit Ethernet Controller"},␊
66␉{PCI_VENDOR_ID_INTEL, 0x107c, OK, "Intel", "82541PI Gigabit Ethernet Controller"},␊
67␉{PCI_VENDOR_ID_INTEL, 0x10b9, OK, "Intel", "82572EI Gigabit Ethernet Controller"},␊
68␊
69␉{},␊
70};␊
71␊
72static void nicintel_request_spibus(void)␊
73{␊
74␉uint32_t tmp;␊
75␊
76␉tmp = pci_mmio_readl(nicintel_spibar + FLA);␊
77␉tmp |= 1 << FL_REQ;␊
78␉pci_mmio_writel(tmp, nicintel_spibar + FLA);␊
79␊
80␉/* Wait until we are allowed to use the SPI bus. */␊
81␉while (!(pci_mmio_readl(nicintel_spibar + FLA) & (1 << FL_GNT))) ;␊
82}␊
83␊
84static void nicintel_release_spibus(void)␊
85{␊
86␉uint32_t tmp;␊
87␊
88␉tmp = pci_mmio_readl(nicintel_spibar + FLA);␊
89␉tmp &= ~(1 << FL_REQ);␊
90␉pci_mmio_writel(tmp, nicintel_spibar + FLA);␊
91}␊
92␊
93static void nicintel_bitbang_set_cs(int val)␊
94{␊
95␉uint32_t tmp;␊
96␊
97␉tmp = pci_mmio_readl(nicintel_spibar + FLA);␊
98␉tmp &= ~(1 << FL_CS);␊
99␉tmp |= (val << FL_CS);␊
100␉pci_mmio_writel(tmp, nicintel_spibar + FLA);␊
101}␊
102␊
103static void nicintel_bitbang_set_sck(int val)␊
104{␊
105␉uint32_t tmp;␊
106␊
107␉tmp = pci_mmio_readl(nicintel_spibar + FLA);␊
108␉tmp &= ~(1 << FL_SCK);␊
109␉tmp |= (val << FL_SCK);␊
110␉pci_mmio_writel(tmp, nicintel_spibar + FLA);␊
111}␊
112␊
113static void nicintel_bitbang_set_mosi(int val)␊
114{␊
115␉uint32_t tmp;␊
116␊
117␉tmp = pci_mmio_readl(nicintel_spibar + FLA);␊
118␉tmp &= ~(1 << FL_SI);␊
119␉tmp |= (val << FL_SI);␊
120␉pci_mmio_writel(tmp, nicintel_spibar + FLA);␊
121}␊
122␊
123static int nicintel_bitbang_get_miso(void)␊
124{␊
125␉uint32_t tmp;␊
126␊
127␉tmp = pci_mmio_readl(nicintel_spibar + FLA);␊
128␉tmp = (tmp >> FL_SO) & 0x1;␊
129␉return tmp;␊
130}␊
131␊
132static const struct bitbang_spi_master bitbang_spi_master_nicintel = {␊
133␉.type = BITBANG_SPI_MASTER_NICINTEL,␊
134␉.set_cs = nicintel_bitbang_set_cs,␊
135␉.set_sck = nicintel_bitbang_set_sck,␊
136␉.set_mosi = nicintel_bitbang_set_mosi,␊
137␉.get_miso = nicintel_bitbang_get_miso,␊
138␉.request_bus = nicintel_request_spibus,␊
139␉.release_bus = nicintel_release_spibus,␊
140␉.half_period = 1,␊
141};␊
142␊
143static int nicintel_spi_shutdown(void *data)␊
144{␊
145␉uint32_t tmp;␊
146␊
147␉/* Disable writes manually. See the comment about EECD in␊
148␉ * nicintel_spi_init() for details.␊
149␉ */␊
150␉tmp = pci_mmio_readl(nicintel_spibar + EECD);␊
151␉tmp &= ~FLASH_WRITES_ENABLED;␊
152␉tmp |= FLASH_WRITES_DISABLED;␊
153␉pci_mmio_writel(tmp, nicintel_spibar + EECD);␊
154␊
155␉physunmap(nicintel_spibar, 4096);␊
156␉pci_cleanup(pacc);␊
157␉release_io_perms();␊
158␊
159␉return 0;␊
160}␊
161␊
162int nicintel_spi_init(void)␊
163{␊
164␉uint32_t tmp;␊
165␊
166␉get_io_perms();␊
167␊
168␉io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, nics_intel_spi);␊
169␊
170␉nicintel_spibar = physmap("Intel Gigabit NIC w/ SPI flash",␊
171␉␉␉␉ io_base_addr, 4096);␊
172␉/* Automatic restore of EECD on shutdown is not possible because EECD␊
173␉ * does not only contain FLASH_WRITES_DISABLED|FLASH_WRITES_ENABLED,␊
174␉ * but other bits with side effects as well. Those other bits must be␊
175␉ * left untouched.␊
176␉ */␊
177␉tmp = pci_mmio_readl(nicintel_spibar + EECD);␊
178␉tmp &= ~FLASH_WRITES_DISABLED;␊
179␉tmp |= FLASH_WRITES_ENABLED;␊
180␉pci_mmio_writel(tmp, nicintel_spibar + EECD);␊
181␊
182␉if (register_shutdown(nicintel_spi_shutdown, NULL))␊
183␉␉return 1;␊
184␊
185␉if (bitbang_spi_init(&bitbang_spi_master_nicintel))␊
186␉␉return 1;␊
187␊
188␉return 0;␊
189}␊
190

Archive Download this file

Revision: HEAD