| 1 | /*␊ |
| 2 | * This file is part of the flashrom project.␊ |
| 3 | *␊ |
| 4 | * Copyright (C) 2011 Carl-Daniel Hailfinger␊ |
| 5 | *␊ |
| 6 | * This program is free software; you can redistribute it and/or modify␊ |
| 7 | * it under the terms of the GNU General Public License as published by␊ |
| 8 | * the Free Software Foundation; version 2 of the License.␊ |
| 9 | *␊ |
| 10 | * This program is distributed in the hope that it will be useful,␊ |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of␊ |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the␊ |
| 13 | * GNU General Public License for more details.␊ |
| 14 | *␊ |
| 15 | * You should have received a copy of the GNU General Public License␊ |
| 16 | * along with this program; if not, write to the Free Software␊ |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA␊ |
| 18 | */␊ |
| 19 | ␊ |
| 20 | /* Datasheet: http://download.intel.com/design/network/datashts/82559_Fast_Ethernet_Multifunction_PCI_Cardbus_Controller_Datasheet.pdf */␊ |
| 21 | ␊ |
| 22 | #include <stdlib.h>␊ |
| 23 | #include "flash.h"␊ |
| 24 | #include "programmer.h"␊ |
| 25 | ␊ |
| 26 | uint8_t *nicintel_bar;␊ |
| 27 | uint8_t *nicintel_control_bar;␊ |
| 28 | ␊ |
| 29 | const struct pcidev_status nics_intel[] = {␊ |
| 30 | ␉{PCI_VENDOR_ID_INTEL, 0x1209, NT, "Intel", "8255xER/82551IT Fast Ethernet Controller"},␊ |
| 31 | ␉{PCI_VENDOR_ID_INTEL, 0x1229, OK, "Intel", "82557/8/9/0/1 Ethernet Pro 100"},␊ |
| 32 | ␊ |
| 33 | ␉{},␊ |
| 34 | };␊ |
| 35 | ␊ |
| 36 | /* Arbitrary limit, taken from the datasheet I just had lying around.␊ |
| 37 | * 128 kByte on the 82559 device. Or not. Depends on whom you ask.␊ |
| 38 | */␊ |
| 39 | #define NICINTEL_MEMMAP_SIZE (128 * 1024)␊ |
| 40 | #define NICINTEL_MEMMAP_MASK (NICINTEL_MEMMAP_SIZE - 1)␊ |
| 41 | ␊ |
| 42 | #define NICINTEL_CONTROL_MEMMAP_SIZE␉0x10 ␊ |
| 43 | ␊ |
| 44 | #define CSR_FCR 0x0c␊ |
| 45 | ␊ |
| 46 | static void nicintel_chip_writeb(const struct flashctx *flash, uint8_t val,␊ |
| 47 | ␉␉␉␉ chipaddr addr);␊ |
| 48 | static uint8_t nicintel_chip_readb(const struct flashctx *flash,␊ |
| 49 | ␉␉␉␉ const chipaddr addr);␊ |
| 50 | static const struct par_programmer par_programmer_nicintel = {␊ |
| 51 | ␉␉.chip_readb␉␉= nicintel_chip_readb,␊ |
| 52 | ␉␉.chip_readw␉␉= fallback_chip_readw,␊ |
| 53 | ␉␉.chip_readl␉␉= fallback_chip_readl,␊ |
| 54 | ␉␉.chip_readn␉␉= fallback_chip_readn,␊ |
| 55 | ␉␉.chip_writeb␉␉= nicintel_chip_writeb,␊ |
| 56 | ␉␉.chip_writew␉␉= fallback_chip_writew,␊ |
| 57 | ␉␉.chip_writel␉␉= fallback_chip_writel,␊ |
| 58 | ␉␉.chip_writen␉␉= fallback_chip_writen,␊ |
| 59 | };␊ |
| 60 | ␊ |
| 61 | static int nicintel_shutdown(void *data)␊ |
| 62 | {␊ |
| 63 | ␉physunmap(nicintel_control_bar, NICINTEL_CONTROL_MEMMAP_SIZE);␊ |
| 64 | ␉physunmap(nicintel_bar, NICINTEL_MEMMAP_SIZE);␊ |
| 65 | ␉pci_cleanup(pacc);␊ |
| 66 | ␉release_io_perms();␊ |
| 67 | ␉return 0;␊ |
| 68 | }␊ |
| 69 | ␊ |
| 70 | int nicintel_init(void)␊ |
| 71 | {␊ |
| 72 | ␉uintptr_t addr;␊ |
| 73 | ␊ |
| 74 | ␉/* Needed only for PCI accesses on some platforms.␊ |
| 75 | ␉ * FIXME: Refactor that into get_mem_perms/get_io_perms/get_pci_perms?␊ |
| 76 | ␉ */␊ |
| 77 | ␉get_io_perms();␊ |
| 78 | ␊ |
| 79 | ␉/* No need to check for errors, pcidev_init() will not return in case␊ |
| 80 | ␉ * of errors.␊ |
| 81 | ␉ * FIXME: BAR2 is not available if the device uses the CardBus function.␊ |
| 82 | ␉ */␊ |
| 83 | ␉addr = pcidev_init(PCI_BASE_ADDRESS_2, nics_intel);␊ |
| 84 | ␊ |
| 85 | ␉nicintel_bar = physmap("Intel NIC flash", addr, NICINTEL_MEMMAP_SIZE);␊ |
| 86 | ␉if (nicintel_bar == ERROR_PTR)␊ |
| 87 | ␉␉goto error_out_unmap;␊ |
| 88 | ␊ |
| 89 | ␉/* FIXME: Using pcidev_dev _will_ cause pretty explosions in the future. */␊ |
| 90 | ␉addr = pcidev_validate(pcidev_dev, PCI_BASE_ADDRESS_0, nics_intel);␊ |
| 91 | ␉/* FIXME: This is not an aligned mapping. Use 4k? */␊ |
| 92 | ␉nicintel_control_bar = physmap("Intel NIC control/status reg",␊ |
| 93 | ␉ addr, NICINTEL_CONTROL_MEMMAP_SIZE);␊ |
| 94 | ␉if (nicintel_control_bar == ERROR_PTR)␊ |
| 95 | ␉␉goto error_out;␊ |
| 96 | ␊ |
| 97 | ␉if (register_shutdown(nicintel_shutdown, NULL))␊ |
| 98 | ␉␉return 1;␊ |
| 99 | ␊ |
| 100 | ␉/* FIXME: This register is pretty undocumented in all publicly available␊ |
| 101 | ␉ * documentation from Intel. Let me quote the complete info we have:␊ |
| 102 | ␉ * "Flash Control Register: The Flash Control register allows the CPU to␊ |
| 103 | ␉ * enable writes to an external Flash. The Flash Control Register is a␊ |
| 104 | ␉ * 32-bit field that allows access to an external Flash device."␊ |
| 105 | ␉ * Ah yes, we also know where it is, but we have absolutely _no_ idea␊ |
| 106 | ␉ * what we should do with it. Write 0x0001 because we have nothing␊ |
| 107 | ␉ * better to do with our time.␊ |
| 108 | ␉ */␊ |
| 109 | ␉pci_rmmio_writew(0x0001, nicintel_control_bar + CSR_FCR);␊ |
| 110 | ␊ |
| 111 | ␉max_rom_decode.parallel = NICINTEL_MEMMAP_SIZE;␊ |
| 112 | ␉register_par_programmer(&par_programmer_nicintel, BUS_PARALLEL);␊ |
| 113 | ␊ |
| 114 | ␉return 0;␊ |
| 115 | ␊ |
| 116 | error_out_unmap:␊ |
| 117 | ␉physunmap(nicintel_bar, NICINTEL_MEMMAP_SIZE);␊ |
| 118 | error_out:␊ |
| 119 | ␉pci_cleanup(pacc);␊ |
| 120 | ␉release_io_perms();␊ |
| 121 | ␉return 1;␊ |
| 122 | }␊ |
| 123 | ␊ |
| 124 | static void nicintel_chip_writeb(const struct flashctx *flash, uint8_t val,␊ |
| 125 | ␉␉␉␉ chipaddr addr)␊ |
| 126 | {␊ |
| 127 | ␉pci_mmio_writeb(val, nicintel_bar + (addr & NICINTEL_MEMMAP_MASK));␊ |
| 128 | }␊ |
| 129 | ␊ |
| 130 | static uint8_t nicintel_chip_readb(const struct flashctx *flash,␊ |
| 131 | ␉␉␉␉ const chipaddr addr)␊ |
| 132 | {␊ |
| 133 | ␉return pci_mmio_readb(nicintel_bar + (addr & NICINTEL_MEMMAP_MASK));␊ |
| 134 | }␊ |
| 135 | |
