| 1 | /*␊ |
| 2 | * This file is part of the flashrom project.␊ |
| 3 | *␊ |
| 4 | * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>␊ |
| 5 | *␊ |
| 6 | * This program is free software; you can redistribute it and/or modify␊ |
| 7 | * it under the terms of the GNU General Public License as published by␊ |
| 8 | * the Free Software Foundation; either version 2 of the License, or␊ |
| 9 | * (at your option) any later version.␊ |
| 10 | *␊ |
| 11 | * This program is distributed in the hope that it will be useful,␊ |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of␊ |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the␊ |
| 14 | * GNU General Public License for more details.␊ |
| 15 | *␊ |
| 16 | * You should have received a copy of the GNU General Public License␊ |
| 17 | * along with this program; if not, write to the Free Software␊ |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA␊ |
| 19 | */␊ |
| 20 | ␊ |
| 21 | #if defined(__i386__) || defined(__x86_64__)␊ |
| 22 | ␊ |
| 23 | #include <stdlib.h>␊ |
| 24 | #include "flash.h"␊ |
| 25 | #include "programmer.h"␊ |
| 26 | ␊ |
| 27 | #define BIOS_ROM_ADDR␉␉0x04␊ |
| 28 | #define BIOS_ROM_DATA␉␉0x08␊ |
| 29 | #define INT_STATUS␉␉0x0e␊ |
| 30 | #define INTERNAL_CONFIG␉␉0x00␊ |
| 31 | #define SELECT_REG_WINDOW␉0x800␊ |
| 32 | ␊ |
| 33 | #define PCI_VENDOR_ID_3COM␉0x10b7␊ |
| 34 | ␊ |
| 35 | static uint32_t internal_conf;␊ |
| 36 | static uint16_t id;␊ |
| 37 | ␊ |
| 38 | const struct pcidev_status nics_3com[] = {␊ |
| 39 | ␉/* 3C90xB */␊ |
| 40 | ␉{0x10b7, 0x9055, OK, "3COM", "3C90xB: PCI 10/100 Mbps; shared 10BASE-T/100BASE-TX"},␊ |
| 41 | ␉{0x10b7, 0x9001, NT, "3COM", "3C90xB: PCI 10/100 Mbps; shared 10BASE-T/100BASE-T4" },␊ |
| 42 | ␉{0x10b7, 0x9004, OK, "3COM", "3C90xB: PCI 10BASE-T (TPO)" },␊ |
| 43 | ␉{0x10b7, 0x9005, NT, "3COM", "3C90xB: PCI 10BASE-T/10BASE2/AUI (COMBO)" },␊ |
| 44 | ␉{0x10b7, 0x9006, NT, "3COM", "3C90xB: PCI 10BASE-T/10BASE2 (TPC)" },␊ |
| 45 | ␉{0x10b7, 0x900a, NT, "3COM", "3C90xB: PCI 10BASE-FL" },␊ |
| 46 | ␉{0x10b7, 0x905a, NT, "3COM", "3C90xB: PCI 10BASE-FX" },␊ |
| 47 | ␉{0x10b7, 0x9058, OK, "3COM", "3C905B: Cyclone 10/100/BNC" },␊ |
| 48 | ␊ |
| 49 | ␉/* 3C905C */␊ |
| 50 | ␉{0x10b7, 0x9200, OK, "3COM", "3C905C: EtherLink 10/100 PCI (TX)" },␊ |
| 51 | ␊ |
| 52 | ␉/* 3C980C */␊ |
| 53 | ␉{0x10b7, 0x9805, NT, "3COM", "3C980C: EtherLink Server 10/100 PCI (TX)" },␊ |
| 54 | ␊ |
| 55 | ␉{},␊ |
| 56 | };␊ |
| 57 | ␊ |
| 58 | static void nic3com_chip_writeb(const struct flashctx *flash, uint8_t val,␊ |
| 59 | ␉␉␉␉chipaddr addr);␊ |
| 60 | static uint8_t nic3com_chip_readb(const struct flashctx *flash,␊ |
| 61 | ␉␉␉␉ const chipaddr addr);␊ |
| 62 | static const struct par_programmer par_programmer_nic3com = {␊ |
| 63 | ␉␉.chip_readb␉␉= nic3com_chip_readb,␊ |
| 64 | ␉␉.chip_readw␉␉= fallback_chip_readw,␊ |
| 65 | ␉␉.chip_readl␉␉= fallback_chip_readl,␊ |
| 66 | ␉␉.chip_readn␉␉= fallback_chip_readn,␊ |
| 67 | ␉␉.chip_writeb␉␉= nic3com_chip_writeb,␊ |
| 68 | ␉␉.chip_writew␉␉= fallback_chip_writew,␊ |
| 69 | ␉␉.chip_writel␉␉= fallback_chip_writel,␊ |
| 70 | ␉␉.chip_writen␉␉= fallback_chip_writen,␊ |
| 71 | };␊ |
| 72 | ␊ |
| 73 | static int nic3com_shutdown(void *data)␊ |
| 74 | {␊ |
| 75 | ␉/* 3COM 3C90xB cards need a special fixup. */␊ |
| 76 | ␉if (id == 0x9055 || id == 0x9001 || id == 0x9004 || id == 0x9005␊ |
| 77 | ␉ || id == 0x9006 || id == 0x900a || id == 0x905a || id == 0x9058) {␊ |
| 78 | ␉␉/* Select register window 3 and restore the receiver status. */␊ |
| 79 | ␉␉OUTW(SELECT_REG_WINDOW + 3, io_base_addr + INT_STATUS);␊ |
| 80 | ␉␉OUTL(internal_conf, io_base_addr + INTERNAL_CONFIG);␊ |
| 81 | ␉}␊ |
| 82 | ␊ |
| 83 | ␉pci_cleanup(pacc);␊ |
| 84 | ␉release_io_perms();␊ |
| 85 | ␉return 0;␊ |
| 86 | }␊ |
| 87 | ␊ |
| 88 | int nic3com_init(void)␊ |
| 89 | {␊ |
| 90 | ␉get_io_perms();␊ |
| 91 | ␊ |
| 92 | ␉io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, nics_3com);␊ |
| 93 | ␊ |
| 94 | ␉id = pcidev_dev->device_id;␊ |
| 95 | ␊ |
| 96 | ␉/* 3COM 3C90xB cards need a special fixup. */␊ |
| 97 | ␉if (id == 0x9055 || id == 0x9001 || id == 0x9004 || id == 0x9005␊ |
| 98 | ␉ || id == 0x9006 || id == 0x900a || id == 0x905a || id == 0x9058) {␊ |
| 99 | ␉␉/* Select register window 3 and save the receiver status. */␊ |
| 100 | ␉␉OUTW(SELECT_REG_WINDOW + 3, io_base_addr + INT_STATUS);␊ |
| 101 | ␉␉internal_conf = INL(io_base_addr + INTERNAL_CONFIG);␊ |
| 102 | ␊ |
| 103 | ␉␉/* Set receiver type to MII for full BIOS ROM access. */␊ |
| 104 | ␉␉OUTL((internal_conf & 0xf00fffff) | 0x00600000, io_base_addr);␊ |
| 105 | ␉}␊ |
| 106 | ␊ |
| 107 | ␉/*␊ |
| 108 | ␉ * The lowest 16 bytes of the I/O mapped register space of (most) 3COM␊ |
| 109 | ␉ * cards form a 'register window' into one of multiple (usually 8)␊ |
| 110 | ␉ * register banks. For 3C90xB/3C90xC we need register window/bank 0.␊ |
| 111 | ␉ */␊ |
| 112 | ␉OUTW(SELECT_REG_WINDOW + 0, io_base_addr + INT_STATUS);␊ |
| 113 | ␊ |
| 114 | ␉if (register_shutdown(nic3com_shutdown, NULL))␊ |
| 115 | ␉␉return 1;␊ |
| 116 | ␊ |
| 117 | ␉max_rom_decode.parallel = 128 * 1024;␊ |
| 118 | ␉register_par_programmer(&par_programmer_nic3com, BUS_PARALLEL);␊ |
| 119 | ␊ |
| 120 | ␉return 0;␊ |
| 121 | }␊ |
| 122 | ␊ |
| 123 | static void nic3com_chip_writeb(const struct flashctx *flash, uint8_t val,␊ |
| 124 | ␉␉␉␉chipaddr addr)␊ |
| 125 | {␊ |
| 126 | ␉OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR);␊ |
| 127 | ␉OUTB(val, io_base_addr + BIOS_ROM_DATA);␊ |
| 128 | }␊ |
| 129 | ␊ |
| 130 | static uint8_t nic3com_chip_readb(const struct flashctx *flash,␊ |
| 131 | ␉␉␉␉ const chipaddr addr)␊ |
| 132 | {␊ |
| 133 | ␉OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR);␊ |
| 134 | ␉return INB(io_base_addr + BIOS_ROM_DATA);␊ |
| 135 | }␊ |
| 136 | ␊ |
| 137 | #else␊ |
| 138 | #error PCI port I/O access is not supported on this architecture yet.␊ |
| 139 | #endif␊ |
| 140 | |
