| 1 | /*␊ |
| 2 | * This file is part of the flashrom project.␊ |
| 3 | *␊ |
| 4 | * Copyright (C) 2007, 2008, 2009 Carl-Daniel Hailfinger␊ |
| 5 | * Copyright (C) 2008 Ronald Hoogenboom <ronald@zonnet.nl>␊ |
| 6 | * Copyright (C) 2008 coresystems GmbH␊ |
| 7 | *␊ |
| 8 | * This program is free software; you can redistribute it and/or modify␊ |
| 9 | * it under the terms of the GNU General Public License as published by␊ |
| 10 | * the Free Software Foundation; version 2 of the License.␊ |
| 11 | *␊ |
| 12 | * This program is distributed in the hope that it will be useful,␊ |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of␊ |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the␊ |
| 15 | * GNU General Public License for more details.␊ |
| 16 | *␊ |
| 17 | * You should have received a copy of the GNU General Public License␊ |
| 18 | * along with this program; if not, write to the Free Software␊ |
| 19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA␊ |
| 20 | */␊ |
| 21 | ␊ |
| 22 | /*␊ |
| 23 | * Contains the ITE IT87* SPI specific routines␊ |
| 24 | */␊ |
| 25 | ␊ |
| 26 | #if defined(__i386__) || defined(__x86_64__)␊ |
| 27 | ␊ |
| 28 | #include <string.h>␊ |
| 29 | #include <stdlib.h>␊ |
| 30 | #include "flash.h"␊ |
| 31 | #include "chipdrivers.h"␊ |
| 32 | #include "programmer.h"␊ |
| 33 | #include "spi.h"␊ |
| 34 | ␊ |
| 35 | #define ITE_SUPERIO_PORT1␉0x2e␊ |
| 36 | #define ITE_SUPERIO_PORT2␉0x4e␊ |
| 37 | ␊ |
| 38 | uint16_t it8716f_flashport = 0;␊ |
| 39 | /* use fast 33MHz SPI (<>0) or slow 16MHz (0) */␊ |
| 40 | static int fast_spi = 1;␊ |
| 41 | ␊ |
| 42 | /* Helper functions for most recent ITE IT87xx Super I/O chips */␊ |
| 43 | #define CHIP_ID_BYTE1_REG␉0x20␊ |
| 44 | #define CHIP_ID_BYTE2_REG␉0x21␊ |
| 45 | #define CHIP_VER_REG␉␉0x22␊ |
| 46 | void enter_conf_mode_ite(uint16_t port)␊ |
| 47 | {␊ |
| 48 | ␉OUTB(0x87, port);␊ |
| 49 | ␉OUTB(0x01, port);␊ |
| 50 | ␉OUTB(0x55, port);␊ |
| 51 | ␉if (port == ITE_SUPERIO_PORT1)␊ |
| 52 | ␉␉OUTB(0x55, port);␊ |
| 53 | ␉else␊ |
| 54 | ␉␉OUTB(0xaa, port);␊ |
| 55 | }␊ |
| 56 | ␊ |
| 57 | void exit_conf_mode_ite(uint16_t port)␊ |
| 58 | {␊ |
| 59 | ␉sio_write(port, 0x02, 0x02);␊ |
| 60 | }␊ |
| 61 | ␊ |
| 62 | uint16_t probe_id_ite(uint16_t port)␊ |
| 63 | {␊ |
| 64 | ␉uint16_t id;␊ |
| 65 | ␊ |
| 66 | ␉enter_conf_mode_ite(port);␊ |
| 67 | ␉id = sio_read(port, CHIP_ID_BYTE1_REG) << 8;␊ |
| 68 | ␉id |= sio_read(port, CHIP_ID_BYTE2_REG);␊ |
| 69 | ␉exit_conf_mode_ite(port);␊ |
| 70 | ␊ |
| 71 | ␉return id;␊ |
| 72 | }␊ |
| 73 | ␊ |
| 74 | void probe_superio_ite(void)␊ |
| 75 | {␊ |
| 76 | ␉struct superio s = {};␊ |
| 77 | ␉uint16_t ite_ports[] = {ITE_SUPERIO_PORT1, ITE_SUPERIO_PORT2, 0};␊ |
| 78 | ␉uint16_t *i = ite_ports;␊ |
| 79 | ␊ |
| 80 | ␉s.vendor = SUPERIO_VENDOR_ITE;␊ |
| 81 | ␉for (; *i; i++) {␊ |
| 82 | ␉␉s.port = *i;␊ |
| 83 | ␉␉s.model = probe_id_ite(s.port);␊ |
| 84 | ␉␉switch (s.model >> 8) {␊ |
| 85 | ␉␉case 0x82:␊ |
| 86 | ␉␉case 0x86:␊ |
| 87 | ␉␉case 0x87:␊ |
| 88 | ␉␉␉/* FIXME: Print revision for all models? */␊ |
| 89 | ␉␉␉msg_pdbg("Found ITE Super I/O, ID 0x%04hx on port "␊ |
| 90 | ␉␉␉␉ "0x%x\n", s.model, s.port);␊ |
| 91 | ␉␉␉register_superio(s);␊ |
| 92 | ␉␉␉break;␊ |
| 93 | ␉␉case 0x85:␊ |
| 94 | ␉␉␉msg_pdbg("Found ITE EC, ID 0x%04hx,"␊ |
| 95 | ␉␉␉ "Rev 0x%02x on port 0x%x.\n",␊ |
| 96 | ␉␉␉ s.model, sio_read(s.port, CHIP_VER_REG),␊ |
| 97 | ␉␉␉ s.port);␊ |
| 98 | ␉␉␉register_superio(s);␊ |
| 99 | ␉␉␉break;␊ |
| 100 | ␉␉}␊ |
| 101 | ␉}␊ |
| 102 | ␊ |
| 103 | ␉return;␊ |
| 104 | }␊ |
| 105 | ␊ |
| 106 | static int it8716f_spi_send_command(struct flashctx *flash,␊ |
| 107 | ␉␉␉␉ unsigned int writecnt, unsigned int readcnt,␊ |
| 108 | ␉␉␉␉ const unsigned char *writearr,␊ |
| 109 | ␉␉␉␉ unsigned char *readarr);␊ |
| 110 | static int it8716f_spi_chip_read(struct flashctx *flash, uint8_t *buf,␊ |
| 111 | ␉␉␉␉ unsigned int start, unsigned int len);␊ |
| 112 | static int it8716f_spi_chip_write_256(struct flashctx *flash, uint8_t *buf,␊ |
| 113 | ␉␉␉␉ unsigned int start, unsigned int len);␊ |
| 114 | ␊ |
| 115 | static const struct spi_programmer spi_programmer_it87xx = {␊ |
| 116 | ␉.type␉␉= SPI_CONTROLLER_IT87XX,␊ |
| 117 | ␉.max_data_read␉= MAX_DATA_UNSPECIFIED,␊ |
| 118 | ␉.max_data_write␉= MAX_DATA_UNSPECIFIED,␊ |
| 119 | ␉.command␉= it8716f_spi_send_command,␊ |
| 120 | ␉.multicommand␉= default_spi_send_multicommand,␊ |
| 121 | ␉.read␉␉= it8716f_spi_chip_read,␊ |
| 122 | ␉.write_256␉= it8716f_spi_chip_write_256,␊ |
| 123 | };␊ |
| 124 | ␊ |
| 125 | static uint16_t it87spi_probe(uint16_t port)␊ |
| 126 | {␊ |
| 127 | ␉uint8_t tmp = 0;␊ |
| 128 | ␉char *portpos = NULL;␊ |
| 129 | ␉uint16_t flashport = 0;␊ |
| 130 | ␊ |
| 131 | ␉enter_conf_mode_ite(port);␊ |
| 132 | ␉/* NOLDN, reg 0x24, mask out lowest bit (suspend) */␊ |
| 133 | ␉tmp = sio_read(port, 0x24) & 0xFE;␊ |
| 134 | ␉/* Check if LPC->SPI translation is active. */␊ |
| 135 | ␉if (!(tmp & 0x0e)) {␊ |
| 136 | ␉␉msg_pdbg("No IT87* serial flash segment enabled.\n");␊ |
| 137 | ␉␉exit_conf_mode_ite(port);␊ |
| 138 | ␉␉/* Nothing to do. */␊ |
| 139 | ␉␉return 0;␊ |
| 140 | ␉}␊ |
| 141 | ␉msg_pdbg("Serial flash segment 0x%08x-0x%08x %sabled\n",␊ |
| 142 | ␉␉ 0xFFFE0000, 0xFFFFFFFF, (tmp & 1 << 1) ? "en" : "dis");␊ |
| 143 | ␉msg_pdbg("Serial flash segment 0x%08x-0x%08x %sabled\n",␊ |
| 144 | ␉␉ 0x000E0000, 0x000FFFFF, (tmp & 1 << 1) ? "en" : "dis");␊ |
| 145 | ␉msg_pdbg("Serial flash segment 0x%08x-0x%08x %sabled\n",␊ |
| 146 | ␉␉ 0xFFEE0000, 0xFFEFFFFF, (tmp & 1 << 2) ? "en" : "dis");␊ |
| 147 | ␉msg_pdbg("Serial flash segment 0x%08x-0x%08x %sabled\n",␊ |
| 148 | ␉␉ 0xFFF80000, 0xFFFEFFFF, (tmp & 1 << 3) ? "en" : "dis");␊ |
| 149 | ␉msg_pdbg("LPC write to serial flash %sabled\n",␊ |
| 150 | ␉␉ (tmp & 1 << 4) ? "en" : "dis");␊ |
| 151 | ␉/* The LPC->SPI force write enable below only makes sense for␊ |
| 152 | ␉ * non-programmer mode.␊ |
| 153 | ␉ */␊ |
| 154 | ␉/* If any serial flash segment is enabled, enable writing. */␊ |
| 155 | ␉if ((tmp & 0xe) && (!(tmp & 1 << 4))) {␊ |
| 156 | ␉␉msg_pdbg("Enabling LPC write to serial flash\n");␊ |
| 157 | ␉␉tmp |= 1 << 4;␊ |
| 158 | ␉␉sio_write(port, 0x24, tmp);␊ |
| 159 | ␉}␊ |
| 160 | ␉msg_pdbg("Serial flash pin %i\n", (tmp & 1 << 5) ? 87 : 29);␊ |
| 161 | ␉/* LDN 0x7, reg 0x64/0x65 */␊ |
| 162 | ␉sio_write(port, 0x07, 0x7);␊ |
| 163 | ␉flashport = sio_read(port, 0x64) << 8;␊ |
| 164 | ␉flashport |= sio_read(port, 0x65);␊ |
| 165 | ␉msg_pdbg("Serial flash port 0x%04x\n", flashport);␊ |
| 166 | ␉/* Non-default port requested? */␊ |
| 167 | ␉portpos = extract_programmer_param("it87spiport");␊ |
| 168 | ␉if (portpos) {␊ |
| 169 | ␉␉char *endptr = NULL;␊ |
| 170 | ␉␉unsigned long forced_flashport;␊ |
| 171 | ␉␉forced_flashport = strtoul(portpos, &endptr, 0);␊ |
| 172 | ␉␉/* Port 0, port >0x1000, unaligned ports and garbage strings␊ |
| 173 | ␉␉ * are rejected.␊ |
| 174 | ␉␉ */␊ |
| 175 | ␉␉if (!forced_flashport || (forced_flashport >= 0x1000) ||␊ |
| 176 | ␉␉ (forced_flashport & 0x7) || (*endptr != '\0')) {␊ |
| 177 | ␉␉␉/* Using ports below 0x100 is a really bad idea, and␊ |
| 178 | ␉␉␉ * should only be done if no port between 0x100 and␊ |
| 179 | ␉␉␉ * 0xff8 works due to routing issues.␊ |
| 180 | ␉␉␉ */␊ |
| 181 | ␉␉␉msg_perr("Error: it87spiport specified, but no valid "␊ |
| 182 | ␉␉␉␉ "port specified.\nPort must be a multiple of "␊ |
| 183 | ␉␉␉␉ "0x8 and lie between 0x100 and 0xff8.\n");␊ |
| 184 | ␉␉␉free(portpos);␊ |
| 185 | ␉␉␉return 1;␊ |
| 186 | ␉␉} else {␊ |
| 187 | ␉␉␉flashport = (uint16_t)forced_flashport;␊ |
| 188 | ␉␉␉msg_pinfo("Forcing serial flash port 0x%04x\n",␊ |
| 189 | ␉␉␉␉ flashport);␊ |
| 190 | ␉␉␉sio_write(port, 0x64, (flashport >> 8));␊ |
| 191 | ␉␉␉sio_write(port, 0x65, (flashport & 0xff));␊ |
| 192 | ␉␉}␊ |
| 193 | ␉}␊ |
| 194 | ␉free(portpos);␊ |
| 195 | ␉exit_conf_mode_ite(port);␊ |
| 196 | ␉it8716f_flashport = flashport;␊ |
| 197 | ␉if (internal_buses_supported & BUS_SPI)␊ |
| 198 | ␉␉msg_pdbg("Overriding chipset SPI with IT87 SPI.\n");␊ |
| 199 | ␉/* FIXME: Add the SPI bus or replace the other buses with it? */␊ |
| 200 | ␉register_spi_programmer(&spi_programmer_it87xx);␊ |
| 201 | ␉return 0;␊ |
| 202 | }␊ |
| 203 | ␊ |
| 204 | int init_superio_ite(void)␊ |
| 205 | {␊ |
| 206 | ␉int i;␊ |
| 207 | ␉int ret = 0;␊ |
| 208 | ␊ |
| 209 | ␉for (i = 0; i < superio_count; i++) {␊ |
| 210 | ␉␉if (superios[i].vendor != SUPERIO_VENDOR_ITE)␊ |
| 211 | ␉␉␉continue;␊ |
| 212 | ␊ |
| 213 | ␉␉switch (superios[i].model) {␊ |
| 214 | ␉␉case 0x8500:␊ |
| 215 | ␉␉case 0x8502:␊ |
| 216 | ␉␉case 0x8510:␊ |
| 217 | ␉␉case 0x8511:␊ |
| 218 | ␉␉case 0x8512:␊ |
| 219 | ␉␉␉/* FIXME: This should be enabled, but we need a check␊ |
| 220 | ␉␉␉ * for laptop whitelisting due to the amount of things␊ |
| 221 | ␉␉␉ * which can go wrong if the EC firmware does not␊ |
| 222 | ␉␉␉ * implement the interface we want.␊ |
| 223 | ␉␉␉ */␊ |
| 224 | ␉␉␉//it85xx_spi_init(superios[i]);␊ |
| 225 | ␉␉␉break;␊ |
| 226 | ␉␉case 0x8705:␊ |
| 227 | ␉␉␉ret |= it8705f_write_enable(superios[i].port);␊ |
| 228 | ␉␉␉break;␊ |
| 229 | ␉␉case 0x8716:␊ |
| 230 | ␉␉case 0x8718:␊ |
| 231 | ␉␉case 0x8720:␊ |
| 232 | ␉␉␉ret |= it87spi_probe(superios[i].port);␊ |
| 233 | ␉␉␉break;␊ |
| 234 | ␉␉default:␊ |
| 235 | ␉␉␉msg_pdbg("Super I/O ID 0x%04hx is not on the list of "␊ |
| 236 | ␉␉␉␉ "flash capable controllers.\n",␊ |
| 237 | ␉␉␉␉ superios[i].model);␊ |
| 238 | ␉␉}␊ |
| 239 | ␉}␊ |
| 240 | ␉return ret;␊ |
| 241 | }␊ |
| 242 | ␊ |
| 243 | /*␊ |
| 244 | * The IT8716F only supports commands with length 1,2,4,5 bytes including␊ |
| 245 | * command byte and can not read more than 3 bytes from the device.␊ |
| 246 | *␊ |
| 247 | * This function expects writearr[0] to be the first byte sent to the device,␊ |
| 248 | * whereas the IT8716F splits commands internally into address and non-address␊ |
| 249 | * commands with the address in inverse wire order. That's why the register␊ |
| 250 | * ordering in case 4 and 5 may seem strange.␊ |
| 251 | */␊ |
| 252 | static int it8716f_spi_send_command(struct flashctx *flash,␊ |
| 253 | ␉␉␉␉ unsigned int writecnt, unsigned int readcnt,␊ |
| 254 | ␉␉␉␉ const unsigned char *writearr,␊ |
| 255 | ␉␉␉␉ unsigned char *readarr)␊ |
| 256 | {␊ |
| 257 | ␉uint8_t busy, writeenc;␊ |
| 258 | ␉int i;␊ |
| 259 | ␊ |
| 260 | ␉do {␊ |
| 261 | ␉␉busy = INB(it8716f_flashport) & 0x80;␊ |
| 262 | ␉} while (busy);␊ |
| 263 | ␉if (readcnt > 3) {␊ |
| 264 | ␉␉msg_pinfo("%s called with unsupported readcnt %i.\n",␊ |
| 265 | ␉␉␉ __func__, readcnt);␊ |
| 266 | ␉␉return SPI_INVALID_LENGTH;␊ |
| 267 | ␉}␊ |
| 268 | ␉switch (writecnt) {␊ |
| 269 | ␉case 1:␊ |
| 270 | ␉␉OUTB(writearr[0], it8716f_flashport + 1);␊ |
| 271 | ␉␉writeenc = 0x0;␊ |
| 272 | ␉␉break;␊ |
| 273 | ␉case 2:␊ |
| 274 | ␉␉OUTB(writearr[0], it8716f_flashport + 1);␊ |
| 275 | ␉␉OUTB(writearr[1], it8716f_flashport + 7);␊ |
| 276 | ␉␉writeenc = 0x1;␊ |
| 277 | ␉␉break;␊ |
| 278 | ␉case 4:␊ |
| 279 | ␉␉OUTB(writearr[0], it8716f_flashport + 1);␊ |
| 280 | ␉␉OUTB(writearr[1], it8716f_flashport + 4);␊ |
| 281 | ␉␉OUTB(writearr[2], it8716f_flashport + 3);␊ |
| 282 | ␉␉OUTB(writearr[3], it8716f_flashport + 2);␊ |
| 283 | ␉␉writeenc = 0x2;␊ |
| 284 | ␉␉break;␊ |
| 285 | ␉case 5:␊ |
| 286 | ␉␉OUTB(writearr[0], it8716f_flashport + 1);␊ |
| 287 | ␉␉OUTB(writearr[1], it8716f_flashport + 4);␊ |
| 288 | ␉␉OUTB(writearr[2], it8716f_flashport + 3);␊ |
| 289 | ␉␉OUTB(writearr[3], it8716f_flashport + 2);␊ |
| 290 | ␉␉OUTB(writearr[4], it8716f_flashport + 7);␊ |
| 291 | ␉␉writeenc = 0x3;␊ |
| 292 | ␉␉break;␊ |
| 293 | ␉default:␊ |
| 294 | ␉␉msg_pinfo("%s called with unsupported writecnt %i.\n",␊ |
| 295 | ␉␉␉ __func__, writecnt);␊ |
| 296 | ␉␉return SPI_INVALID_LENGTH;␊ |
| 297 | ␉}␊ |
| 298 | ␉/*␊ |
| 299 | ␉ * Start IO, 33 or 16 MHz, readcnt input bytes, writecnt output bytes.␊ |
| 300 | ␉ * Note:␊ |
| 301 | ␉ * We can't use writecnt directly, but have to use a strange encoding.␊ |
| 302 | ␉ */␊ |
| 303 | ␉OUTB(((0x4 + (fast_spi ? 1 : 0)) << 4)␊ |
| 304 | ␉␉| ((readcnt & 0x3) << 2) | (writeenc), it8716f_flashport);␊ |
| 305 | ␊ |
| 306 | ␉if (readcnt > 0) {␊ |
| 307 | ␉␉do {␊ |
| 308 | ␉␉␉busy = INB(it8716f_flashport) & 0x80;␊ |
| 309 | ␉␉} while (busy);␊ |
| 310 | ␊ |
| 311 | ␉␉for (i = 0; i < readcnt; i++)␊ |
| 312 | ␉␉␉readarr[i] = INB(it8716f_flashport + 5 + i);␊ |
| 313 | ␉}␊ |
| 314 | ␊ |
| 315 | ␉return 0;␊ |
| 316 | }␊ |
| 317 | ␊ |
| 318 | /* Page size is usually 256 bytes */␊ |
| 319 | static int it8716f_spi_page_program(struct flashctx *flash, uint8_t *buf,␊ |
| 320 | ␉␉␉␉ unsigned int start)␊ |
| 321 | {␊ |
| 322 | ␉unsigned int i;␊ |
| 323 | ␉int result;␊ |
| 324 | ␉chipaddr bios = flash->virtual_memory;␊ |
| 325 | ␊ |
| 326 | ␉result = spi_write_enable(flash);␊ |
| 327 | ␉if (result)␊ |
| 328 | ␉␉return result;␊ |
| 329 | ␉/* FIXME: The command below seems to be redundant or wrong. */␊ |
| 330 | ␉OUTB(0x06, it8716f_flashport + 1);␊ |
| 331 | ␉OUTB(((2 + (fast_spi ? 1 : 0)) << 4), it8716f_flashport);␊ |
| 332 | ␉for (i = 0; i < flash->page_size; i++)␊ |
| 333 | ␉␉chip_writeb(flash, buf[i], bios + start + i);␊ |
| 334 | ␉OUTB(0, it8716f_flashport);␊ |
| 335 | ␉/* Wait until the Write-In-Progress bit is cleared.␊ |
| 336 | ␉ * This usually takes 1-10 ms, so wait in 1 ms steps.␊ |
| 337 | ␉ */␊ |
| 338 | ␉while (spi_read_status_register(flash) & JEDEC_RDSR_BIT_WIP)␊ |
| 339 | ␉␉programmer_delay(1000);␊ |
| 340 | ␉return 0;␊ |
| 341 | }␊ |
| 342 | ␊ |
| 343 | /*␊ |
| 344 | * IT8716F only allows maximum of 512 kb SPI mapped to LPC memory cycles␊ |
| 345 | * Need to read this big flash using firmware cycles 3 byte at a time.␊ |
| 346 | */␊ |
| 347 | static int it8716f_spi_chip_read(struct flashctx *flash, uint8_t *buf,␊ |
| 348 | ␉␉␉␉ unsigned int start, unsigned int len)␊ |
| 349 | {␊ |
| 350 | ␉fast_spi = 0;␊ |
| 351 | ␊ |
| 352 | ␉/* FIXME: Check if someone explicitly requested to use IT87 SPI although␊ |
| 353 | ␉ * the mainboard does not use IT87 SPI translation. This should be done␊ |
| 354 | ␉ * via a programmer parameter for the internal programmer.␊ |
| 355 | ␉ */␊ |
| 356 | ␉if ((flash->total_size * 1024 > 512 * 1024)) {␊ |
| 357 | ␉␉spi_read_chunked(flash, buf, start, len, 3);␊ |
| 358 | ␉} else {␊ |
| 359 | ␉␉read_memmapped(flash, buf, start, len);␊ |
| 360 | ␉}␊ |
| 361 | ␊ |
| 362 | ␉return 0;␊ |
| 363 | }␊ |
| 364 | ␊ |
| 365 | static int it8716f_spi_chip_write_256(struct flashctx *flash, uint8_t *buf,␊ |
| 366 | ␉␉␉␉ unsigned int start, unsigned int len)␊ |
| 367 | {␊ |
| 368 | ␉/*␊ |
| 369 | ␉ * IT8716F only allows maximum of 512 kb SPI chip size for memory␊ |
| 370 | ␉ * mapped access. It also can't write more than 1+3+256 bytes at once,␊ |
| 371 | ␉ * so page_size > 256 bytes needs a fallback.␊ |
| 372 | ␉ * FIXME: Split too big page writes into chunks IT87* can handle instead␊ |
| 373 | ␉ * of degrading to single-byte program.␊ |
| 374 | ␉ * FIXME: Check if someone explicitly requested to use IT87 SPI although␊ |
| 375 | ␉ * the mainboard does not use IT87 SPI translation. This should be done␊ |
| 376 | ␉ * via a programmer parameter for the internal programmer.␊ |
| 377 | ␉ */␊ |
| 378 | ␉if ((flash->total_size * 1024 > 512 * 1024) ||␊ |
| 379 | ␉ (flash->page_size > 256)) {␊ |
| 380 | ␉␉spi_chip_write_1(flash, buf, start, len);␊ |
| 381 | ␉} else {␊ |
| 382 | ␉␉unsigned int lenhere;␊ |
| 383 | ␊ |
| 384 | ␉␉if (start % flash->page_size) {␊ |
| 385 | ␉␉␉/* start to the end of the page or to start + len,␊ |
| 386 | ␉␉␉ * whichever is smaller.␊ |
| 387 | ␉␉␉ */␊ |
| 388 | ␉␉␉lenhere = min(len, flash->page_size - start % flash->page_size);␊ |
| 389 | ␉␉␉spi_chip_write_1(flash, buf, start, lenhere);␊ |
| 390 | ␉␉␉start += lenhere;␊ |
| 391 | ␉␉␉len -= lenhere;␊ |
| 392 | ␉␉␉buf += lenhere;␊ |
| 393 | ␉␉}␊ |
| 394 | ␊ |
| 395 | ␉␉while (len >= flash->page_size) {␊ |
| 396 | ␉␉␉it8716f_spi_page_program(flash, buf, start);␊ |
| 397 | ␉␉␉start += flash->page_size;␊ |
| 398 | ␉␉␉len -= flash->page_size;␊ |
| 399 | ␉␉␉buf += flash->page_size;␊ |
| 400 | ␉␉}␊ |
| 401 | ␉␉if (len)␊ |
| 402 | ␉␉␉spi_chip_write_1(flash, buf, start, len);␊ |
| 403 | ␉}␊ |
| 404 | ␊ |
| 405 | ␉return 0;␊ |
| 406 | }␊ |
| 407 | ␊ |
| 408 | #endif␊ |
| 409 | |
