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1/*␊
2 * This file is part of the flashrom project.␊
3 *␊
4 * Copyright (c) 2010 Matthias Wenzel <bios at mazzoo dot de>␊
5 * Copyright (c) 2011 Stefan Tauner␊
6 *␊
7 * This program is free software; you can redistribute it and/or modify␊
8 * it under the terms of the GNU General Public License as published by␊
9 * the Free Software Foundation; either version 2 of the License, or␊
10 * (at your option) any later version.␊
11 *␊
12 * This program is distributed in the hope that it will be useful,␊
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of␊
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the␊
15 * GNU General Public License for more details.␊
16 *␊
17 * You should have received a copy of the GNU General Public License␊
18 * along with this program; if not, write to the Free Software␊
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA␊
20 */␊
21␊
22#if defined(__i386__) || defined(__x86_64__)␊
23#ifndef __ICH_DESCRIPTORS_H__␊
24#define __ICH_DESCRIPTORS_H__ 1␊
25␊
26#include <stdint.h>␊
27#include "programmer.h" /* for enum ich_chipset */␊
28␊
29/* FIXME: Replace with generic return codes */␊
30#define ICH_RET_OK␉0␊
31#define ICH_RET_ERR␉-1␊
32#define ICH_RET_WARN␉-2␊
33#define ICH_RET_PARAM␉-3␊
34#define ICH_RET_OOB␉-4␊
35␊
36#define ICH9_REG_FDOC␉␉0xB0␉/* 32 Bits Flash Descriptor Observability Control */␊
37␉␉␉␉␉/* 0-1: reserved */␊
38#define FDOC_FDSI_OFF␉␉2␉/* 2-11: Flash Descriptor Section Index */␊
39#define FDOC_FDSI␉␉(0x3f << FDOC_FDSI_OFF)␊
40#define FDOC_FDSS_OFF␉␉12␉/* 12-14: Flash Descriptor Section Select */␊
41#define FDOC_FDSS␉␉(0x3 << FDOC_FDSS_OFF)␊
42␉␉␉␉␉/* 15-31: reserved */␊
43␊
44#define ICH9_REG_FDOD␉␉0xB4␉/* 32 Bits Flash Descriptor Observability Data */␊
45␊
46/* Field locations and semantics for LVSCC, UVSCC and related words in the flash␊
47 * descriptor are equal therefore they all share the same macros below. */␊
48#define VSCC_BES_OFF␉␉0␉/* 0-1: Block/Sector Erase Size */␊
49#define VSCC_BES␉␉␉(0x3 << VSCC_BES_OFF)␊
50#define VSCC_WG_OFF␉␉2␉/* 2: Write Granularity */␊
51#define VSCC_WG␉␉␉␉(0x1 << VSCC_WG_OFF)␊
52#define VSCC_WSR_OFF␉␉3␉/* 3: Write Status Required */␊
53#define VSCC_WSR␉␉␉(0x1 << VSCC_WSR_OFF)␊
54#define VSCC_WEWS_OFF␉␉4␉/* 4: Write Enable on Write Status */␊
55#define VSCC_WEWS␉␉␉(0x1 << VSCC_WEWS_OFF)␊
56␉␉␉␉␉/* 5-7: reserved */␊
57#define VSCC_EO_OFF␉␉8␉/* 8-15: Erase Opcode */␊
58#define VSCC_EO␉␉␉␉(0xff << VSCC_EO_OFF)␊
59␉␉␉␉␉/* 16-22: reserved */␊
60#define VSCC_VCL_OFF␉␉23␉/* 23: Vendor Component Lock */␊
61#define VSCC_VCL␉␉␉(0x1 << VSCC_VCL_OFF)␊
62␉␉␉␉␉/* 24-31: reserved */␊
63␊
64#define ICH_FREG_BASE(flreg) (((flreg) << 12) & 0x01fff000)␊
65#define ICH_FREG_LIMIT(flreg) (((flreg) >> 4) & 0x01fff000)␊
66␊
67void prettyprint_ich_reg_vscc(uint32_t reg_val, int verbosity);␊
68␊
69struct ich_desc_content {␊
70␉uint32_t FLVALSIG;␉/* 0x00 */␊
71␉union {␉␉␉/* 0x04 */␊
72␉␉uint32_t FLMAP0;␊
73␉␉struct {␊
74␉␉␉uint32_t FCBA␉:8, /* Flash Component Base Address */␊
75␉␉␉␉ NC␉:2, /* Number Of Components */␊
76␉␉␉␉␉:6,␊
77␉␉␉␉ FRBA␉:8, /* Flash Region Base Address */␊
78␉␉␉␉ NR␉:3, /* Number Of Regions */␊
79␉␉␉␉␉:5;␊
80␉␉};␊
81␉};␊
82␉union {␉␉␉/* 0x08 */␊
83␉␉uint32_t FLMAP1;␊
84␉␉struct {␊
85␉␉␉uint32_t FMBA␉:8, /* Flash Master Base Address */␊
86␉␉␉␉ NM␉:3, /* Number Of Masters */␊
87␉␉␉␉␉:5,␊
88␉␉␉␉ FISBA␉:8, /* Flash ICH Strap Base Address */␊
89␉␉␉␉ ISL␉:8; /* ICH Strap Length */␊
90␉␉};␊
91␉};␊
92␉union {␉␉␉/* 0x0c */␊
93␉␉uint32_t FLMAP2;␊
94␉␉struct {␊
95␉␉␉uint32_t FMSBA␉:8, /* Flash (G)MCH Strap Base Addr. */␊
96␉␉␉␉ MSL␉:8, /* MCH Strap Length */␊
97␉␉␉␉␉:16;␊
98␉␉};␊
99␉};␊
100};␊
101␊
102struct ich_desc_component {␊
103␉union {␉␉␉/* 0x00 */␊
104␉␉uint32_t FLCOMP; /* Flash Components Register */␊
105␉␉struct {␊
106␉␉␉uint32_t comp1_density␉:3,␊
107␉␉␉␉ comp2_density␉:3,␊
108␉␉␉␉␉␉:11,␊
109␉␉␉␉ freq_read␉:3,␊
110␉␉␉␉ fastread␉:1,␊
111␉␉␉␉ freq_fastread␉:3,␊
112␉␉␉␉ freq_write␉:3,␊
113␉␉␉␉ freq_read_id␉:3,␊
114␉␉␉␉␉␉:2;␊
115␉␉};␊
116␉};␊
117␉union {␉␉␉/* 0x04 */␊
118␉␉uint32_t FLILL; /* Flash Invalid Instructions Register */␊
119␉␉struct {␊
120␉␉␉uint32_t invalid_instr0␉:8,␊
121␉␉␉␉ invalid_instr1␉:8,␊
122␉␉␉␉ invalid_instr2␉:8,␊
123␉␉␉␉ invalid_instr3␉:8;␊
124␉␉};␊
125␉};␊
126␉union {␉␉␉/* 0x08 */␊
127␉␉uint32_t FLPB; /* Flash Partition Boundary Register */␊
128␉␉struct {␊
129␉␉␉uint32_t FPBA␉:13, /* Flash Partition Boundary Addr */␊
130␉␉␉␉␉:19;␊
131␉␉};␊
132␉};␊
133};␊
134␊
135struct ich_desc_region {␊
136␉union {␊
137␉␉uint32_t FLREGs[5];␊
138␉␉struct {␊
139␉␉␉struct { /* FLREG0 Flash Descriptor */␊
140␉␉␉␉uint32_t reg0_base␉:13,␊
141␉␉␉␉␉␉␉:3,␊
142␉␉␉␉␉ reg0_limit␉:13,␊
143␉␉␉␉␉␉␉:3;␊
144␉␉␉};␊
145␉␉␉struct { /* FLREG1 BIOS */␊
146␉␉␉␉uint32_t reg1_base␉:13,␊
147␉␉␉␉␉␉␉:3,␊
148␉␉␉␉␉ reg1_limit␉:13,␊
149␉␉␉␉␉␉␉:3;␊
150␉␉␉};␊
151␉␉␉struct { /* FLREG2 ME */␊
152␉␉␉␉uint32_t reg2_base␉:13,␊
153␉␉␉␉␉␉␉:3,␊
154␉␉␉␉␉ reg2_limit␉:13,␊
155␉␉␉␉␉␉␉:3;␊
156␉␉␉};␊
157␉␉␉struct { /* FLREG3 GbE */␊
158␉␉␉␉uint32_t reg3_base␉:13,␊
159␉␉␉␉␉␉␉:3,␊
160␉␉␉␉␉ reg3_limit␉:13,␊
161␉␉␉␉␉␉␉:3;␊
162␉␉␉};␊
163␉␉␉struct { /* FLREG4 Platform */␊
164␉␉␉␉uint32_t reg4_base␉:13,␊
165␉␉␉␉␉␉␉:3,␊
166␉␉␉␉␉ reg4_limit␉:13,␊
167␉␉␉␉␉␉␉:3;␊
168␉␉␉};␊
169␉␉};␊
170␉};␊
171};␊
172␊
173struct ich_desc_master {␊
174␉union {␊
175␉␉uint32_t FLMSTR1;␊
176␉␉struct {␊
177␉␉␉uint32_t BIOS_req_ID␉:16,␊
178␉␉␉␉ BIOS_descr_r␉:1,␊
179␉␉␉␉ BIOS_BIOS_r␉:1,␊
180␉␉␉␉ BIOS_ME_r␉:1,␊
181␉␉␉␉ BIOS_GbE_r␉:1,␊
182␉␉␉␉ BIOS_plat_r␉:1,␊
183␉␉␉␉␉␉:3,␊
184␉␉␉␉ BIOS_descr_w␉:1,␊
185␉␉␉␉ BIOS_BIOS_w␉:1,␊
186␉␉␉␉ BIOS_ME_w␉:1,␊
187␉␉␉␉ BIOS_GbE_w␉:1,␊
188␉␉␉␉ BIOS_plat_w␉:1,␊
189␉␉␉␉␉␉:3;␊
190␉␉};␊
191␉};␊
192␉union {␊
193␉␉uint32_t FLMSTR2;␊
194␉␉struct {␊
195␉␉␉uint32_t ME_req_ID␉:16,␊
196␉␉␉␉ ME_descr_r␉:1,␊
197␉␉␉␉ ME_BIOS_r␉:1,␊
198␉␉␉␉ ME_ME_r␉:1,␊
199␉␉␉␉ ME_GbE_r␉:1,␊
200␉␉␉␉ ME_plat_r␉:1,␊
201␉␉␉␉␉␉:3,␊
202␉␉␉␉ ME_descr_w␉:1,␊
203␉␉␉␉ ME_BIOS_w␉:1,␊
204␉␉␉␉ ME_ME_w␉:1,␊
205␉␉␉␉ ME_GbE_w␉:1,␊
206␉␉␉␉ ME_plat_w␉:1,␊
207␉␉␉␉␉␉:3;␊
208␉␉};␊
209␉};␊
210␉union {␊
211␉␉uint32_t FLMSTR3;␊
212␉␉struct {␊
213␉␉␉uint32_t GbE_req_ID␉:16,␊
214␉␉␉␉ GbE_descr_r␉:1,␊
215␉␉␉␉ GbE_BIOS_r␉:1,␊
216␉␉␉␉ GbE_ME_r␉:1,␊
217␉␉␉␉ GbE_GbE_r␉:1,␊
218␉␉␉␉ GbE_plat_r␉:1,␊
219␉␉␉␉␉␉:3,␊
220␉␉␉␉ GbE_descr_w␉:1,␊
221␉␉␉␉ GbE_BIOS_w␉:1,␊
222␉␉␉␉ GbE_ME_w␉:1,␊
223␉␉␉␉ GbE_GbE_w␉:1,␊
224␉␉␉␉ GbE_plat_w␉:1,␊
225␉␉␉␉␉␉:3;␊
226␉␉};␊
227␉};␊
228};␊
229␊
230#ifdef ICH_DESCRIPTORS_FROM_DUMP␊
231struct ich_desc_north_strap {␊
232␉union {␊
233␉␉uint32_t STRPs[1]; /* current maximum: ich8 */␊
234␉␉struct { /* ich8 */␊
235␉␉␉struct { /* STRP2 (in the datasheet) */␊
236␉␉␉␉uint32_t MDB␉␉␉:1,␊
237␉␉␉␉␉␉␉␉:31;␊
238␉␉␉};␊
239␉␉} ich8;␊
240␉};␊
241};␊
242␊
243struct ich_desc_south_strap {␊
244␉union {␊
245␉␉uint32_t STRPs[16]; /* current maximum: ibex peak */␊
246␉␉struct { /* ich8 */␊
247␉␉␉struct { /* STRP1 */␊
248␉␉␉␉uint32_t ME_DISABLE␉␉:1,␊
249␉␉␉␉␉␉␉␉:6,␊
250␉␉␉␉␉ TCOMODE␉␉:1,␊
251␉␉␉␉␉ ASD␉␉␉:7,␊
252␉␉␉␉␉ BMCMODE␉␉:1,␊
253␉␉␉␉␉␉␉␉:3,␊
254␉␉␉␉␉ GLAN_PCIE_SEL␉␉:1,␊
255␉␉␉␉␉ GPIO12_SEL␉␉:2,␊
256␉␉␉␉␉ SPICS1_LANPHYPC_SEL␉:1,␊
257␉␉␉␉␉ MESM2SEL␉␉:1,␊
258␉␉␉␉␉␉␉␉:1,␊
259␉␉␉␉␉ ASD2␉␉␉:7;␊
260␉␉␉};␊
261␉␉} ich8;␊
262␉␉struct { /* ibex peak */␊
263␉␉␉struct { /* STRP0 */␊
264␉␉␉␉uint32_t␉␉␉:1,␊
265␉␉␉␉␉ cs_ss2␉␉␉:1,␊
266␉␉␉␉␉␉␉␉:5,␊
267␉␉␉␉␉ SMB_EN␉␉␉:1,␊
268␉␉␉␉␉ SML0_EN␉␉:1,␊
269␉␉␉␉␉ SML1_EN␉␉:1,␊
270␉␉␉␉␉ SML1FRQ␉␉:2,␊
271␉␉␉␉␉ SMB0FRQ␉␉:2,␊
272␉␉␉␉␉ SML0FRQ␉␉:2,␊
273␉␉␉␉␉␉␉␉:4,␊
274␉␉␉␉␉ LANPHYPC_GP12_SEL␉:1,␊
275␉␉␉␉␉ cs_ss1␉␉␉:1,␊
276␉␉␉␉␉␉␉␉:2,␊
277␉␉␉␉␉ DMI_REQID_DIS␉␉:1,␊
278␉␉␉␉␉␉␉␉:4,␊
279␉␉␉␉␉ BBBS␉␉␉:2,␊
280␉␉␉␉␉␉␉␉:1;␊
281␉␉␉};␊
282␉␉␉struct { /* STRP1 */␊
283␉␉␉␉uint32_t cs_ss3␉␉␉:4,␊
284␉␉␉␉␉␉␉␉:28;␊
285␉␉␉};␊
286␉␉␉struct { /* STRP2 */␊
287␉␉␉␉uint32_t␉␉␉:8,␊
288␉␉␉␉␉ MESMASDEN␉␉:1,␊
289␉␉␉␉␉ MESMASDA␉␉:7,␊
290␉␉␉␉␉␉␉␉:8,␊
291␉␉␉␉␉ MESMI2CEN␉␉:1,␊
292␉␉␉␉␉ MESMI2CA␉␉:7;␊
293␉␉␉};␊
294␉␉␉struct { /* STRP3 */␊
295␉␉␉␉uint32_t␉␉␉:32;␊
296␉␉␉};␊
297␉␉␉struct { /* STRP4 */␊
298␉␉␉␉uint32_t PHYCON␉␉␉:2,␊
299␉␉␉␉␉␉␉␉:6,␊
300␉␉␉␉␉ GBEMAC_SMBUS_ADDR_EN␉:1,␊
301␉␉␉␉␉ GBEMAC_SMBUS_ADDR␉:7,␊
302␉␉␉␉␉␉␉␉:1,␊
303␉␉␉␉␉ GBEPHY_SMBUS_ADDR␉:7,␊
304␉␉␉␉␉␉␉␉:8;␊
305␉␉␉};␊
306␉␉␉struct { /* STRP5 */␊
307␉␉␉␉uint32_t␉␉␉:32;␊
308␉␉␉};␊
309␉␉␉struct { /* STRP6 */␊
310␉␉␉␉uint32_t␉␉␉:32;␊
311␉␉␉};␊
312␉␉␉struct { /* STRP7 */␊
313␉␉␉␉uint32_t MESMA2UDID_VENDOR␉:16,␊
314␉␉␉␉␉ MESMA2UDID_DEVICE␉:16;␊
315␉␉␉};␊
316␉␉␉struct { /* STRP8 */␊
317␉␉␉␉uint32_t␉␉␉:32;␊
318␉␉␉};␊
319␉␉␉struct { /* STRP9 */␊
320␉␉␉␉uint32_t PCIEPCS1␉␉:2,␊
321␉␉␉␉␉ PCIEPCS2␉␉:2,␊
322␉␉␉␉␉ PCIELR1␉␉:1,␊
323␉␉␉␉␉ PCIELR2␉␉:1,␊
324␉␉␉␉␉ DMILR␉␉␉:1,␊
325␉␉␉␉␉␉␉␉:1,␊
326␉␉␉␉␉ PHY_PCIEPORTSEL␉:3,␊
327␉␉␉␉␉ PHY_PCIE_EN␉␉:1,␊
328␉␉␉␉␉␉␉␉:20;␊
329␉␉␉};␊
330␉␉␉struct { /* STRP10 */␊
331␉␉␉␉uint32_t␉␉␉:1,␊
332␉␉␉␉␉ ME_BOOT_FLASH␉␉:1,␊
333␉␉␉␉␉ cs_ss5␉␉␉:1,␊
334␉␉␉␉␉ VE_EN␉␉␉:1,␊
335␉␉␉␉␉␉␉␉:4,␊
336␉␉␉␉␉ MMDDE␉␉␉:1,␊
337␉␉␉␉␉ MMADDR␉␉␉:7,␊
338␉␉␉␉␉ cs_ss7␉␉␉:1,␊
339␉␉␉␉␉␉␉␉:1,␊
340␉␉␉␉␉ ICC_SEL␉␉:3,␊
341␉␉␉␉␉ MER_CL1␉␉:1,␊
342␉␉␉␉␉␉␉␉:10;␊
343␉␉␉};␊
344␉␉␉struct { /* STRP11 */␊
345␉␉␉␉uint32_t SML1GPAEN␉␉:1,␊
346␉␉␉␉␉ SML1GPA␉␉:7,␊
347␉␉␉␉␉␉␉␉:16,␊
348␉␉␉␉␉ SML1I2CAEN␉␉:1,␊
349␉␉␉␉␉ SML1I2CA␉␉:7;␊
350␉␉␉};␊
351␉␉␉struct { /* STRP12 */␊
352␉␉␉␉uint32_t␉␉␉:32;␊
353␉␉␉};␊
354␉␉␉struct { /* STRP13 */␊
355␉␉␉␉uint32_t␉␉␉:32;␊
356␉␉␉};␊
357␉␉␉struct { /* STRP14 */␊
358␉␉␉␉uint32_t␉␉␉:8,␊
359␉␉␉␉␉ VE_EN2␉␉␉:1,␊
360␉␉␉␉␉␉␉␉:5,␊
361␉␉␉␉␉ VE_BOOT_FLASH␉␉:1,␊
362␉␉␉␉␉␉␉␉:1,␊
363␉␉␉␉␉ BW_SSD␉␉␉:1,␊
364␉␉␉␉␉ NVMHCI_EN␉␉:1,␊
365␉␉␉␉␉␉␉␉:14;␊
366␉␉␉};␊
367␉␉␉struct { /* STRP15 */␊
368␉␉␉␉uint32_t␉␉␉:3,␊
369␉␉␉␉␉ cs_ss6␉␉␉:2,␊
370␉␉␉␉␉␉␉␉:1,␊
371␉␉␉␉␉ IWL_EN␉␉␉:1,␊
372␉␉␉␉␉␉␉␉:1,␊
373␉␉␉␉␉ t209min␉␉:2,␊
374␉␉␉␉␉␉␉␉:22;␊
375␉␉␉};␊
376␉␉} ibex;␊
377␉␉struct { /* cougar point */␊
378␉␉␉struct { /* STRP0 */␊
379␉␉␉␉uint32_t␉␉␉:1,␊
380␉␉␉␉␉ cs_ss1␉␉␉:1,␊
381␉␉␉␉␉␉␉␉:5,␊
382␉␉␉␉␉ SMB_EN␉␉␉:1,␊
383␉␉␉␉␉ SML0_EN␉␉:1,␊
384␉␉␉␉␉ SML1_EN␉␉:1,␊
385␉␉␉␉␉ SML1FRQ␉␉:2,␊
386␉␉␉␉␉ SMB0FRQ␉␉:2,␊
387␉␉␉␉␉ SML0FRQ␉␉:2,␊
388␉␉␉␉␉␉␉␉:4,␊
389␉␉␉␉␉ LANPHYPC_GP12_SEL␉:1,␊
390␉␉␉␉␉ LINKSEC_DIS␉␉:1,␊
391␉␉␉␉␉␉␉␉:2,␊
392␉␉␉␉␉ DMI_REQID_DIS␉␉:1,␊
393␉␉␉␉␉␉␉␉:4,␊
394␉␉␉␉␉ BBBS␉␉␉:2,␊
395␉␉␉␉␉␉␉␉:1;␊
396␉␉␉};␊
397␉␉␉struct { /* STRP1 */␊
398␉␉␉␉uint32_t cs_ss3␉␉␉:4,␊
399␉␉␉␉␉␉␉␉:4,␊
400␉␉␉␉␉ cs_ss2␉␉␉:1,␊
401␉␉␉␉␉␉␉␉:28;␊
402␉␉␉};␊
403␉␉␉struct { /* STRP2 */␊
404␉␉␉␉uint32_t␉␉␉:8,␊
405␉␉␉␉␉ MESMASDEN␉␉:1,␊
406␉␉␉␉␉ MESMASDA␉␉:7,␊
407␉␉␉␉␉ MESMMCTPAEN␉␉:1,␊
408␉␉␉␉␉ MESMMCTPA␉␉:7,␊
409␉␉␉␉␉ MESMI2CEN␉␉:1,␊
410␉␉␉␉␉ MESMI2CA␉␉:7;␊
411␉␉␉};␊
412␉␉␉struct { /* STRP3 */␊
413␉␉␉␉uint32_t␉␉␉:32;␊
414␉␉␉};␊
415␉␉␉struct { /* STRP4 */␊
416␉␉␉␉uint32_t PHYCON␉␉␉:2,␊
417␉␉␉␉␉␉␉␉:6,␊
418␉␉␉␉␉ GBEMAC_SMBUS_ADDR_EN␉:1,␊
419␉␉␉␉␉ GBEMAC_SMBUS_ADDR␉:7,␊
420␉␉␉␉␉␉␉␉:1,␊
421␉␉␉␉␉ GBEPHY_SMBUS_ADDR␉:7,␊
422␉␉␉␉␉␉␉␉:8;␊
423␉␉␉};␊
424␉␉␉struct { /* STRP5 */␊
425␉␉␉␉uint32_t␉␉␉:32;␊
426␉␉␉};␊
427␉␉␉struct { /* STRP6 */␊
428␉␉␉␉uint32_t␉␉␉:32;␊
429␉␉␉};␊
430␉␉␉struct { /* STRP7 */␊
431␉␉␉␉uint32_t MESMA2UDID_VENDOR␉:16,␊
432␉␉␉␉␉ MESMA2UDID_DEVICE␉:16;␊
433␉␉␉};␊
434␉␉␉struct { /* STRP8 */␊
435␉␉␉␉uint32_t␉␉␉:32;␊
436␉␉␉};␊
437␉␉␉struct { /* STRP9 */␊
438␉␉␉␉uint32_t PCIEPCS1␉␉:2,␊
439␉␉␉␉␉ PCIEPCS2␉␉:2,␊
440␉␉␉␉␉ PCIELR1␉␉:1,␊
441␉␉␉␉␉ PCIELR2␉␉:1,␊
442␉␉␉␉␉ DMILR␉␉␉:1,␊
443␉␉␉␉␉ cs_ss4␉␉␉:1,␊
444␉␉␉␉␉ PHY_PCIEPORTSEL␉:3,␊
445␉␉␉␉␉ PHY_PCIE_EN␉␉:1,␊
446␉␉␉␉␉␉␉␉:2,␊
447␉␉␉␉␉ SUB_DECODE_EN␉␉:1,␊
448␉␉␉␉␉␉␉␉:7,␊
449␉␉␉␉␉ PCHHOT_SML1ALERT_SEL␉:1,␊
450␉␉␉␉␉␉␉␉:9;␊
451␉␉␉};␊
452␉␉␉struct { /* STRP10 */␊
453␉␉␉␉uint32_t␉␉␉:1,␊
454␉␉␉␉␉ ME_BOOT_FLASH␉␉:1,␊
455␉␉␉␉␉␉␉␉:6,␊
456␉␉␉␉␉ MDSMBE_EN␉␉:1,␊
457␉␉␉␉␉ MDSMBE_ADD␉␉:7,␊
458␉␉␉␉␉␉␉␉:2,␊
459␉␉␉␉␉ ICC_SEL␉␉:3,␊
460␉␉␉␉␉ MER_CL1␉␉:1,␊
461␉␉␉␉␉ ICC_PRO_SEL␉␉:1,␊
462␉␉␉␉␉ Deep_SX_EN␉␉:1,␊
463␉␉␉␉␉ ME_DBG_LAN␉␉:1,␊
464␉␉␉␉␉␉␉␉:7;␊
465␉␉␉};␊
466␉␉␉struct { /* STRP11 */␊
467␉␉␉␉uint32_t SML1GPAEN␉␉:1,␊
468␉␉␉␉␉ SML1GPA␉␉:7,␊
469␉␉␉␉␉␉␉␉:16,␊
470␉␉␉␉␉ SML1I2CAEN␉␉:1,␊
471␉␉␉␉␉ SML1I2CA␉␉:7;␊
472␉␉␉};␊
473␉␉␉struct { /* STRP12 */␊
474␉␉␉␉uint32_t␉␉␉:32;␊
475␉␉␉};␊
476␉␉␉struct { /* STRP13 */␊
477␉␉␉␉uint32_t␉␉␉:32;␊
478␉␉␉};␊
479␉␉␉struct { /* STRP14 */␊
480␉␉␉␉uint32_t␉␉␉:32;␊
481␉␉␉};␊
482␉␉␉struct { /* STRP15 */␊
483␉␉␉␉uint32_t cs_ss6␉␉␉:6,␊
484␉␉␉␉␉ IWL_EN␉␉␉:1,␊
485␉␉␉␉␉ cs_ss5␉␉␉:2,␊
486␉␉␉␉␉␉␉␉:4,␊
487␉␉␉␉␉ SMLINK1_THERM_SEL␉:1,␊
488␉␉␉␉␉ SLP_LAN_GP29_SEL␉:1,␊
489␉␉␉␉␉␉␉␉:16;␊
490␉␉␉};␊
491␉␉␉struct { /* STRP16 */␊
492␉␉␉␉uint32_t␉␉␉:32;␊
493␉␉␉};␊
494␉␉␉struct { /* STRP17 */␊
495␉␉␉␉uint32_t ICML␉␉␉:1,␊
496␉␉␉␉␉ cs_ss7␉␉␉:1,␊
497␉␉␉␉␉␉␉␉:30;␊
498␉␉␉};␊
499␉␉} cougar;␊
500␉};␊
501};␊
502␊
503struct ich_desc_upper_map {␊
504␉union {␊
505␉␉uint32_t FLUMAP1;␉␉/* Flash Upper Map 1 */␊
506␉␉struct {␊
507␉␉␉uint32_t VTBA␉:8,␉/* ME VSCC Table Base Address */␊
508␉␉␉␉ VTL␉:8,␉/* ME VSCC Table Length */␊
509␉␉␉␉␉:16;␊
510␉␉};␊
511␉};␊
512␉struct {␊
513␉␉union {␉␉/* JEDEC-ID Register */␊
514␉␉␉uint32_t JID;␊
515␉␉␉struct {␊
516␉␉␉␉uint32_t vid␉:8, /* Vendor ID */␊
517␉␉␉␉␉ cid0␉:8, /* Component ID 0 */␊
518␉␉␉␉␉ cid1␉:8, /* Component ID 1 */␊
519␉␉␉␉␉␉:8;␊
520␉␉␉};␊
521␉␉};␊
522␉␉union {␉␉/* Vendor Specific Component Capabilities */␊
523␉␉␉uint32_t VSCC;␊
524␉␉␉struct {␊
525␉␉␉␉uint32_t ubes␉:2, /* Upper Block/Sector Erase Size */␊
526␉␉␉␉␉ uwg␉:1, /* Upper Write Granularity */␊
527␉␉␉␉␉ uwsr␉:1, /* Upper Write Status Required */␊
528␉␉␉␉␉ uwews␉:1, /* Upper Write Enable on Write Status */␊
529␉␉␉␉␉␉:3,␊
530␉␉␉␉␉ ueo␉:8, /* Upper Erase Opcode */␊
531␉␉␉␉␉ lbes␉:2, /* Lower Block/Sector Erase Size */␊
532␉␉␉␉␉ lwg␉:1, /* Lower Write Granularity */␊
533␉␉␉␉␉ lwsr␉:1, /* Lower Write Status Required */␊
534␉␉␉␉␉ lwews␉:1, /* Lower Write Enable on Write Status */␊
535␉␉␉␉␉␉:3,␊
536␉␉␉␉␉ leo␉:16; /* Lower Erase Opcode */␊
537␉␉␉};␊
538␉␉};␊
539␉} vscc_table[128];␊
540};␊
541#endif /* ICH_DESCRIPTORS_FROM_DUMP */␊
542␊
543struct ich_descriptors {␊
544␉struct ich_desc_content content;␊
545␉struct ich_desc_component component;␊
546␉struct ich_desc_region region;␊
547␉struct ich_desc_master master;␊
548#ifdef ICH_DESCRIPTORS_FROM_DUMP␊
549␉struct ich_desc_north_strap north;␊
550␉struct ich_desc_south_strap south;␊
551␉struct ich_desc_upper_map upper;␊
552#endif /* ICH_DESCRIPTORS_FROM_DUMP */␊
553};␊
554␊
555void prettyprint_ich_descriptors(enum ich_chipset cs, const struct ich_descriptors *desc);␊
556␊
557void prettyprint_ich_descriptor_content(const struct ich_desc_content *content);␊
558void prettyprint_ich_descriptor_component(const struct ich_descriptors *desc);␊
559void prettyprint_ich_descriptor_region(const struct ich_descriptors *desc);␊
560void prettyprint_ich_descriptor_master(const struct ich_desc_master *master);␊
561␊
562#ifdef ICH_DESCRIPTORS_FROM_DUMP␊
563␊
564void prettyprint_ich_descriptor_upper_map(const struct ich_desc_upper_map *umap);␊
565void prettyprint_ich_descriptor_straps(enum ich_chipset cs, const struct ich_descriptors *desc);␊
566int read_ich_descriptors_from_dump(const uint32_t *dump, unsigned int len, struct ich_descriptors *desc);␊
567␊
568#else /* ICH_DESCRIPTORS_FROM_DUMP */␊
569␊
570int read_ich_descriptors_via_fdo(void *spibar, struct ich_descriptors *desc);␊
571int getFCBA_component_density(const struct ich_descriptors *desc, uint8_t idx);␊
572␊
573#endif /* ICH_DESCRIPTORS_FROM_DUMP */␊
574#endif /* __ICH_DESCRIPTORS_H__ */␊
575#endif /* defined(__i386__) || defined(__x86_64__) */␊
576

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