| 1 | /*␊ |
| 2 | * This file is part of the flashrom project.␊ |
| 3 | *␊ |
| 4 | * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>␊ |
| 5 | *␊ |
| 6 | * This program is free software; you can redistribute it and/or modify␊ |
| 7 | * it under the terms of the GNU General Public License as published by␊ |
| 8 | * the Free Software Foundation; either version 2 of the License, or␊ |
| 9 | * (at your option) any later version.␊ |
| 10 | *␊ |
| 11 | * This program is distributed in the hope that it will be useful,␊ |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of␊ |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the␊ |
| 14 | * GNU General Public License for more details.␊ |
| 15 | *␊ |
| 16 | * You should have received a copy of the GNU General Public License␊ |
| 17 | * along with this program; if not, write to the Free Software␊ |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA␊ |
| 19 | */␊ |
| 20 | ␊ |
| 21 | #include <stdlib.h>␊ |
| 22 | #include <string.h>␊ |
| 23 | #include "flash.h"␊ |
| 24 | #include "programmer.h"␊ |
| 25 | ␊ |
| 26 | #define PCI_VENDOR_ID_NVIDIA␉0x10de␊ |
| 27 | ␊ |
| 28 | /* Mask to restrict flash accesses to a 128kB memory window.␊ |
| 29 | * FIXME: Is this size a one-fits-all or card dependent?␊ |
| 30 | */␊ |
| 31 | #define GFXNVIDIA_MEMMAP_MASK␉␉((1 << 17) - 1)␊ |
| 32 | #define GFXNVIDIA_MEMMAP_SIZE␉␉(16 * 1024 * 1024)␊ |
| 33 | ␊ |
| 34 | uint8_t *nvidia_bar;␊ |
| 35 | ␊ |
| 36 | const struct pcidev_status gfx_nvidia[] = {␊ |
| 37 | ␉{0x10de, 0x0010, NT, "NVIDIA", "Mutara V08 [NV2]" },␊ |
| 38 | ␉{0x10de, 0x0018, NT, "NVIDIA", "RIVA 128" },␊ |
| 39 | ␉{0x10de, 0x0020, NT, "NVIDIA", "RIVA TNT" },␊ |
| 40 | ␉{0x10de, 0x0028, NT, "NVIDIA", "RIVA TNT2/TNT2 Pro" },␊ |
| 41 | ␉{0x10de, 0x0029, NT, "NVIDIA", "RIVA TNT2 Ultra" },␊ |
| 42 | ␉{0x10de, 0x002c, NT, "NVIDIA", "Vanta/Vanta LT" },␊ |
| 43 | ␉{0x10de, 0x002d, OK, "NVIDIA", "RIVA TNT2 Model 64/Model 64 Pro" },␊ |
| 44 | ␉{0x10de, 0x00a0, NT, "NVIDIA", "Aladdin TNT2" },␊ |
| 45 | ␉{0x10de, 0x0100, NT, "NVIDIA", "GeForce 256" },␊ |
| 46 | ␉{0x10de, 0x0101, NT, "NVIDIA", "GeForce DDR" },␊ |
| 47 | ␉{0x10de, 0x0103, NT, "NVIDIA", "Quadro" },␊ |
| 48 | ␉{0x10de, 0x0110, NT, "NVIDIA", "GeForce2 MX" },␊ |
| 49 | ␉{0x10de, 0x0111, NT, "NVIDIA", "GeForce2 MX" },␊ |
| 50 | ␉{0x10de, 0x0112, NT, "NVIDIA", "GeForce2 GO" },␊ |
| 51 | ␉{0x10de, 0x0113, NT, "NVIDIA", "Quadro2 MXR" },␊ |
| 52 | ␉{0x10de, 0x0150, NT, "NVIDIA", "GeForce2 GTS/Pro" },␊ |
| 53 | ␉{0x10de, 0x0151, NT, "NVIDIA", "GeForce2 GTS" },␊ |
| 54 | ␉{0x10de, 0x0152, NT, "NVIDIA", "GeForce2 Ultra" },␊ |
| 55 | ␉{0x10de, 0x0153, NT, "NVIDIA", "Quadro2 Pro" },␊ |
| 56 | ␉{0x10de, 0x0200, NT, "NVIDIA", "GeForce 3 nFX" },␊ |
| 57 | ␉{0x10de, 0x0201, NT, "NVIDIA", "GeForce 3 nFX" },␊ |
| 58 | ␉{0x10de, 0x0202, NT, "NVIDIA", "GeForce 3 nFX Ultra" },␊ |
| 59 | ␉{0x10de, 0x0203, NT, "NVIDIA", "Quadro 3 DDC" },␊ |
| 60 | ␊ |
| 61 | ␉{},␊ |
| 62 | };␊ |
| 63 | ␊ |
| 64 | static void gfxnvidia_chip_writeb(const struct flashctx *flash, uint8_t val,␊ |
| 65 | ␉␉␉␉ chipaddr addr);␊ |
| 66 | static uint8_t gfxnvidia_chip_readb(const struct flashctx *flash,␊ |
| 67 | ␉␉␉␉ const chipaddr addr);␊ |
| 68 | static const struct par_programmer par_programmer_gfxnvidia = {␊ |
| 69 | ␉␉.chip_readb␉␉= gfxnvidia_chip_readb,␊ |
| 70 | ␉␉.chip_readw␉␉= fallback_chip_readw,␊ |
| 71 | ␉␉.chip_readl␉␉= fallback_chip_readl,␊ |
| 72 | ␉␉.chip_readn␉␉= fallback_chip_readn,␊ |
| 73 | ␉␉.chip_writeb␉␉= gfxnvidia_chip_writeb,␊ |
| 74 | ␉␉.chip_writew␉␉= fallback_chip_writew,␊ |
| 75 | ␉␉.chip_writel␉␉= fallback_chip_writel,␊ |
| 76 | ␉␉.chip_writen␉␉= fallback_chip_writen,␊ |
| 77 | };␊ |
| 78 | ␊ |
| 79 | static int gfxnvidia_shutdown(void *data)␊ |
| 80 | {␊ |
| 81 | ␉physunmap(nvidia_bar, GFXNVIDIA_MEMMAP_SIZE);␊ |
| 82 | ␉/* Flash interface access is disabled (and screen enabled) automatically␊ |
| 83 | ␉ * by PCI restore.␊ |
| 84 | ␉ */␊ |
| 85 | ␉pci_cleanup(pacc);␊ |
| 86 | ␉release_io_perms();␊ |
| 87 | ␉return 0;␊ |
| 88 | }␊ |
| 89 | ␊ |
| 90 | int gfxnvidia_init(void)␊ |
| 91 | {␊ |
| 92 | ␉uint32_t reg32;␊ |
| 93 | ␊ |
| 94 | ␉get_io_perms();␊ |
| 95 | ␊ |
| 96 | ␉io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, gfx_nvidia);␊ |
| 97 | ␊ |
| 98 | ␉io_base_addr += 0x300000;␊ |
| 99 | ␉msg_pinfo("Detected NVIDIA I/O base address: 0x%x.\n", io_base_addr);␊ |
| 100 | ␊ |
| 101 | ␉nvidia_bar = physmap("NVIDIA", io_base_addr, GFXNVIDIA_MEMMAP_SIZE);␊ |
| 102 | ␊ |
| 103 | ␉/* Must be done before rpci calls. */␊ |
| 104 | ␉if (register_shutdown(gfxnvidia_shutdown, NULL))␊ |
| 105 | ␉␉return 1;␊ |
| 106 | ␊ |
| 107 | ␉/* Allow access to flash interface (will disable screen). */␊ |
| 108 | ␉reg32 = pci_read_long(pcidev_dev, 0x50);␊ |
| 109 | ␉reg32 &= ~(1 << 0);␊ |
| 110 | ␉rpci_write_long(pcidev_dev, 0x50, reg32);␊ |
| 111 | ␊ |
| 112 | ␉/* Write/erase doesn't work. */␊ |
| 113 | ␉programmer_may_write = 0;␊ |
| 114 | ␉register_par_programmer(&par_programmer_gfxnvidia, BUS_PARALLEL);␊ |
| 115 | ␊ |
| 116 | ␉return 0;␊ |
| 117 | }␊ |
| 118 | ␊ |
| 119 | static void gfxnvidia_chip_writeb(const struct flashctx *flash, uint8_t val,␊ |
| 120 | ␉␉␉␉ chipaddr addr)␊ |
| 121 | {␊ |
| 122 | ␉pci_mmio_writeb(val, nvidia_bar + (addr & GFXNVIDIA_MEMMAP_MASK));␊ |
| 123 | }␊ |
| 124 | ␊ |
| 125 | static uint8_t gfxnvidia_chip_readb(const struct flashctx *flash,␊ |
| 126 | ␉␉␉␉ const chipaddr addr)␊ |
| 127 | {␊ |
| 128 | ␉return pci_mmio_readb(nvidia_bar + (addr & GFXNVIDIA_MEMMAP_MASK));␊ |
| 129 | }␊ |
| 130 | |
