| 1 | /*␊ |
| 2 | * This file is part of the flashrom project.␊ |
| 3 | *␊ |
| 4 | * Copyright (C) 2005-2007 coresystems GmbH <stepan@coresystems.de>␊ |
| 5 | * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>␊ |
| 6 | * Copyright (C) 2007-2009 Luc Verhaegen <libv@skynet.be>␊ |
| 7 | * Copyright (C) 2007 Carl-Daniel Hailfinger␊ |
| 8 | *␊ |
| 9 | * This program is free software; you can redistribute it and/or modify␊ |
| 10 | * it under the terms of the GNU General Public License as published by␊ |
| 11 | * the Free Software Foundation; version 2 of the License.␊ |
| 12 | *␊ |
| 13 | * This program is distributed in the hope that it will be useful,␊ |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of␊ |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the␊ |
| 16 | * GNU General Public License for more details.␊ |
| 17 | *␊ |
| 18 | * You should have received a copy of the GNU General Public License␊ |
| 19 | * along with this program; if not, write to the Free Software␊ |
| 20 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA␊ |
| 21 | */␊ |
| 22 | ␊ |
| 23 | /*␊ |
| 24 | * Contains the board specific flash enables.␊ |
| 25 | */␊ |
| 26 | ␊ |
| 27 | #include <string.h>␊ |
| 28 | #include "flash.h"␊ |
| 29 | #include "programmer.h"␊ |
| 30 | ␊ |
| 31 | #if defined(__i386__) || defined(__x86_64__)␊ |
| 32 | /*␊ |
| 33 | * Helper functions for many Winbond Super I/Os of the W836xx range.␊ |
| 34 | */␊ |
| 35 | /* Enter extended functions */␊ |
| 36 | void w836xx_ext_enter(uint16_t port)␊ |
| 37 | {␊ |
| 38 | ␉OUTB(0x87, port);␊ |
| 39 | ␉OUTB(0x87, port);␊ |
| 40 | }␊ |
| 41 | ␊ |
| 42 | /* Leave extended functions */␊ |
| 43 | void w836xx_ext_leave(uint16_t port)␊ |
| 44 | {␊ |
| 45 | ␉OUTB(0xAA, port);␊ |
| 46 | }␊ |
| 47 | ␊ |
| 48 | /* Generic Super I/O helper functions */␊ |
| 49 | uint8_t sio_read(uint16_t port, uint8_t reg)␊ |
| 50 | {␊ |
| 51 | ␉OUTB(reg, port);␊ |
| 52 | ␉return INB(port + 1);␊ |
| 53 | }␊ |
| 54 | ␊ |
| 55 | void sio_write(uint16_t port, uint8_t reg, uint8_t data)␊ |
| 56 | {␊ |
| 57 | ␉OUTB(reg, port);␊ |
| 58 | ␉OUTB(data, port + 1);␊ |
| 59 | }␊ |
| 60 | ␊ |
| 61 | void sio_mask(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask)␊ |
| 62 | {␊ |
| 63 | ␉uint8_t tmp;␊ |
| 64 | ␊ |
| 65 | ␉OUTB(reg, port);␊ |
| 66 | ␉tmp = INB(port + 1) & ~mask;␊ |
| 67 | ␉OUTB(tmp | (data & mask), port + 1);␊ |
| 68 | }␊ |
| 69 | ␊ |
| 70 | /* Not used yet. */␊ |
| 71 | #if 0␊ |
| 72 | static int enable_flash_decode_superio(void)␊ |
| 73 | {␊ |
| 74 | ␉int ret;␊ |
| 75 | ␉uint8_t tmp;␊ |
| 76 | ␊ |
| 77 | ␉switch (superio.vendor) {␊ |
| 78 | ␉case SUPERIO_VENDOR_NONE:␊ |
| 79 | ␉␉ret = -1;␊ |
| 80 | ␉␉break;␊ |
| 81 | ␉case SUPERIO_VENDOR_ITE:␊ |
| 82 | ␉␉enter_conf_mode_ite(superio.port);␊ |
| 83 | ␉␉/* Enable flash mapping. Works for most old ITE style Super I/O. */␊ |
| 84 | ␉␉tmp = sio_read(superio.port, 0x24);␊ |
| 85 | ␉␉tmp |= 0xfc;␊ |
| 86 | ␉␉sio_write(superio.port, 0x24, tmp);␊ |
| 87 | ␉␉exit_conf_mode_ite(superio.port);␊ |
| 88 | ␉␉ret = 0;␊ |
| 89 | ␉␉break;␊ |
| 90 | ␉default:␊ |
| 91 | ␉␉msg_pdbg("Unhandled Super I/O type!\n");␊ |
| 92 | ␉␉ret = -1;␊ |
| 93 | ␉␉break;␊ |
| 94 | ␉}␊ |
| 95 | ␉return ret;␊ |
| 96 | }␊ |
| 97 | #endif␊ |
| 98 | ␊ |
| 99 | /*␊ |
| 100 | * SMSC FDC37B787: Raise GPIO50␊ |
| 101 | */␊ |
| 102 | static int fdc37b787_gpio50_raise(uint16_t port)␊ |
| 103 | {␊ |
| 104 | ␉uint8_t id, val;␊ |
| 105 | ␊ |
| 106 | ␉OUTB(0x55, port);␉/* enter conf mode */␊ |
| 107 | ␉id = sio_read(port, 0x20);␊ |
| 108 | ␉if (id != 0x44) {␊ |
| 109 | ␉␉msg_perr("\nERROR: FDC37B787: Wrong ID 0x%02X.\n", id);␊ |
| 110 | ␉␉OUTB(0xAA, port); /* leave conf mode */␊ |
| 111 | ␉␉return -1;␊ |
| 112 | ␉}␊ |
| 113 | ␊ |
| 114 | ␉sio_write(port, 0x07, 0x08);␉/* Select Aux I/O subdevice */␊ |
| 115 | ␊ |
| 116 | ␉val = sio_read(port, 0xC8);␉/* GP50 */␊ |
| 117 | ␉if ((val & 0x1B) != 0x10)␉/* output, no invert, GPIO */␊ |
| 118 | ␉{␊ |
| 119 | ␉␉msg_perr("\nERROR: GPIO50 mode 0x%02X unexpected.\n", val);␊ |
| 120 | ␉␉OUTB(0xAA, port);␊ |
| 121 | ␉␉return -1;␊ |
| 122 | ␉}␊ |
| 123 | ␊ |
| 124 | ␉sio_mask(port, 0xF9, 0x01, 0x01);␊ |
| 125 | ␊ |
| 126 | ␉OUTB(0xAA, port);␉␉/* Leave conf mode */␊ |
| 127 | ␉return 0;␊ |
| 128 | }␊ |
| 129 | ␊ |
| 130 | /*␊ |
| 131 | * Suited for:␊ |
| 132 | * - Nokia IP530: Intel 440BX + PIIX4 + FDC37B787␊ |
| 133 | */␊ |
| 134 | static int fdc37b787_gpio50_raise_3f0(void)␊ |
| 135 | {␊ |
| 136 | ␉return fdc37b787_gpio50_raise(0x3f0);␊ |
| 137 | }␊ |
| 138 | ␊ |
| 139 | struct winbond_mux {␊ |
| 140 | ␉uint8_t reg;␉␉/* 0 if the corresponding pin is not muxed */␊ |
| 141 | ␉uint8_t data;␉␉/* reg/data/mask may be directly ... */␊ |
| 142 | ␉uint8_t mask;␉␉/* ... passed to sio_mask */␊ |
| 143 | };␊ |
| 144 | ␊ |
| 145 | struct winbond_port {␊ |
| 146 | ␉const struct winbond_mux *mux; /* NULL or pointer to mux info for the 8 bits */␊ |
| 147 | ␉uint8_t ldn;␉␉/* LDN this GPIO register is located in */␊ |
| 148 | ␉uint8_t enable_bit;␉/* bit in 0x30 of that LDN to enable ␊ |
| 149 | ␉ the GPIO port */␊ |
| 150 | ␉uint8_t base;␉␉/* base register in that LDN for the port */␊ |
| 151 | };␊ |
| 152 | ␊ |
| 153 | struct winbond_chip {␊ |
| 154 | ␉uint8_t device_id;␉/* reg 0x20 of the expected w83626x */␊ |
| 155 | ␉uint8_t gpio_port_count;␊ |
| 156 | ␉const struct winbond_port *port;␊ |
| 157 | };␊ |
| 158 | ␊ |
| 159 | ␊ |
| 160 | #define UNIMPLEMENTED_PORT {NULL, 0, 0, 0}␊ |
| 161 | ␊ |
| 162 | enum winbond_id {␊ |
| 163 | ␉WINBOND_W83627HF_ID = 0x52,␊ |
| 164 | ␉WINBOND_W83627EHF_ID = 0x88,␊ |
| 165 | ␉WINBOND_W83627THF_ID = 0x82,␊ |
| 166 | };␊ |
| 167 | ␊ |
| 168 | static const struct winbond_mux w83627hf_port2_mux[8] = {␊ |
| 169 | ␉{0x2A, 0x01, 0x01},␉/* or MIDI */␊ |
| 170 | ␉{0x2B, 0x80, 0x80},␉/* or SPI */␊ |
| 171 | ␉{0x2B, 0x40, 0x40},␉/* or SPI */␊ |
| 172 | ␉{0x2B, 0x20, 0x20},␉/* or power LED */␊ |
| 173 | ␉{0x2B, 0x10, 0x10},␉/* or watchdog */␊ |
| 174 | ␉{0x2B, 0x08, 0x08},␉/* or infra red */␊ |
| 175 | ␉{0x2B, 0x04, 0x04},␉/* or infra red */␊ |
| 176 | ␉{0x2B, 0x03, 0x03}␉/* or IRQ1 input */␊ |
| 177 | };␊ |
| 178 | ␊ |
| 179 | static const struct winbond_port w83627hf[3] = {␊ |
| 180 | ␉UNIMPLEMENTED_PORT,␊ |
| 181 | ␉{w83627hf_port2_mux, 0x08, 0, 0xF0},␊ |
| 182 | ␉UNIMPLEMENTED_PORT,␊ |
| 183 | };␊ |
| 184 | ␊ |
| 185 | static const struct winbond_mux w83627ehf_port2_mux[8] = {␊ |
| 186 | ␉{0x29, 0x06, 0x02},␉/* or MIDI */␊ |
| 187 | ␉{0x29, 0x06, 0x02},␊ |
| 188 | ␉{0x24, 0x02, 0x00},␉/* or SPI ROM interface */␊ |
| 189 | ␉{0x24, 0x02, 0x00},␊ |
| 190 | ␉{0x2A, 0x01, 0x01},␉/* or keyboard/mouse interface */␊ |
| 191 | ␉{0x2A, 0x01, 0x01},␊ |
| 192 | ␉{0x2A, 0x01, 0x01},␊ |
| 193 | ␉{0x2A, 0x01, 0x01},␊ |
| 194 | };␊ |
| 195 | ␊ |
| 196 | static const struct winbond_port w83627ehf[6] = {␊ |
| 197 | ␉UNIMPLEMENTED_PORT,␊ |
| 198 | ␉{w83627ehf_port2_mux, 0x09, 0, 0xE3},␊ |
| 199 | ␉UNIMPLEMENTED_PORT,␊ |
| 200 | ␉UNIMPLEMENTED_PORT,␊ |
| 201 | ␉UNIMPLEMENTED_PORT,␊ |
| 202 | ␉UNIMPLEMENTED_PORT,␊ |
| 203 | };␊ |
| 204 | ␊ |
| 205 | static const struct winbond_mux w83627thf_port4_mux[8] = {␊ |
| 206 | ␉{0x2D, 0x01, 0x01},␉/* or watchdog or VID level strap */␊ |
| 207 | ␉{0x2D, 0x02, 0x02},␉/* or resume reset */␊ |
| 208 | ␉{0x2D, 0x04, 0x04},␉/* or S3 input */␊ |
| 209 | ␉{0x2D, 0x08, 0x08},␉/* or PSON# */␊ |
| 210 | ␉{0x2D, 0x10, 0x10},␉/* or PWROK */␊ |
| 211 | ␉{0x2D, 0x20, 0x20},␉/* or suspend LED */␊ |
| 212 | ␉{0x2D, 0x40, 0x40},␉/* or panel switch input */␊ |
| 213 | ␉{0x2D, 0x80, 0x80},␉/* or panel switch output */␊ |
| 214 | };␊ |
| 215 | ␊ |
| 216 | static const struct winbond_port w83627thf[5] = {␊ |
| 217 | ␉UNIMPLEMENTED_PORT,␉/* GPIO1 */␊ |
| 218 | ␉UNIMPLEMENTED_PORT,␉/* GPIO2 */␊ |
| 219 | ␉UNIMPLEMENTED_PORT,␉/* GPIO3 */␊ |
| 220 | ␉{w83627thf_port4_mux, 0x09, 1, 0xF4},␊ |
| 221 | ␉UNIMPLEMENTED_PORT,␉/* GPIO5 */␊ |
| 222 | };␊ |
| 223 | ␊ |
| 224 | static const struct winbond_chip winbond_chips[] = {␊ |
| 225 | ␉{WINBOND_W83627HF_ID, ARRAY_SIZE(w83627hf), w83627hf },␊ |
| 226 | ␉{WINBOND_W83627EHF_ID, ARRAY_SIZE(w83627ehf), w83627ehf},␊ |
| 227 | ␉{WINBOND_W83627THF_ID, ARRAY_SIZE(w83627thf), w83627thf},␊ |
| 228 | };␊ |
| 229 | ␊ |
| 230 | /*␊ |
| 231 | * Detects which Winbond Super I/O is responding at the given base address,␊ |
| 232 | * but takes no effort to make sure the chip is really a Winbond Super I/O.␊ |
| 233 | */␊ |
| 234 | static const struct winbond_chip *winbond_superio_detect(uint16_t base)␊ |
| 235 | {␊ |
| 236 | ␉uint8_t chipid;␊ |
| 237 | ␉const struct winbond_chip *chip = NULL;␊ |
| 238 | ␉int i;␊ |
| 239 | ␊ |
| 240 | ␉w836xx_ext_enter(base);␊ |
| 241 | ␉chipid = sio_read(base, 0x20);␊ |
| 242 | ␊ |
| 243 | ␉for (i = 0; i < ARRAY_SIZE(winbond_chips); i++) {␊ |
| 244 | ␉␉if (winbond_chips[i].device_id == chipid) {␊ |
| 245 | ␉␉␉chip = &winbond_chips[i];␊ |
| 246 | ␉␉␉break;␊ |
| 247 | ␉␉}␊ |
| 248 | ␉}␊ |
| 249 | ␊ |
| 250 | ␉w836xx_ext_leave(base);␊ |
| 251 | ␉return chip;␊ |
| 252 | }␊ |
| 253 | ␊ |
| 254 | /*␊ |
| 255 | * The chipid parameter goes away as soon as we have Super I/O matching in the␊ |
| 256 | * board enable table. The call to winbond_superio_detect() goes away as␊ |
| 257 | * soon as we have generic Super I/O detection code.␊ |
| 258 | */␊ |
| 259 | static int winbond_gpio_set(uint16_t base, enum winbond_id chipid,␊ |
| 260 | int pin, int raise)␊ |
| 261 | {␊ |
| 262 | ␉const struct winbond_chip *chip = NULL;␊ |
| 263 | ␉const struct winbond_port *gpio;␊ |
| 264 | ␉int port = pin / 10;␊ |
| 265 | ␉int bit = pin % 10;␊ |
| 266 | ␊ |
| 267 | ␉chip = winbond_superio_detect(base);␊ |
| 268 | ␉if (!chip) {␊ |
| 269 | ␉␉msg_perr("\nERROR: No supported Winbond Super I/O found\n");␊ |
| 270 | ␉␉return -1;␊ |
| 271 | ␉}␊ |
| 272 | ␉if (chip->device_id != chipid) {␊ |
| 273 | ␉␉msg_perr("\nERROR: Found Winbond chip with ID 0x%x, "␊ |
| 274 | ␉␉ "expected %x\n", chip->device_id, chipid);␊ |
| 275 | ␉␉return -1;␊ |
| 276 | ␉}␊ |
| 277 | ␉if (bit >= 8 || port == 0 || port > chip->gpio_port_count) {␊ |
| 278 | ␉␉msg_perr("\nERROR: winbond_gpio_set: Invalid GPIO number %d\n",␊ |
| 279 | ␉␉ pin);␊ |
| 280 | ␉␉return -1;␊ |
| 281 | ␉}␊ |
| 282 | ␊ |
| 283 | ␉gpio = &chip->port[port - 1];␊ |
| 284 | ␊ |
| 285 | ␉if (gpio->ldn == 0) {␊ |
| 286 | ␉␉msg_perr("\nERROR: GPIO%d is not supported yet on this"␊ |
| 287 | ␉␉ " winbond chip\n", port);␊ |
| 288 | ␉␉return -1;␊ |
| 289 | ␉}␊ |
| 290 | ␊ |
| 291 | ␉w836xx_ext_enter(base);␊ |
| 292 | ␊ |
| 293 | ␉/* Select logical device. */␊ |
| 294 | ␉sio_write(base, 0x07, gpio->ldn);␊ |
| 295 | ␊ |
| 296 | ␉/* Activate logical device. */␊ |
| 297 | ␉sio_mask(base, 0x30, 1 << gpio->enable_bit, 1 << gpio->enable_bit);␊ |
| 298 | ␊ |
| 299 | ␉/* Select GPIO function of that pin. */␊ |
| 300 | ␉if (gpio->mux && gpio->mux[bit].reg)␊ |
| 301 | ␉␉sio_mask(base, gpio->mux[bit].reg,␊ |
| 302 | ␉␉ gpio->mux[bit].data, gpio->mux[bit].mask);␊ |
| 303 | ␊ |
| 304 | ␉sio_mask(base, gpio->base + 0, 0, 1 << bit);␉/* Make pin output */␊ |
| 305 | ␉sio_mask(base, gpio->base + 2, 0, 1 << bit);␉/* Clear inversion */␊ |
| 306 | ␉sio_mask(base, gpio->base + 1, raise << bit, 1 << bit);␊ |
| 307 | ␊ |
| 308 | ␉w836xx_ext_leave(base);␊ |
| 309 | ␊ |
| 310 | ␉return 0;␊ |
| 311 | }␊ |
| 312 | ␊ |
| 313 | /*␊ |
| 314 | * Winbond W83627HF: Raise GPIO24.␊ |
| 315 | *␊ |
| 316 | * Suited for:␊ |
| 317 | * - Agami Aruma␊ |
| 318 | * - IWILL DK8-HTX␊ |
| 319 | */␊ |
| 320 | static int w83627hf_gpio24_raise_2e(void)␊ |
| 321 | {␊ |
| 322 | ␉return winbond_gpio_set(0x2e, WINBOND_W83627HF_ID, 24, 1);␊ |
| 323 | }␊ |
| 324 | ␊ |
| 325 | /*␊ |
| 326 | * Winbond W83627HF: Raise GPIO25.␊ |
| 327 | *␊ |
| 328 | * Suited for:␊ |
| 329 | * - MSI MS-6577␊ |
| 330 | */␊ |
| 331 | static int w83627hf_gpio25_raise_2e(void)␊ |
| 332 | {␊ |
| 333 | ␉return winbond_gpio_set(0x2e, WINBOND_W83627HF_ID, 25, 1);␊ |
| 334 | }␊ |
| 335 | ␊ |
| 336 | /*␊ |
| 337 | * Winbond W83627EHF: Raise GPIO22.␊ |
| 338 | *␊ |
| 339 | * Suited for:␊ |
| 340 | * - ASUS A8N-VM CSM: AMD Socket 939 + GeForce 6150 (C51) + MCP51␊ |
| 341 | */␊ |
| 342 | static int w83627ehf_gpio22_raise_2e(void)␊ |
| 343 | {␊ |
| 344 | ␉return winbond_gpio_set(0x2e, WINBOND_W83627EHF_ID, 22, 1);␊ |
| 345 | }␊ |
| 346 | ␊ |
| 347 | /*␊ |
| 348 | * Winbond W83627THF: Raise GPIO 44.␊ |
| 349 | *␊ |
| 350 | * Suited for:␊ |
| 351 | * - MSI K8T Neo2-F␊ |
| 352 | */␊ |
| 353 | static int w83627thf_gpio44_raise_2e(void)␊ |
| 354 | {␊ |
| 355 | ␉return winbond_gpio_set(0x2e, WINBOND_W83627THF_ID, 44, 1);␊ |
| 356 | }␊ |
| 357 | ␊ |
| 358 | /*␊ |
| 359 | * Winbond W83627THF: Raise GPIO 44.␊ |
| 360 | *␊ |
| 361 | * Suited for:␊ |
| 362 | * - MSI K8N Neo3␊ |
| 363 | */␊ |
| 364 | static int w83627thf_gpio44_raise_4e(void)␊ |
| 365 | {␊ |
| 366 | ␉return winbond_gpio_set(0x4e, WINBOND_W83627THF_ID, 44, 1);␊ |
| 367 | }␊ |
| 368 | ␊ |
| 369 | /*␊ |
| 370 | * Enable MEMW# and set ROM size to max.␊ |
| 371 | * Supported chips: W83L517D, W83697HF/F/HG, W83697SF/UF/UG␊ |
| 372 | */␊ |
| 373 | static void w836xx_memw_enable(uint16_t port)␊ |
| 374 | {␊ |
| 375 | ␉w836xx_ext_enter(port);␊ |
| 376 | ␉if (!(sio_read(port, 0x24) & 0x02)) {␉/* Flash ROM enabled? */␊ |
| 377 | ␉␉/* Enable MEMW# and set ROM size select to max. (4M). */␊ |
| 378 | ␉␉sio_mask(port, 0x24, 0x28, 0x28);␊ |
| 379 | ␉}␊ |
| 380 | ␉w836xx_ext_leave(port);␊ |
| 381 | }␊ |
| 382 | ␊ |
| 383 | /*␊ |
| 384 | * Suited for:␊ |
| 385 | * - EPoX EP-8K5A2: VIA KT333 + VT8235␊ |
| 386 | * - Albatron PM266A Pro: VIA P4M266A + VT8235␊ |
| 387 | * - Shuttle AK31 (all versions): VIA KT266 + VT8233␊ |
| 388 | * - ASUS A7V8X-MX SE and A7V400-MX: AMD K7 + VIA KM400A + VT8235␊ |
| 389 | * - Tyan S2498 (Tomcat K7M): AMD Geode NX + VIA KM400 + VT8237␊ |
| 390 | * - MSI KM4M-V and KM4AM-V: VIA KM400/KM400A + VT8237␊ |
| 391 | * - MSI MS-6561 (745 Ultra): SiS 745 + W83697HF␊ |
| 392 | * - MSI MS-6787 (P4MAM-V/P4MAM-L): VIA P4M266 + VT8235␊ |
| 393 | * - ASRock K7S41: SiS 741 + SiS 963 + W83697HF␊ |
| 394 | * - ASRock K7S41GX: SiS 741GX + SiS 963L + W83697HF␊ |
| 395 | */␊ |
| 396 | static int w836xx_memw_enable_2e(void)␊ |
| 397 | {␊ |
| 398 | ␉w836xx_memw_enable(0x2E);␊ |
| 399 | ␊ |
| 400 | ␉return 0;␊ |
| 401 | }␊ |
| 402 | ␊ |
| 403 | /*␊ |
| 404 | * Suited for:␊ |
| 405 | * - Termtek TK-3370 (rev. 2.5b)␊ |
| 406 | */␊ |
| 407 | static int w836xx_memw_enable_4e(void)␊ |
| 408 | {␊ |
| 409 | ␉w836xx_memw_enable(0x4E);␊ |
| 410 | ␊ |
| 411 | ␉return 0;␊ |
| 412 | }␊ |
| 413 | ␊ |
| 414 | /*␊ |
| 415 | * Suited for all boards with ITE IT8705F.␊ |
| 416 | * The SIS950 Super I/O probably requires a similar flash write enable.␊ |
| 417 | */␊ |
| 418 | int it8705f_write_enable(uint8_t port)␊ |
| 419 | {␊ |
| 420 | ␉uint8_t tmp;␊ |
| 421 | ␉int ret = 0;␊ |
| 422 | ␊ |
| 423 | ␉enter_conf_mode_ite(port);␊ |
| 424 | ␉tmp = sio_read(port, 0x24);␊ |
| 425 | ␉/* Check if at least one flash segment is enabled. */␊ |
| 426 | ␉if (tmp & 0xf0) {␊ |
| 427 | ␉␉/* The IT8705F will respond to LPC cycles and translate them. */␊ |
| 428 | ␉␉internal_buses_supported = BUS_PARALLEL;␊ |
| 429 | ␉␉/* Flash ROM I/F Writes Enable */␊ |
| 430 | ␉␉tmp |= 0x04;␊ |
| 431 | ␉␉msg_pdbg("Enabling IT8705F flash ROM interface write.\n");␊ |
| 432 | ␉␉if (tmp & 0x02) {␊ |
| 433 | ␉␉␉/* The data sheet contradicts itself about max size. */␊ |
| 434 | ␉␉␉max_rom_decode.parallel = 1024 * 1024;␊ |
| 435 | ␉␉␉msg_pinfo("IT8705F with very unusual settings. Please "␊ |
| 436 | ␉␉␉␉ "send the output of \"flashrom -V\" to \n"␊ |
| 437 | ␉␉␉␉ "flashrom@flashrom.org with "␊ |
| 438 | ␉␉␉␉ "IT8705: your board name: flashrom -V\n"␊ |
| 439 | ␉␉␉␉ "as the subject to help us finish "␊ |
| 440 | ␉␉␉␉ "support for your Super I/O. Thanks.\n");␊ |
| 441 | ␉␉␉ret = 1;␊ |
| 442 | ␉␉} else if (tmp & 0x08) {␊ |
| 443 | ␉␉␉max_rom_decode.parallel = 512 * 1024;␊ |
| 444 | ␉␉} else {␊ |
| 445 | ␉␉␉max_rom_decode.parallel = 256 * 1024;␊ |
| 446 | ␉␉}␊ |
| 447 | ␉␉/* Safety checks. The data sheet is unclear here: Segments 1+3␊ |
| 448 | ␉␉ * overlap, no segment seems to cover top - 1MB to top - 512kB.␊ |
| 449 | ␉␉ * We assume that certain combinations make no sense.␊ |
| 450 | ␉␉ */␊ |
| 451 | ␉␉if (((tmp & 0x02) && !(tmp & 0x08)) || /* 1 MB en, 512 kB dis */␊ |
| 452 | ␉␉ (!(tmp & 0x10)) || /* 128 kB dis */␊ |
| 453 | ␉␉ (!(tmp & 0x40))) { /* 256/512 kB dis */␊ |
| 454 | ␉␉␉msg_perr("Inconsistent IT8705F decode size!\n");␊ |
| 455 | ␉␉␉ret = 1;␊ |
| 456 | ␉␉}␊ |
| 457 | ␉␉if (sio_read(port, 0x25) != 0) {␊ |
| 458 | ␉␉␉msg_perr("IT8705F flash data pins disabled!\n");␊ |
| 459 | ␉␉␉ret = 1;␊ |
| 460 | ␉␉}␊ |
| 461 | ␉␉if (sio_read(port, 0x26) != 0) {␊ |
| 462 | ␉␉␉msg_perr("IT8705F flash address pins 0-7 disabled!\n");␊ |
| 463 | ␉␉␉ret = 1;␊ |
| 464 | ␉␉}␊ |
| 465 | ␉␉if (sio_read(port, 0x27) != 0) {␊ |
| 466 | ␉␉␉msg_perr("IT8705F flash address pins 8-15 disabled!\n");␊ |
| 467 | ␉␉␉ret = 1;␊ |
| 468 | ␉␉}␊ |
| 469 | ␉␉if ((sio_read(port, 0x29) & 0x10) != 0) {␊ |
| 470 | ␉␉␉msg_perr("IT8705F flash write enable pin disabled!\n");␊ |
| 471 | ␉␉␉ret = 1;␊ |
| 472 | ␉␉}␊ |
| 473 | ␉␉if ((sio_read(port, 0x29) & 0x08) != 0) {␊ |
| 474 | ␉␉␉msg_perr("IT8705F flash chip select pin disabled!\n");␊ |
| 475 | ␉␉␉ret = 1;␊ |
| 476 | ␉␉}␊ |
| 477 | ␉␉if ((sio_read(port, 0x29) & 0x04) != 0) {␊ |
| 478 | ␉␉␉msg_perr("IT8705F flash read strobe pin disabled!\n");␊ |
| 479 | ␉␉␉ret = 1;␊ |
| 480 | ␉␉}␊ |
| 481 | ␉␉if ((sio_read(port, 0x29) & 0x03) != 0) {␊ |
| 482 | ␉␉␉msg_perr("IT8705F flash address pins 16-17 disabled!\n");␊ |
| 483 | ␉␉␉/* Not really an error if you use flash chips smaller␊ |
| 484 | ␉␉␉ * than 256 kByte, but such a configuration is unlikely.␊ |
| 485 | ␉␉␉ */␊ |
| 486 | ␉␉␉ret = 1;␊ |
| 487 | ␉␉}␊ |
| 488 | ␉␉msg_pdbg("Maximum IT8705F parallel flash decode size is %u.\n",␊ |
| 489 | ␉␉␉max_rom_decode.parallel);␊ |
| 490 | ␉␉if (ret) {␊ |
| 491 | ␉␉␉msg_pinfo("Not enabling IT8705F flash write.\n");␊ |
| 492 | ␉␉} else {␊ |
| 493 | ␉␉␉sio_write(port, 0x24, tmp);␊ |
| 494 | ␉␉}␊ |
| 495 | ␉} else {␊ |
| 496 | ␉␉msg_pdbg("No IT8705F flash segment enabled.\n");␊ |
| 497 | ␉␉ret = 0;␊ |
| 498 | ␉}␊ |
| 499 | ␉exit_conf_mode_ite(port);␊ |
| 500 | ␊ |
| 501 | ␉return ret;␊ |
| 502 | }␊ |
| 503 | ␊ |
| 504 | /*␊ |
| 505 | * The ITE IT8707F is a custom chip made by ITE exclusively for ASUS.␊ |
| 506 | * It uses the Winbond command sequence to enter extended configuration␊ |
| 507 | * mode and the ITE sequence to exit.␊ |
| 508 | *␊ |
| 509 | * Registers seems similar to the ones on ITE IT8710F.␊ |
| 510 | */␊ |
| 511 | static int it8707f_write_enable(uint8_t port)␊ |
| 512 | {␊ |
| 513 | ␉uint8_t tmp;␊ |
| 514 | ␊ |
| 515 | ␉w836xx_ext_enter(port);␊ |
| 516 | ␊ |
| 517 | ␉/* Set bit 3 (GLB_REG_WE) of reg 0x23: Makes reg 0x24-0x2A rw */␊ |
| 518 | ␉tmp = sio_read(port, 0x23);␊ |
| 519 | ␉tmp |= (1 << 3);␊ |
| 520 | ␉sio_write(port, 0x23, tmp);␊ |
| 521 | ␊ |
| 522 | ␉/* Set bit 2 (FLASH_WE) and bit 3 (FLASH_IF_EN) of reg 0x24 */␊ |
| 523 | ␉tmp = sio_read(port, 0x24);␊ |
| 524 | ␉tmp |= (1 << 2) | (1 << 3);␊ |
| 525 | ␉sio_write(port, 0x24, tmp);␊ |
| 526 | ␊ |
| 527 | ␉/* Clear bit 3 (GLB_REG_WE) of reg 0x23: Makes reg 0x24-0x2A ro */␊ |
| 528 | ␉tmp = sio_read(port, 0x23);␊ |
| 529 | ␉tmp &= ~(1 << 3);␊ |
| 530 | ␉sio_write(port, 0x23, tmp);␊ |
| 531 | ␊ |
| 532 | ␉exit_conf_mode_ite(port);␊ |
| 533 | ␊ |
| 534 | ␉return 0;␊ |
| 535 | }␊ |
| 536 | ␊ |
| 537 | /*␊ |
| 538 | * Suited for:␊ |
| 539 | * - ASUS P4SC-E: SiS 651 + 962 + ITE IT8707F␊ |
| 540 | */␊ |
| 541 | static int it8707f_write_enable_2e(void)␊ |
| 542 | {␊ |
| 543 | ␉return it8707f_write_enable(0x2e);␊ |
| 544 | }␊ |
| 545 | ␊ |
| 546 | #define PC87360_ID 0xE1␊ |
| 547 | #define PC87364_ID 0xE4␊ |
| 548 | ␊ |
| 549 | static int pc8736x_gpio_set(uint8_t chipid, uint8_t gpio, int raise)␊ |
| 550 | {␊ |
| 551 | ␉static const int bankbase[] = {0, 4, 8, 10, 12};␊ |
| 552 | ␉int gpio_bank = gpio / 8;␊ |
| 553 | ␉int gpio_pin = gpio % 8;␊ |
| 554 | ␉uint16_t baseport;␊ |
| 555 | ␉uint8_t id, val;␊ |
| 556 | ␊ |
| 557 | ␉if (gpio_bank > 4) {␊ |
| 558 | ␉␉msg_perr("PC8736x: Invalid GPIO %d\n", gpio);␊ |
| 559 | ␉␉return -1;␊ |
| 560 | ␉}␊ |
| 561 | ␊ |
| 562 | ␉id = sio_read(0x2E, 0x20);␊ |
| 563 | ␉if (id != chipid) {␊ |
| 564 | ␉␉msg_perr("PC8736x: unexpected ID %02x (expected %02x)\n",␊ |
| 565 | ␉␉␉ id, chipid);␊ |
| 566 | ␉␉return -1;␊ |
| 567 | ␉}␊ |
| 568 | ␊ |
| 569 | ␉sio_write(0x2E, 0x07, 0x07);␉␉/* Select GPIO device. */␊ |
| 570 | ␉baseport = (sio_read(0x2E, 0x60) << 8) | sio_read(0x2E, 0x61);␊ |
| 571 | ␉if ((baseport & 0xFFF0) == 0xFFF0 || baseport == 0) {␊ |
| 572 | ␉␉msg_perr("PC87360: invalid GPIO base address %04x\n",␊ |
| 573 | ␉␉␉ baseport);␊ |
| 574 | ␉␉return -1;␊ |
| 575 | ␉}␊ |
| 576 | ␉sio_mask (0x2E, 0x30, 0x01, 0x01);␉/* Enable logical device. */␊ |
| 577 | ␉sio_write(0x2E, 0xF0, gpio_bank * 16 + gpio_pin);␊ |
| 578 | ␉sio_mask (0x2E, 0xF1, 0x01, 0x01);␉/* Make pin output. */␊ |
| 579 | ␊ |
| 580 | ␉val = INB(baseport + bankbase[gpio_bank]);␊ |
| 581 | ␉if (raise)␊ |
| 582 | ␉␉val |= 1 << gpio_pin;␊ |
| 583 | ␉else␊ |
| 584 | ␉␉val &= ~(1 << gpio_pin);␊ |
| 585 | ␉OUTB(val, baseport + bankbase[gpio_bank]);␊ |
| 586 | ␊ |
| 587 | ␉return 0;␊ |
| 588 | }␊ |
| 589 | ␊ |
| 590 | /*␊ |
| 591 | * VIA VT823x: Set one of the GPIO pins.␊ |
| 592 | */␊ |
| 593 | static int via_vt823x_gpio_set(uint8_t gpio, int raise)␊ |
| 594 | {␊ |
| 595 | ␉struct pci_dev *dev;␊ |
| 596 | ␉uint16_t base;␊ |
| 597 | ␉uint8_t val, bit, offset;␊ |
| 598 | ␊ |
| 599 | ␉dev = pci_dev_find_vendorclass(0x1106, 0x0601);␊ |
| 600 | ␉switch (dev->device_id) {␊ |
| 601 | ␉case 0x3177:␉/* VT8235 */␊ |
| 602 | ␉case 0x3227:␉/* VT8237R */␊ |
| 603 | ␉case 0x3337:␉/* VT8237A */␊ |
| 604 | ␉␉break;␊ |
| 605 | ␉default:␊ |
| 606 | ␉␉msg_perr("\nERROR: VT823x ISA bridge not found.\n");␊ |
| 607 | ␉␉return -1;␊ |
| 608 | ␉}␊ |
| 609 | ␊ |
| 610 | ␉if ((gpio >= 12) && (gpio <= 15)) {␊ |
| 611 | ␉␉/* GPIO12-15 -> output */␊ |
| 612 | ␉␉val = pci_read_byte(dev, 0xE4);␊ |
| 613 | ␉␉val |= 0x10;␊ |
| 614 | ␉␉pci_write_byte(dev, 0xE4, val);␊ |
| 615 | ␉} else if (gpio == 9) {␊ |
| 616 | ␉␉/* GPIO9 -> Output */␊ |
| 617 | ␉␉val = pci_read_byte(dev, 0xE4);␊ |
| 618 | ␉␉val |= 0x20;␊ |
| 619 | ␉␉pci_write_byte(dev, 0xE4, val);␊ |
| 620 | ␉} else if (gpio == 5) {␊ |
| 621 | ␉␉val = pci_read_byte(dev, 0xE4);␊ |
| 622 | ␉␉val |= 0x01;␊ |
| 623 | ␉␉pci_write_byte(dev, 0xE4, val);␊ |
| 624 | ␉} else {␊ |
| 625 | ␉␉msg_perr("\nERROR: "␊ |
| 626 | ␉␉␉"VT823x GPIO%02d is not implemented.\n", gpio);␊ |
| 627 | ␉␉return -1;␊ |
| 628 | ␉}␊ |
| 629 | ␊ |
| 630 | ␉/* We need the I/O Base Address for this board's flash enable. */␊ |
| 631 | ␉base = pci_read_word(dev, 0x88) & 0xff80;␊ |
| 632 | ␊ |
| 633 | ␉offset = 0x4C + gpio / 8;␊ |
| 634 | ␉bit = 0x01 << (gpio % 8);␊ |
| 635 | ␊ |
| 636 | ␉val = INB(base + offset);␊ |
| 637 | ␉if (raise)␊ |
| 638 | ␉␉val |= bit;␊ |
| 639 | ␉else␊ |
| 640 | ␉␉val &= ~bit;␊ |
| 641 | ␉OUTB(val, base + offset);␊ |
| 642 | ␊ |
| 643 | ␉return 0;␊ |
| 644 | }␊ |
| 645 | ␊ |
| 646 | /*␊ |
| 647 | * Suited for:␊ |
| 648 | * - ASUS M2V-MX: VIA K8M890 + VT8237A + IT8716F␊ |
| 649 | */␊ |
| 650 | static int via_vt823x_gpio5_raise(void)␊ |
| 651 | {␊ |
| 652 | ␉/* On M2V-MX: GPO5 is connected to WP# and TBL#. */␊ |
| 653 | ␉return via_vt823x_gpio_set(5, 1);␊ |
| 654 | }␊ |
| 655 | ␊ |
| 656 | /*␊ |
| 657 | * Suited for:␊ |
| 658 | * - VIA EPIA EK & N & NL␊ |
| 659 | */␊ |
| 660 | static int via_vt823x_gpio9_raise(void)␊ |
| 661 | {␊ |
| 662 | ␉return via_vt823x_gpio_set(9, 1);␊ |
| 663 | }␊ |
| 664 | ␊ |
| 665 | /*␊ |
| 666 | * Suited for:␊ |
| 667 | * - VIA EPIA M and MII (and maybe other CLE266 based EPIAs)␊ |
| 668 | *␊ |
| 669 | * We don't need to do this for EPIA M when using coreboot, GPIO15 is never␊ |
| 670 | * lowered there.␊ |
| 671 | */␊ |
| 672 | static int via_vt823x_gpio15_raise(void)␊ |
| 673 | {␊ |
| 674 | ␉return via_vt823x_gpio_set(15, 1);␊ |
| 675 | }␊ |
| 676 | ␊ |
| 677 | /*␊ |
| 678 | * Winbond W83697HF Super I/O + VIA VT8235 southbridge␊ |
| 679 | *␊ |
| 680 | * Suited for:␊ |
| 681 | * - MSI KT4V and KT4V-L: AMD K7 + VIA KT400 + VT8235␊ |
| 682 | * - MSI KT4 Ultra: AMD K7 + VIA KT400 + VT8235␊ |
| 683 | */␊ |
| 684 | static int board_msi_kt4v(void)␊ |
| 685 | {␊ |
| 686 | ␉int ret;␊ |
| 687 | ␊ |
| 688 | ␉ret = via_vt823x_gpio_set(12, 1);␊ |
| 689 | ␉w836xx_memw_enable(0x2E);␊ |
| 690 | ␊ |
| 691 | ␉return ret;␊ |
| 692 | }␊ |
| 693 | ␊ |
| 694 | /*␊ |
| 695 | * Suited for:␊ |
| 696 | * - ASUS P5A␊ |
| 697 | *␊ |
| 698 | * This is rather nasty code, but there's no way to do this cleanly.␊ |
| 699 | * We're basically talking to some unknown device on SMBus, my guess␊ |
| 700 | * is that it is the Winbond W83781D that lives near the DIP BIOS.␊ |
| 701 | */␊ |
| 702 | static int board_asus_p5a(void)␊ |
| 703 | {␊ |
| 704 | ␉uint8_t tmp;␊ |
| 705 | ␉int i;␊ |
| 706 | ␊ |
| 707 | #define ASUSP5A_LOOP 5000␊ |
| 708 | ␊ |
| 709 | ␉OUTB(0x00, 0xE807);␊ |
| 710 | ␉OUTB(0xEF, 0xE803);␊ |
| 711 | ␊ |
| 712 | ␉OUTB(0xFF, 0xE800);␊ |
| 713 | ␊ |
| 714 | ␉for (i = 0; i < ASUSP5A_LOOP; i++) {␊ |
| 715 | ␉␉OUTB(0xE1, 0xFF);␊ |
| 716 | ␉␉if (INB(0xE800) & 0x04)␊ |
| 717 | ␉␉␉break;␊ |
| 718 | ␉}␊ |
| 719 | ␊ |
| 720 | ␉if (i == ASUSP5A_LOOP) {␊ |
| 721 | ␉␉msg_perr("Unable to contact device.\n");␊ |
| 722 | ␉␉return -1;␊ |
| 723 | ␉}␊ |
| 724 | ␊ |
| 725 | ␉OUTB(0x20, 0xE801);␊ |
| 726 | ␉OUTB(0x20, 0xE1);␊ |
| 727 | ␊ |
| 728 | ␉OUTB(0xFF, 0xE802);␊ |
| 729 | ␊ |
| 730 | ␉for (i = 0; i < ASUSP5A_LOOP; i++) {␊ |
| 731 | ␉␉tmp = INB(0xE800);␊ |
| 732 | ␉␉if (tmp & 0x70)␊ |
| 733 | ␉␉␉break;␊ |
| 734 | ␉}␊ |
| 735 | ␊ |
| 736 | ␉if ((i == ASUSP5A_LOOP) || !(tmp & 0x10)) {␊ |
| 737 | ␉␉msg_perr("Failed to read device.\n");␊ |
| 738 | ␉␉return -1;␊ |
| 739 | ␉}␊ |
| 740 | ␊ |
| 741 | ␉tmp = INB(0xE804);␊ |
| 742 | ␉tmp &= ~0x02;␊ |
| 743 | ␊ |
| 744 | ␉OUTB(0x00, 0xE807);␊ |
| 745 | ␉OUTB(0xEE, 0xE803);␊ |
| 746 | ␊ |
| 747 | ␉OUTB(tmp, 0xE804);␊ |
| 748 | ␊ |
| 749 | ␉OUTB(0xFF, 0xE800);␊ |
| 750 | ␉OUTB(0xE1, 0xFF);␊ |
| 751 | ␊ |
| 752 | ␉OUTB(0x20, 0xE801);␊ |
| 753 | ␉OUTB(0x20, 0xE1);␊ |
| 754 | ␊ |
| 755 | ␉OUTB(0xFF, 0xE802);␊ |
| 756 | ␊ |
| 757 | ␉for (i = 0; i < ASUSP5A_LOOP; i++) {␊ |
| 758 | ␉␉tmp = INB(0xE800);␊ |
| 759 | ␉␉if (tmp & 0x70)␊ |
| 760 | ␉␉␉break;␊ |
| 761 | ␉}␊ |
| 762 | ␊ |
| 763 | ␉if ((i == ASUSP5A_LOOP) || !(tmp & 0x10)) {␊ |
| 764 | ␉␉msg_perr("Failed to write to device.\n");␊ |
| 765 | ␉␉return -1;␊ |
| 766 | ␉}␊ |
| 767 | ␊ |
| 768 | ␉return 0;␊ |
| 769 | }␊ |
| 770 | ␊ |
| 771 | /*␊ |
| 772 | * Set GPIO lines in the Broadcom HT-1000 southbridge.␊ |
| 773 | *␊ |
| 774 | * It's not a Super I/O but it uses the same index/data port method.␊ |
| 775 | */␊ |
| 776 | static int board_hp_dl145_g3_enable(void)␊ |
| 777 | {␊ |
| 778 | ␉/* GPIO 0 reg from PM regs */␊ |
| 779 | ␉/* Set GPIO 2 and 5 high, connected to flash WP# and TBL# pins. */␊ |
| 780 | ␉sio_mask(0xcd6, 0x44, 0x24, 0x24);␊ |
| 781 | ␊ |
| 782 | ␉return 0;␊ |
| 783 | }␊ |
| 784 | ␊ |
| 785 | /*␊ |
| 786 | * Set GPIO lines in the Broadcom HT-1000 southbridge.␊ |
| 787 | *␊ |
| 788 | * It's not a Super I/O but it uses the same index/data port method.␊ |
| 789 | */␊ |
| 790 | static int board_hp_dl165_g6_enable(void)␊ |
| 791 | {␊ |
| 792 | ␉/* Variant of DL145, with slightly different pin placement. */␊ |
| 793 | ␉sio_mask(0xcd6, 0x44, 0x80, 0x80); /* TBL# */␊ |
| 794 | ␉sio_mask(0xcd6, 0x46, 0x04, 0x04); /* WP# */␊ |
| 795 | ␊ |
| 796 | ␉return 0;␊ |
| 797 | }␊ |
| 798 | ␊ |
| 799 | static int board_ibm_x3455(void)␊ |
| 800 | {␊ |
| 801 | ␉/* Raise GPIO13. */␊ |
| 802 | ␉sio_mask(0xcd6, 0x45, 0x20, 0x20);␊ |
| 803 | ␊ |
| 804 | ␉return 0;␊ |
| 805 | }␊ |
| 806 | ␊ |
| 807 | /*␊ |
| 808 | * Suited for:␊ |
| 809 | * - Shuttle FN25 (SN25P): AMD S939 + NVIDIA CK804 (nForce4)␊ |
| 810 | */␊ |
| 811 | static int board_shuttle_fn25(void)␊ |
| 812 | {␊ |
| 813 | ␉struct pci_dev *dev;␊ |
| 814 | ␊ |
| 815 | ␉dev = pci_dev_find(0x10DE, 0x0050);␉/* NVIDIA CK804 ISA bridge. */␊ |
| 816 | ␉if (!dev) {␊ |
| 817 | ␉␉msg_perr("\nERROR: NVIDIA nForce4 ISA bridge not found.\n");␊ |
| 818 | ␉␉return -1;␊ |
| 819 | ␉}␊ |
| 820 | ␊ |
| 821 | ␉/* One of those bits seems to be connected to TBL#, but -ENOINFO. */␊ |
| 822 | ␉pci_write_byte(dev, 0x92, 0);␊ |
| 823 | ␊ |
| 824 | ␉return 0;␊ |
| 825 | }␊ |
| 826 | ␊ |
| 827 | /*␊ |
| 828 | * Suited for:␊ |
| 829 | * - Elitegroup GeForce6100SM-M: NVIDIA MCP61 + ITE IT8726F␊ |
| 830 | */␊ |
| 831 | static int board_ecs_geforce6100sm_m(void)␊ |
| 832 | {␊ |
| 833 | ␉struct pci_dev *dev;␊ |
| 834 | ␉uint32_t tmp;␊ |
| 835 | ␊ |
| 836 | ␉dev = pci_dev_find(0x10DE, 0x03EB); /* NVIDIA MCP61 SMBus. */␊ |
| 837 | ␉if (!dev) {␊ |
| 838 | ␉␉msg_perr("\nERROR: NVIDIA MCP61 SMBus not found.\n");␊ |
| 839 | ␉␉return -1;␊ |
| 840 | ␉}␊ |
| 841 | ␊ |
| 842 | ␉tmp = pci_read_byte(dev, 0xE0);␊ |
| 843 | ␉tmp &= ~(1 << 3);␊ |
| 844 | ␉pci_write_byte(dev, 0xE0, tmp);␊ |
| 845 | ␊ |
| 846 | ␉return 0;␊ |
| 847 | }␊ |
| 848 | ␊ |
| 849 | /*␊ |
| 850 | * Very similar to AMD 8111 IO Hub.␊ |
| 851 | */␊ |
| 852 | static int nvidia_mcp_gpio_set(int gpio, int raise)␊ |
| 853 | {␊ |
| 854 | ␉struct pci_dev *dev;␊ |
| 855 | ␉uint16_t base, devclass;␊ |
| 856 | ␉uint8_t tmp;␊ |
| 857 | ␊ |
| 858 | ␉if ((gpio < 0) || (gpio >= 0x40)) {␊ |
| 859 | ␉␉msg_perr("\nERROR: unsupported GPIO: %d.\n", gpio);␊ |
| 860 | ␉␉return -1;␊ |
| 861 | ␉}␊ |
| 862 | ␊ |
| 863 | ␉/* Check for the ISA bridge first. */␊ |
| 864 | ␉dev = pci_dev_find_vendorclass(0x10DE, 0x0601);␊ |
| 865 | ␉switch (dev->device_id) {␊ |
| 866 | ␉case 0x0030: /* CK804 */␊ |
| 867 | ␉case 0x0050: /* MCP04 */␊ |
| 868 | ␉case 0x0060: /* MCP2 */␊ |
| 869 | ␉case 0x00E0: /* CK8 */␊ |
| 870 | ␉␉break;␊ |
| 871 | ␉case 0x0260: /* MCP51 */␊ |
| 872 | ␉case 0x0261: /* MCP51 */␊ |
| 873 | ␉case 0x0364: /* MCP55 */␊ |
| 874 | ␉␉/* find SMBus controller on *this* southbridge */␊ |
| 875 | ␉␉/* The infamous Tyan S2915-E has two south bridges; they are␊ |
| 876 | ␉␉ easily told apart from each other by the class of the ␊ |
| 877 | ␉␉ LPC bridge, but have the same SMBus bridge IDs */␊ |
| 878 | ␉␉if (dev->func != 0) {␊ |
| 879 | ␉␉␉msg_perr("MCP LPC bridge at unexpected function"␊ |
| 880 | ␉␉␉ " number %d\n", dev->func);␊ |
| 881 | ␉␉␉return -1;␊ |
| 882 | ␉␉}␊ |
| 883 | ␊ |
| 884 | #if PCI_LIB_VERSION >= 0x020200␊ |
| 885 | ␉␉dev = pci_get_dev(pacc, dev->domain, dev->bus, dev->dev, 1);␊ |
| 886 | #else␊ |
| 887 | ␉␉/* pciutils/libpci before version 2.2 is too old to support␊ |
| 888 | ␉␉ * PCI domains. Such old machines usually don't have domains␊ |
| 889 | ␉␉ * besides domain 0, so this is not a problem.␊ |
| 890 | ␉␉ */␊ |
| 891 | ␉␉dev = pci_get_dev(pacc, dev->bus, dev->dev, 1);␊ |
| 892 | #endif␊ |
| 893 | ␉␉if (!dev) {␊ |
| 894 | ␉␉␉msg_perr("MCP SMBus controller could not be found\n");␊ |
| 895 | ␉␉␉return -1;␊ |
| 896 | ␉␉}␊ |
| 897 | ␉␉devclass = pci_read_word(dev, PCI_CLASS_DEVICE);␊ |
| 898 | ␉␉if (devclass != 0x0C05) {␊ |
| 899 | ␉␉␉msg_perr("Unexpected device class %04x for SMBus"␊ |
| 900 | ␉␉␉ " controller\n", devclass);␊ |
| 901 | ␉␉␉return -1;␊ |
| 902 | ␉␉}␊ |
| 903 | ␉␉break;␊ |
| 904 | ␉default:␊ |
| 905 | ␉␉msg_perr("\nERROR: no NVIDIA LPC/SMBus controller found.\n");␊ |
| 906 | ␉␉return -1;␊ |
| 907 | ␉}␊ |
| 908 | ␊ |
| 909 | ␉base = pci_read_long(dev, 0x64) & 0x0000FF00; /* System control area */␊ |
| 910 | ␉base += 0xC0;␊ |
| 911 | ␊ |
| 912 | ␉tmp = INB(base + gpio);␊ |
| 913 | ␉tmp &= ~0x0F; /* null lower nibble */␊ |
| 914 | ␉tmp |= 0x04; /* gpio -> output. */␊ |
| 915 | ␉if (raise)␊ |
| 916 | ␉␉tmp |= 0x01;␊ |
| 917 | ␉OUTB(tmp, base + gpio);␊ |
| 918 | ␊ |
| 919 | ␉return 0;␊ |
| 920 | }␊ |
| 921 | ␊ |
| 922 | /*␊ |
| 923 | * Suited for:␊ |
| 924 | * - ASUS A8M2N-LA (HP OEM "NodusM3-GL8E"): NVIDIA MCP51␊ |
| 925 | * - ASUS A8N-LA (HP OEM "Nagami-GL8E"): NVIDIA MCP51␊ |
| 926 | * - ASUS M2NBP-VM CSM: NVIDIA MCP51␊ |
| 927 | */␊ |
| 928 | static int nvidia_mcp_gpio0_raise(void)␊ |
| 929 | {␊ |
| 930 | ␉return nvidia_mcp_gpio_set(0x00, 1);␊ |
| 931 | }␊ |
| 932 | ␊ |
| 933 | /*␊ |
| 934 | * Suited for:␊ |
| 935 | * - abit KN8 Ultra: NVIDIA CK804␊ |
| 936 | */␊ |
| 937 | static int nvidia_mcp_gpio2_lower(void)␊ |
| 938 | {␊ |
| 939 | ␉return nvidia_mcp_gpio_set(0x02, 0);␊ |
| 940 | }␊ |
| 941 | ␊ |
| 942 | /*␊ |
| 943 | * Suited for:␊ |
| 944 | * - Foxconn 6150K8MD-8EKRSH: Socket 939 + NVIDIA MCP51␊ |
| 945 | * - MSI K8N Neo4: NVIDIA CK804. TODO: Should probably be K8N Neo4 Platinum, see http://www.coreboot.org/pipermail/flashrom/2010-August/004362.html.␊ |
| 946 | * - MSI K8NGM2-L: NVIDIA MCP51␊ |
| 947 | */␊ |
| 948 | static int nvidia_mcp_gpio2_raise(void)␊ |
| 949 | {␊ |
| 950 | ␉return nvidia_mcp_gpio_set(0x02, 1);␊ |
| 951 | }␊ |
| 952 | ␊ |
| 953 | /*␊ |
| 954 | * Suited for:␊ |
| 955 | * - EPoX EP-8NPA7I: Socket 754 + NVIDIA nForce4 4X␊ |
| 956 | */␊ |
| 957 | static int nvidia_mcp_gpio4_raise(void)␊ |
| 958 | {␊ |
| 959 | ␉return nvidia_mcp_gpio_set(0x04, 1);␊ |
| 960 | }␊ |
| 961 | ␊ |
| 962 | /*␊ |
| 963 | * Suited for:␊ |
| 964 | * - HP xw9400 (Tyan S2915-E OEM): Dual(!) NVIDIA MCP55␊ |
| 965 | *␊ |
| 966 | * Notes: a) There are two MCP55 chips, so also two SMBus bridges on that␊ |
| 967 | * board. We can't tell the SMBus logical devices apart, but we␊ |
| 968 | * can tell the LPC bridge functions apart.␊ |
| 969 | * We need to choose the SMBus bridge next to the LPC bridge with␊ |
| 970 | * ID 0x364 and the "LPC bridge" class.␊ |
| 971 | * b) #TBL is hardwired on that board to a pull-down. It can be␊ |
| 972 | * overridden by connecting the two solder points next to F2.␊ |
| 973 | */␊ |
| 974 | static int nvidia_mcp_gpio5_raise(void)␊ |
| 975 | {␊ |
| 976 | ␉return nvidia_mcp_gpio_set(0x05, 1);␊ |
| 977 | }␊ |
| 978 | ␊ |
| 979 | /*␊ |
| 980 | * Suited for:␊ |
| 981 | * - abit NF7-S: NVIDIA CK804␊ |
| 982 | */␊ |
| 983 | static int nvidia_mcp_gpio8_raise(void)␊ |
| 984 | {␊ |
| 985 | ␉return nvidia_mcp_gpio_set(0x08, 1);␊ |
| 986 | }␊ |
| 987 | ␊ |
| 988 | /*␊ |
| 989 | * Suited for:␊ |
| 990 | * - GIGABYTE GA-K8NS Pro-939: Socket 939 + NVIDIA nForce3 + CK8␊ |
| 991 | */␊ |
| 992 | static int nvidia_mcp_gpio0a_raise(void)␊ |
| 993 | {␊ |
| 994 | ␉return nvidia_mcp_gpio_set(0x0a, 1);␊ |
| 995 | }␊ |
| 996 | ␊ |
| 997 | /*␊ |
| 998 | * Suited for:␊ |
| 999 | * - MSI K8N Neo2 Platinum: Socket 939 + nForce3 Ultra + CK8␊ |
| 1000 | */␊ |
| 1001 | static int nvidia_mcp_gpio0c_raise(void)␊ |
| 1002 | {␊ |
| 1003 | ␉return nvidia_mcp_gpio_set(0x0c, 1);␊ |
| 1004 | }␊ |
| 1005 | ␊ |
| 1006 | /*␊ |
| 1007 | * Suited for:␊ |
| 1008 | * - abit NF-M2 nView: Socket AM2 + NVIDIA MCP51␊ |
| 1009 | */␊ |
| 1010 | static int nvidia_mcp_gpio4_lower(void)␊ |
| 1011 | {␊ |
| 1012 | ␉return nvidia_mcp_gpio_set(0x04, 0);␊ |
| 1013 | }␊ |
| 1014 | ␊ |
| 1015 | /*␊ |
| 1016 | * Suited for:␊ |
| 1017 | * - ASUS P5ND2-SLI Deluxe: LGA775 + nForce4 SLI + MCP04␊ |
| 1018 | */␊ |
| 1019 | static int nvidia_mcp_gpio10_raise(void)␊ |
| 1020 | {␊ |
| 1021 | ␉return nvidia_mcp_gpio_set(0x10, 1);␊ |
| 1022 | }␊ |
| 1023 | ␊ |
| 1024 | /*␊ |
| 1025 | * Suited for:␊ |
| 1026 | * - GIGABYTE GA-K8N-SLI: AMD socket 939 + NVIDIA CK804 + ITE IT8712F␊ |
| 1027 | */␊ |
| 1028 | static int nvidia_mcp_gpio21_raise(void)␊ |
| 1029 | {␊ |
| 1030 | ␉return nvidia_mcp_gpio_set(0x21, 0x01);␊ |
| 1031 | }␊ |
| 1032 | ␊ |
| 1033 | /*␊ |
| 1034 | * Suited for:␊ |
| 1035 | * - EPoX EP-8RDA3+: Socket A + nForce2 Ultra 400 + MCP2␊ |
| 1036 | */␊ |
| 1037 | static int nvidia_mcp_gpio31_raise(void)␊ |
| 1038 | {␊ |
| 1039 | ␉return nvidia_mcp_gpio_set(0x31, 0x01);␊ |
| 1040 | }␊ |
| 1041 | ␊ |
| 1042 | /*␊ |
| 1043 | * Suited for:␊ |
| 1044 | * - GIGABYTE GA-K8N51GMF: Socket 754 + Geforce 6100 + MCP51␊ |
| 1045 | * - GIGABYTE GA-K8N51GMF-9: Socket 939 + Geforce 6100 + MCP51␊ |
| 1046 | */␊ |
| 1047 | static int nvidia_mcp_gpio3b_raise(void)␊ |
| 1048 | {␊ |
| 1049 | ␉return nvidia_mcp_gpio_set(0x3b, 1);␊ |
| 1050 | }␊ |
| 1051 | ␊ |
| 1052 | /*␊ |
| 1053 | * Suited for:␊ |
| 1054 | * - Sun Ultra 40 M2: Dual Socket F (1207) + MCP55␊ |
| 1055 | */␊ |
| 1056 | static int board_sun_ultra_40_m2(void)␊ |
| 1057 | {␊ |
| 1058 | ␉int ret;␊ |
| 1059 | ␉uint8_t reg;␊ |
| 1060 | ␉uint16_t base;␊ |
| 1061 | ␉struct pci_dev *dev;␊ |
| 1062 | ␊ |
| 1063 | ␉ret = nvidia_mcp_gpio4_lower();␊ |
| 1064 | ␉if (ret)␊ |
| 1065 | ␉␉return ret;␊ |
| 1066 | ␊ |
| 1067 | ␉dev = pci_dev_find(0x10de, 0x0364); /* NVIDIA MCP55 LPC bridge */␊ |
| 1068 | ␉if (!dev) {␊ |
| 1069 | ␉␉msg_perr("\nERROR: NVIDIA MCP55 LPC bridge not found.\n");␊ |
| 1070 | ␉␉return -1;␊ |
| 1071 | ␉}␊ |
| 1072 | ␊ |
| 1073 | ␉base = pci_read_word(dev, 0xb4); /* some IO BAR? */␊ |
| 1074 | ␉if (!base)␊ |
| 1075 | ␉␉return -1;␊ |
| 1076 | ␊ |
| 1077 | ␉reg = INB(base + 0x4b);␊ |
| 1078 | ␉reg |= 0x10;␊ |
| 1079 | ␉OUTB(reg, base + 0x4b);␊ |
| 1080 | ␊ |
| 1081 | ␉return 0;␊ |
| 1082 | }␊ |
| 1083 | ␊ |
| 1084 | /*␊ |
| 1085 | * Suited for:␊ |
| 1086 | * - Artec Group DBE61 and DBE62␊ |
| 1087 | */␊ |
| 1088 | static int board_artecgroup_dbe6x(void)␊ |
| 1089 | {␊ |
| 1090 | #define DBE6x_MSR_DIVIL_BALL_OPTS␉0x51400015␊ |
| 1091 | #define DBE6x_PRI_BOOT_LOC_SHIFT␉2␊ |
| 1092 | #define DBE6x_BOOT_OP_LATCHED_SHIFT␉8␊ |
| 1093 | #define DBE6x_SEC_BOOT_LOC_SHIFT␉10␊ |
| 1094 | #define DBE6x_PRI_BOOT_LOC␉␉(3 << DBE6x_PRI_BOOT_LOC_SHIFT)␊ |
| 1095 | #define DBE6x_BOOT_OP_LATCHED␉␉(3 << DBE6x_BOOT_OP_LATCHED_SHIFT)␊ |
| 1096 | #define DBE6x_SEC_BOOT_LOC␉␉(3 << DBE6x_SEC_BOOT_LOC_SHIFT)␊ |
| 1097 | #define DBE6x_BOOT_LOC_FLASH␉␉2␊ |
| 1098 | #define DBE6x_BOOT_LOC_FWHUB␉␉3␊ |
| 1099 | ␊ |
| 1100 | ␉msr_t msr;␊ |
| 1101 | ␉unsigned long boot_loc;␊ |
| 1102 | ␊ |
| 1103 | ␉/* Geode only has a single core */␊ |
| 1104 | ␉if (setup_cpu_msr(0))␊ |
| 1105 | ␉␉return -1;␊ |
| 1106 | ␊ |
| 1107 | ␉msr = rdmsr(DBE6x_MSR_DIVIL_BALL_OPTS);␊ |
| 1108 | ␊ |
| 1109 | ␉if ((msr.lo & (DBE6x_BOOT_OP_LATCHED)) ==␊ |
| 1110 | ␉ (DBE6x_BOOT_LOC_FWHUB << DBE6x_BOOT_OP_LATCHED_SHIFT))␊ |
| 1111 | ␉␉boot_loc = DBE6x_BOOT_LOC_FWHUB;␊ |
| 1112 | ␉else␊ |
| 1113 | ␉␉boot_loc = DBE6x_BOOT_LOC_FLASH;␊ |
| 1114 | ␊ |
| 1115 | ␉msr.lo &= ~(DBE6x_PRI_BOOT_LOC | DBE6x_SEC_BOOT_LOC);␊ |
| 1116 | ␉msr.lo |= ((boot_loc << DBE6x_PRI_BOOT_LOC_SHIFT) |␊ |
| 1117 | ␉␉ (boot_loc << DBE6x_SEC_BOOT_LOC_SHIFT));␊ |
| 1118 | ␊ |
| 1119 | ␉wrmsr(DBE6x_MSR_DIVIL_BALL_OPTS, msr);␊ |
| 1120 | ␊ |
| 1121 | ␉cleanup_cpu_msr();␊ |
| 1122 | ␊ |
| 1123 | ␉return 0;␊ |
| 1124 | }␊ |
| 1125 | ␊ |
| 1126 | /*␊ |
| 1127 | * Suited for:␊ |
| 1128 | * - ASUS A8AE-LE (Codename AmberineM; used in Compaq Presario 061)␊ |
| 1129 | * Datasheet(s) used:␊ |
| 1130 | * - AMD document 43009 "AMD SB700/710/750 Register Reference Guide" rev. 1.00␊ |
| 1131 | */␊ |
| 1132 | static int amd_sbxxx_gpio9_raise(void)␊ |
| 1133 | {␊ |
| 1134 | ␉struct pci_dev *dev;␊ |
| 1135 | ␉uint32_t reg;␊ |
| 1136 | ␊ |
| 1137 | ␉dev = pci_dev_find(0x1002, 0x4372); /* AMD SMBus controller */␊ |
| 1138 | ␉if (!dev) {␊ |
| 1139 | ␉␉msg_perr("\nERROR: AMD SMBus Controller (0x4372) not found.\n");␊ |
| 1140 | ␉␉return -1;␊ |
| 1141 | ␉}␊ |
| 1142 | ␊ |
| 1143 | ␉reg = pci_read_long(dev, 0xA8); /* GPIO_12_to_4_Cntrl CI_Reg: A8h-ABh */␊ |
| 1144 | ␉/* enable output (0: enable, 1: tristate):␊ |
| 1145 | ␉ GPIO9 output enable is at bit 5 in 0xA9 */␊ |
| 1146 | ␉reg &= ~((uint32_t)1<<(8+5));␊ |
| 1147 | ␉/* raise:␊ |
| 1148 | ␉ GPIO9 output register is at bit 5 in 0xA8 */␊ |
| 1149 | ␉reg |= (1<<5);␊ |
| 1150 | ␉pci_write_long(dev, 0xA8, reg);␊ |
| 1151 | ␊ |
| 1152 | ␉return 0;␊ |
| 1153 | }␊ |
| 1154 | ␊ |
| 1155 | /*␊ |
| 1156 | * Helper function to raise/drop a given gpo line on Intel PIIX4{,E,M}.␊ |
| 1157 | */␊ |
| 1158 | static int intel_piix4_gpo_set(unsigned int gpo, int raise)␊ |
| 1159 | {␊ |
| 1160 | ␉unsigned int gpo_byte, gpo_bit;␊ |
| 1161 | ␉struct pci_dev *dev;␊ |
| 1162 | ␉uint32_t tmp, base;␊ |
| 1163 | ␊ |
| 1164 | ␉/* GPO{0,8,27,28,30} are always available. */␊ |
| 1165 | ␉static const uint32_t nonmuxed_gpos = 0x58000101;␊ |
| 1166 | ␊ |
| 1167 | ␉static const struct {unsigned int reg, mask, value; } piix4_gpo[] = {␊ |
| 1168 | ␉␉{0},␊ |
| 1169 | ␉␉{0xB0, 0x0001, 0x0000}, /* GPO1... */␊ |
| 1170 | ␉␉{0xB0, 0x0001, 0x0000},␊ |
| 1171 | ␉␉{0xB0, 0x0001, 0x0000},␊ |
| 1172 | ␉␉{0xB0, 0x0001, 0x0000},␊ |
| 1173 | ␉␉{0xB0, 0x0001, 0x0000},␊ |
| 1174 | ␉␉{0xB0, 0x0001, 0x0000},␊ |
| 1175 | ␉␉{0xB0, 0x0001, 0x0000}, /* ...GPO7: GENCFG bit 0 */␊ |
| 1176 | ␉␉{0},␊ |
| 1177 | ␉␉{0xB0, 0x0100, 0x0000}, /* GPO9: GENCFG bit 8 */␊ |
| 1178 | ␉␉{0xB0, 0x0200, 0x0000}, /* GPO10: GENCFG bit 9 */␊ |
| 1179 | ␉␉{0xB0, 0x0400, 0x0000}, /* GPO11: GENCFG bit 10 */␊ |
| 1180 | ␉␉{0x4E, 0x0100, 0x0000}, /* GPO12... */␊ |
| 1181 | ␉␉{0x4E, 0x0100, 0x0000},␊ |
| 1182 | ␉␉{0x4E, 0x0100, 0x0000}, /* ...GPO14: XBCS bit 8 */␊ |
| 1183 | ␉␉{0xB2, 0x0002, 0x0002}, /* GPO15... */␊ |
| 1184 | ␉␉{0xB2, 0x0002, 0x0002}, /* ...GPO16: GENCFG bit 17 */␊ |
| 1185 | ␉␉{0xB2, 0x0004, 0x0004}, /* GPO17: GENCFG bit 18 */␊ |
| 1186 | ␉␉{0xB2, 0x0008, 0x0008}, /* GPO18: GENCFG bit 19 */␊ |
| 1187 | ␉␉{0xB2, 0x0010, 0x0010}, /* GPO19: GENCFG bit 20 */␊ |
| 1188 | ␉␉{0xB2, 0x0020, 0x0020}, /* GPO20: GENCFG bit 21 */␊ |
| 1189 | ␉␉{0xB2, 0x0040, 0x0040}, /* GPO21: GENCFG bit 22 */␊ |
| 1190 | ␉␉{0xB2, 0x1000, 0x1000}, /* GPO22... */␊ |
| 1191 | ␉␉{0xB2, 0x1000, 0x1000}, /* ...GPO23: GENCFG bit 28 */␊ |
| 1192 | ␉␉{0xB2, 0x2000, 0x2000}, /* GPO24: GENCFG bit 29 */␊ |
| 1193 | ␉␉{0xB2, 0x4000, 0x4000}, /* GPO25: GENCFG bit 30 */␊ |
| 1194 | ␉␉{0xB2, 0x8000, 0x8000}, /* GPO26: GENCFG bit 31 */␊ |
| 1195 | ␉␉{0},␊ |
| 1196 | ␉␉{0},␊ |
| 1197 | ␉␉{0x4E, 0x0100, 0x0000}, /* ...GPO29: XBCS bit 8 */␊ |
| 1198 | ␉␉{0}␊ |
| 1199 | ␉};␊ |
| 1200 | ␊ |
| 1201 | ␉dev = pci_dev_find(0x8086, 0x7110);␉/* Intel PIIX4 ISA bridge */␊ |
| 1202 | ␉if (!dev) {␊ |
| 1203 | ␉␉msg_perr("\nERROR: Intel PIIX4 ISA bridge not found.\n");␊ |
| 1204 | ␉␉return -1;␊ |
| 1205 | ␉}␊ |
| 1206 | ␊ |
| 1207 | ␉/* Sanity check. */␊ |
| 1208 | ␉if (gpo > 30) {␊ |
| 1209 | ␉␉msg_perr("\nERROR: Intel PIIX4 has no GPO%d.\n", gpo);␊ |
| 1210 | ␉␉return -1;␊ |
| 1211 | ␉}␊ |
| 1212 | ␊ |
| 1213 | ␉if ((((1 << gpo) & nonmuxed_gpos) == 0) &&␊ |
| 1214 | ␉ ((pci_read_word(dev, piix4_gpo[gpo].reg) & piix4_gpo[gpo].mask) !=␊ |
| 1215 | ␉ piix4_gpo[gpo].value)) {␊ |
| 1216 | ␉␉msg_perr("\nERROR: PIIX4 GPO%d not programmed for output.\n", gpo);␊ |
| 1217 | ␉␉return -1;␊ |
| 1218 | ␉}␊ |
| 1219 | ␊ |
| 1220 | ␉dev = pci_dev_find(0x8086, 0x7113);␉/* Intel PIIX4 PM */␊ |
| 1221 | ␉if (!dev) {␊ |
| 1222 | ␉␉msg_perr("\nERROR: Intel PIIX4 PM not found.\n");␊ |
| 1223 | ␉␉return -1;␊ |
| 1224 | ␉}␊ |
| 1225 | ␊ |
| 1226 | ␉/* PM IO base */␊ |
| 1227 | ␉base = pci_read_long(dev, 0x40) & 0x0000FFC0;␊ |
| 1228 | ␊ |
| 1229 | ␉gpo_byte = gpo >> 3;␊ |
| 1230 | ␉gpo_bit = gpo & 7;␊ |
| 1231 | ␉tmp = INB(base + 0x34 + gpo_byte); /* GPO register */␊ |
| 1232 | ␉if (raise)␊ |
| 1233 | ␉␉tmp |= 0x01 << gpo_bit;␊ |
| 1234 | ␉else␊ |
| 1235 | ␉␉tmp &= ~(0x01 << gpo_bit);␊ |
| 1236 | ␉OUTB(tmp, base + 0x34 + gpo_byte);␊ |
| 1237 | ␊ |
| 1238 | ␉return 0;␊ |
| 1239 | }␊ |
| 1240 | ␊ |
| 1241 | /*␊ |
| 1242 | * Suited for:␊ |
| 1243 | * - ASUS P2B-N␊ |
| 1244 | */␊ |
| 1245 | static int intel_piix4_gpo18_lower(void)␊ |
| 1246 | {␊ |
| 1247 | ␉return intel_piix4_gpo_set(18, 0);␊ |
| 1248 | }␊ |
| 1249 | ␊ |
| 1250 | /*␊ |
| 1251 | * Suited for:␊ |
| 1252 | * - MSI MS-6163 v2 (MS-6163 Pro): Intel 440BX + PIIX4E + Winbond W83977EF␊ |
| 1253 | */␊ |
| 1254 | static int intel_piix4_gpo14_raise(void)␊ |
| 1255 | {␊ |
| 1256 | ␉return intel_piix4_gpo_set(14, 1);␊ |
| 1257 | }␊ |
| 1258 | ␊ |
| 1259 | /*␊ |
| 1260 | * Suited for:␊ |
| 1261 | * - EPoX EP-BX3␊ |
| 1262 | */␊ |
| 1263 | static int intel_piix4_gpo22_raise(void)␊ |
| 1264 | {␊ |
| 1265 | ␉return intel_piix4_gpo_set(22, 1);␊ |
| 1266 | }␊ |
| 1267 | ␊ |
| 1268 | /*␊ |
| 1269 | * Suited for:␊ |
| 1270 | * - abit BM6␊ |
| 1271 | */␊ |
| 1272 | static int intel_piix4_gpo26_lower(void)␊ |
| 1273 | {␊ |
| 1274 | ␉return intel_piix4_gpo_set(26, 0);␊ |
| 1275 | }␊ |
| 1276 | ␊ |
| 1277 | /*␊ |
| 1278 | * Suited for:␊ |
| 1279 | * - Intel SE440BX-2␊ |
| 1280 | */␊ |
| 1281 | static int intel_piix4_gpo27_lower(void)␊ |
| 1282 | {␊ |
| 1283 | ␉return intel_piix4_gpo_set(27, 0);␊ |
| 1284 | }␊ |
| 1285 | ␊ |
| 1286 | /*␊ |
| 1287 | * Suited for:␊ |
| 1288 | * - Dell OptiPlex GX1␊ |
| 1289 | */␊ |
| 1290 | static int intel_piix4_gpo30_lower(void)␊ |
| 1291 | {␊ |
| 1292 | ␉return intel_piix4_gpo_set(30, 0);␊ |
| 1293 | }␊ |
| 1294 | ␊ |
| 1295 | /*␊ |
| 1296 | * Set a GPIO line on a given Intel ICH LPC controller.␊ |
| 1297 | */␊ |
| 1298 | static int intel_ich_gpio_set(int gpio, int raise)␊ |
| 1299 | {␊ |
| 1300 | ␉/* Table mapping the different Intel ICH LPC chipsets. */␊ |
| 1301 | ␉static struct {␊ |
| 1302 | ␉␉uint16_t id;␊ |
| 1303 | ␉␉uint8_t base_reg;␊ |
| 1304 | ␉␉uint32_t bank0;␊ |
| 1305 | ␉␉uint32_t bank1;␊ |
| 1306 | ␉␉uint32_t bank2;␊ |
| 1307 | ␉} intel_ich_gpio_table[] = {␊ |
| 1308 | ␉␉{0x2410, 0x58, 0x0FE30000, 0, 0}, /* 82801AA (ICH) */␊ |
| 1309 | ␉␉{0x2420, 0x58, 0x0FE30000, 0, 0}, /* 82801AB (ICH0) */␊ |
| 1310 | ␉␉{0x2440, 0x58, 0x1BFF391B, 0, 0}, /* 82801BA (ICH2) */␊ |
| 1311 | ␉␉{0x244C, 0x58, 0x1A23399B, 0, 0}, /* 82801BAM (ICH2M) */␊ |
| 1312 | ␉␉{0x2450, 0x58, 0x1BFF0000, 0, 0}, /* 82801E (C-ICH) */␊ |
| 1313 | ␉␉{0x2480, 0x58, 0x1BFF0000, 0x00000FFF, 0}, /* 82801CA (ICH3-S) */␊ |
| 1314 | ␉␉{0x248C, 0x58, 0x1A230000, 0x00000FFF, 0}, /* 82801CAM (ICH3-M) */␊ |
| 1315 | ␉␉{0x24C0, 0x58, 0x1BFF0000, 0x00000FFF, 0}, /* 82801DB/DBL (ICH4/ICH4-L) */␊ |
| 1316 | ␉␉{0x24CC, 0x58, 0x1A030000, 0x00000FFF, 0}, /* 82801DBM (ICH4-M) */␊ |
| 1317 | ␉␉{0x24D0, 0x58, 0x1BFF0000, 0x00030305, 0}, /* 82801EB/ER (ICH5/ICH5R) */␊ |
| 1318 | ␉␉{0x2640, 0x48, 0x1BFF0000, 0x00030307, 0}, /* 82801FB/FR (ICH6/ICH6R) */␊ |
| 1319 | ␉␉{0x2641, 0x48, 0x1BFF0000, 0x00030307, 0}, /* 82801FBM (ICH6M) */␊ |
| 1320 | ␉␉{0x27B8, 0x48, 0xFFFFFFFF, 0x000300FF, 0}, /* 82801GB/GR (ICH7 Family) */␊ |
| 1321 | ␉␉{0x27B9, 0x48, 0xFFEBFFFE, 0x000300FE, 0}, /* 82801GBM (ICH7-M) */␊ |
| 1322 | ␉␉{0x27BD, 0x48, 0xFFEBFFFE, 0x000300FE, 0}, /* 82801GHM (ICH7-M DH) */␊ |
| 1323 | ␉␉{0x2810, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HB/HR (ICH8/R) */␊ |
| 1324 | ␉␉{0x2811, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HBM (ICH8M-E) */␊ |
| 1325 | ␉␉{0x2812, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HH (ICH8DH) */␊ |
| 1326 | ␉␉{0x2814, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HO (ICH8DO) */␊ |
| 1327 | ␉␉{0x2815, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HEM (ICH8M) */␊ |
| 1328 | ␉␉{0x2912, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IH (ICH9DH) */␊ |
| 1329 | ␉␉{0x2914, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IO (ICH9DO) */␊ |
| 1330 | ␉␉{0x2916, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IR (ICH9R) */␊ |
| 1331 | ␉␉{0x2917, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IEM (ICH9M-E) */␊ |
| 1332 | ␉␉{0x2918, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IB (ICH9) */␊ |
| 1333 | ␉␉{0x2919, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IBM (ICH9M) */␊ |
| 1334 | ␉␉{0x3A14, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JDO (ICH10DO) */␊ |
| 1335 | ␉␉{0x3A16, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JIR (ICH10R) */␊ |
| 1336 | ␉␉{0x3A18, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JIB (ICH10) */␊ |
| 1337 | ␉␉{0x3A1A, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JD (ICH10D) */␊ |
| 1338 | ␉␉{0, 0, 0, 0, 0} /* end marker */␊ |
| 1339 | ␉};␊ |
| 1340 | ␊ |
| 1341 | ␉struct pci_dev *dev;␊ |
| 1342 | ␉uint16_t base;␊ |
| 1343 | ␉uint32_t tmp;␊ |
| 1344 | ␉int i, allowed;␊ |
| 1345 | ␊ |
| 1346 | ␉/* First, look for a known LPC bridge */␊ |
| 1347 | ␉for (dev = pacc->devices; dev; dev = dev->next) {␊ |
| 1348 | ␉␉uint16_t device_class;␊ |
| 1349 | ␉␉/* libpci before version 2.2.4 does not store class info. */␊ |
| 1350 | ␉␉device_class = pci_read_word(dev, PCI_CLASS_DEVICE);␊ |
| 1351 | ␉␉if ((dev->vendor_id == 0x8086) &&␊ |
| 1352 | ␉␉ (device_class == 0x0601)) { /* ISA bridge */␊ |
| 1353 | ␉␉␉/* Is this device in our list? */␊ |
| 1354 | ␉␉␉for (i = 0; intel_ich_gpio_table[i].id; i++)␊ |
| 1355 | ␉␉␉␉if (dev->device_id == intel_ich_gpio_table[i].id)␊ |
| 1356 | ␉␉␉␉␉break;␊ |
| 1357 | ␊ |
| 1358 | ␉␉␉if (intel_ich_gpio_table[i].id)␊ |
| 1359 | ␉␉␉␉break;␊ |
| 1360 | ␉␉}␊ |
| 1361 | ␉}␊ |
| 1362 | ␊ |
| 1363 | ␉if (!dev) {␊ |
| 1364 | ␉␉msg_perr("\nERROR: No known Intel LPC bridge found.\n");␊ |
| 1365 | ␉␉return -1;␊ |
| 1366 | ␉}␊ |
| 1367 | ␊ |
| 1368 | ␉/*␊ |
| 1369 | ␉ * According to the datasheets, all Intel ICHs have the GPIO bar 5:1␊ |
| 1370 | ␉ * strapped to zero. From some mobile ICH9 version on, this becomes␊ |
| 1371 | ␉ * 6:1. The mask below catches all.␊ |
| 1372 | ␉ */␊ |
| 1373 | ␉base = pci_read_word(dev, intel_ich_gpio_table[i].base_reg) & 0xFFC0;␊ |
| 1374 | ␊ |
| 1375 | ␉/* Check whether the line is allowed. */␊ |
| 1376 | ␉if (gpio < 32)␊ |
| 1377 | ␉␉allowed = (intel_ich_gpio_table[i].bank0 >> gpio) & 0x01;␊ |
| 1378 | ␉else if (gpio < 64)␊ |
| 1379 | ␉␉allowed = (intel_ich_gpio_table[i].bank1 >> (gpio - 32)) & 0x01;␊ |
| 1380 | ␉else␊ |
| 1381 | ␉␉allowed = (intel_ich_gpio_table[i].bank2 >> (gpio - 64)) & 0x01;␊ |
| 1382 | ␊ |
| 1383 | ␉if (!allowed) {␊ |
| 1384 | ␉␉msg_perr("\nERROR: This Intel LPC bridge does not allow"␊ |
| 1385 | ␉␉␉ " setting GPIO%02d\n", gpio);␊ |
| 1386 | ␉␉return -1;␊ |
| 1387 | ␉}␊ |
| 1388 | ␊ |
| 1389 | ␉msg_pdbg("\nIntel ICH LPC bridge: %sing GPIO%02d.\n",␊ |
| 1390 | ␉␉ raise ? "Rais" : "Dropp", gpio);␊ |
| 1391 | ␊ |
| 1392 | ␉if (gpio < 32) {␊ |
| 1393 | ␉␉/* Set line to GPIO. */␊ |
| 1394 | ␉␉tmp = INL(base);␊ |
| 1395 | ␉␉/* ICH/ICH0 multiplexes 27/28 on the line set. */␊ |
| 1396 | ␉␉if ((gpio == 28) &&␊ |
| 1397 | ␉␉ ((dev->device_id == 0x2410) || (dev->device_id == 0x2420)))␊ |
| 1398 | ␉␉␉tmp |= 1 << 27;␊ |
| 1399 | ␉␉else␊ |
| 1400 | ␉␉␉tmp |= 1 << gpio;␊ |
| 1401 | ␉␉OUTL(tmp, base);␊ |
| 1402 | ␊ |
| 1403 | ␉␉/* As soon as we are talking to ICH8 and above, this register␊ |
| 1404 | ␉␉ decides whether we can set the gpio or not. */␊ |
| 1405 | ␉␉if (dev->device_id > 0x2800) {␊ |
| 1406 | ␉␉␉tmp = INL(base);␊ |
| 1407 | ␉␉␉if (!(tmp & (1 << gpio))) {␊ |
| 1408 | ␉␉␉␉msg_perr("\nERROR: This Intel LPC bridge"␊ |
| 1409 | ␉␉␉␉␉" does not allow setting GPIO%02d\n",␊ |
| 1410 | ␉␉␉␉␉gpio);␊ |
| 1411 | ␉␉␉␉return -1;␊ |
| 1412 | ␉␉␉}␊ |
| 1413 | ␉␉}␊ |
| 1414 | ␊ |
| 1415 | ␉␉/* Set GPIO to OUTPUT. */␊ |
| 1416 | ␉␉tmp = INL(base + 0x04);␊ |
| 1417 | ␉␉tmp &= ~(1 << gpio);␊ |
| 1418 | ␉␉OUTL(tmp, base + 0x04);␊ |
| 1419 | ␊ |
| 1420 | ␉␉/* Raise GPIO line. */␊ |
| 1421 | ␉␉tmp = INL(base + 0x0C);␊ |
| 1422 | ␉␉if (raise)␊ |
| 1423 | ␉␉␉tmp |= 1 << gpio;␊ |
| 1424 | ␉␉else␊ |
| 1425 | ␉␉␉tmp &= ~(1 << gpio);␊ |
| 1426 | ␉␉OUTL(tmp, base + 0x0C);␊ |
| 1427 | ␉} else if (gpio < 64) {␊ |
| 1428 | ␉␉gpio -= 32;␊ |
| 1429 | ␊ |
| 1430 | ␉␉/* Set line to GPIO. */␊ |
| 1431 | ␉␉tmp = INL(base + 0x30);␊ |
| 1432 | ␉␉tmp |= 1 << gpio;␊ |
| 1433 | ␉␉OUTL(tmp, base + 0x30);␊ |
| 1434 | ␊ |
| 1435 | ␉␉/* As soon as we are talking to ICH8 and above, this register␊ |
| 1436 | ␉␉ decides whether we can set the gpio or not. */␊ |
| 1437 | ␉␉if (dev->device_id > 0x2800) {␊ |
| 1438 | ␉␉␉tmp = INL(base + 30);␊ |
| 1439 | ␉␉␉if (!(tmp & (1 << gpio))) {␊ |
| 1440 | ␉␉␉␉msg_perr("\nERROR: This Intel LPC bridge"␊ |
| 1441 | ␉␉␉␉␉" does not allow setting GPIO%02d\n",␊ |
| 1442 | ␉␉␉␉␉gpio + 32);␊ |
| 1443 | ␉␉␉␉return -1;␊ |
| 1444 | ␉␉␉}␊ |
| 1445 | ␉␉}␊ |
| 1446 | ␊ |
| 1447 | ␉␉/* Set GPIO to OUTPUT. */␊ |
| 1448 | ␉␉tmp = INL(base + 0x34);␊ |
| 1449 | ␉␉tmp &= ~(1 << gpio);␊ |
| 1450 | ␉␉OUTL(tmp, base + 0x34);␊ |
| 1451 | ␊ |
| 1452 | ␉␉/* Raise GPIO line. */␊ |
| 1453 | ␉␉tmp = INL(base + 0x38);␊ |
| 1454 | ␉␉if (raise)␊ |
| 1455 | ␉␉␉tmp |= 1 << gpio;␊ |
| 1456 | ␉␉else␊ |
| 1457 | ␉␉␉tmp &= ~(1 << gpio);␊ |
| 1458 | ␉␉OUTL(tmp, base + 0x38);␊ |
| 1459 | ␉} else {␊ |
| 1460 | ␉␉gpio -= 64;␊ |
| 1461 | ␊ |
| 1462 | ␉␉/* Set line to GPIO. */␊ |
| 1463 | ␉␉tmp = INL(base + 0x40);␊ |
| 1464 | ␉␉tmp |= 1 << gpio;␊ |
| 1465 | ␉␉OUTL(tmp, base + 0x40);␊ |
| 1466 | ␊ |
| 1467 | ␉␉tmp = INL(base + 40);␊ |
| 1468 | ␉␉if (!(tmp & (1 << gpio))) {␊ |
| 1469 | ␉␉␉msg_perr("\nERROR: This Intel LPC bridge does "␊ |
| 1470 | ␉␉␉␉"not allow setting GPIO%02d\n", gpio + 64);␊ |
| 1471 | ␉␉␉return -1;␊ |
| 1472 | ␉␉}␊ |
| 1473 | ␊ |
| 1474 | ␉␉/* Set GPIO to OUTPUT. */␊ |
| 1475 | ␉␉tmp = INL(base + 0x44);␊ |
| 1476 | ␉␉tmp &= ~(1 << gpio);␊ |
| 1477 | ␉␉OUTL(tmp, base + 0x44);␊ |
| 1478 | ␊ |
| 1479 | ␉␉/* Raise GPIO line. */␊ |
| 1480 | ␉␉tmp = INL(base + 0x48);␊ |
| 1481 | ␉␉if (raise)␊ |
| 1482 | ␉␉␉tmp |= 1 << gpio;␊ |
| 1483 | ␉␉else␊ |
| 1484 | ␉␉␉tmp &= ~(1 << gpio);␊ |
| 1485 | ␉␉OUTL(tmp, base + 0x48);␊ |
| 1486 | ␉}␊ |
| 1487 | ␊ |
| 1488 | ␉return 0;␊ |
| 1489 | }␊ |
| 1490 | ␊ |
| 1491 | /*␊ |
| 1492 | * Suited for:␊ |
| 1493 | * - abit IP35: Intel P35 + ICH9R␊ |
| 1494 | * - abit IP35 Pro: Intel P35 + ICH9R␊ |
| 1495 | * - ASUS P5LD2␊ |
| 1496 | */␊ |
| 1497 | static int intel_ich_gpio16_raise(void)␊ |
| 1498 | {␊ |
| 1499 | ␉return intel_ich_gpio_set(16, 1);␊ |
| 1500 | }␊ |
| 1501 | ␊ |
| 1502 | /*␊ |
| 1503 | * Suited for:␊ |
| 1504 | * - HP Puffer2-UL8E (ASUS PTGD-LA OEM): LGA775 + 915 + ICH6␊ |
| 1505 | */␊ |
| 1506 | static int intel_ich_gpio18_raise(void)␊ |
| 1507 | {␊ |
| 1508 | ␉return intel_ich_gpio_set(18, 1);␊ |
| 1509 | }␊ |
| 1510 | ␊ |
| 1511 | /*␊ |
| 1512 | * Suited for:␊ |
| 1513 | * - MSI MS-7046: LGA775 + 915P + ICH6␊ |
| 1514 | */␊ |
| 1515 | static int intel_ich_gpio19_raise(void)␊ |
| 1516 | {␊ |
| 1517 | ␉return intel_ich_gpio_set(19, 1);␊ |
| 1518 | }␊ |
| 1519 | ␊ |
| 1520 | /*␊ |
| 1521 | * Suited for:␊ |
| 1522 | * - ASUS P4B266LM (Sony Vaio PCV-RX650): socket478 + 845D + ICH2␊ |
| 1523 | * - ASUS P4C800-E Deluxe: socket478 + 875P + ICH5␊ |
| 1524 | * - ASUS P4P800: Intel socket478 + 865PE + ICH5R␊ |
| 1525 | * - ASUS P4P800-E Deluxe: Intel socket478 + 865PE + ICH5R␊ |
| 1526 | * - ASUS P4P800-VM: Intel socket478 + 865PE + ICH5R␊ |
| 1527 | * - ASUS P5GD1 Pro: Intel LGA 775 + 915P + ICH6R␊ |
| 1528 | * - ASUS P5GD2 Premium: Intel LGA775 + 915G + ICH6R␊ |
| 1529 | * - ASUS P5GDC Deluxe: Intel socket775 + 915P + ICH6R␊ |
| 1530 | * - ASUS P5PE-VM: Intel LGA775 + 865G + ICH5␊ |
| 1531 | * - Samsung Polaris 32: socket478 + 865P + ICH5␊ |
| 1532 | */␊ |
| 1533 | static int intel_ich_gpio21_raise(void)␊ |
| 1534 | {␊ |
| 1535 | ␉return intel_ich_gpio_set(21, 1);␊ |
| 1536 | }␊ |
| 1537 | ␊ |
| 1538 | /*␊ |
| 1539 | * Suited for:␊ |
| 1540 | * - ASUS P4B266: socket478 + Intel 845D + ICH2␊ |
| 1541 | * - ASUS P4B533-E: socket478 + 845E + ICH4␊ |
| 1542 | * - ASUS P4B-MX variant in HP Vectra VL420 SFF: socket478 + 845D + ICH2␊ |
| 1543 | */␊ |
| 1544 | static int intel_ich_gpio22_raise(void)␊ |
| 1545 | {␊ |
| 1546 | ␉return intel_ich_gpio_set(22, 1);␊ |
| 1547 | }␊ |
| 1548 | ␊ |
| 1549 | /*␊ |
| 1550 | * Suited for:␊ |
| 1551 | * - ASUS A8Jm (laptop): Intel 945 + ICH7␊ |
| 1552 | * - ASUS P5LP-LE used in ...␊ |
| 1553 | * - HP Media Center m7270.fr Desktop PC as "Lithium-UL8E"␊ |
| 1554 | * - Epson Endeavor MT7700␊ |
| 1555 | */␊ |
| 1556 | static int intel_ich_gpio34_raise(void)␊ |
| 1557 | {␊ |
| 1558 | ␉return intel_ich_gpio_set(34, 1);␊ |
| 1559 | }␊ |
| 1560 | ␊ |
| 1561 | /*␊ |
| 1562 | * Suited for:␊ |
| 1563 | * - AOpen i945GMx-VFX: Intel 945GM + ICH7-M used in ...␊ |
| 1564 | * - FCS ESPRIMO Q5010 (SMBIOS: D2544-B1)␊ |
| 1565 | */␊ |
| 1566 | static int intel_ich_gpio38_raise(void)␊ |
| 1567 | {␊ |
| 1568 | ␉return intel_ich_gpio_set(38, 1);␊ |
| 1569 | }␊ |
| 1570 | ␊ |
| 1571 | /*␊ |
| 1572 | * Suited for:␊ |
| 1573 | * - ASUS M6Ne (laptop): socket 479M (guessed) + Intel 855PM + ICH4-M␊ |
| 1574 | */␊ |
| 1575 | static int intel_ich_gpio43_raise(void)␊ |
| 1576 | {␊ |
| 1577 | ␉return intel_ich_gpio_set(43, 1);␊ |
| 1578 | }␊ |
| 1579 | ␊ |
| 1580 | /*␊ |
| 1581 | * Suited for:␊ |
| 1582 | * - HP Vectra VL400: 815 + ICH + PC87360␊ |
| 1583 | */␊ |
| 1584 | static int board_hp_vl400(void)␊ |
| 1585 | {␊ |
| 1586 | ␉int ret;␊ |
| 1587 | ␉ret = intel_ich_gpio_set(25, 1);␉/* Master write enable ? */␊ |
| 1588 | ␉if (!ret)␊ |
| 1589 | ␉␉ret = pc8736x_gpio_set(PC87360_ID, 0x09, 1);␉/* #WP ? */␊ |
| 1590 | ␉if (!ret)␊ |
| 1591 | ␉␉ret = pc8736x_gpio_set(PC87360_ID, 0x27, 1);␉/* #TBL */␊ |
| 1592 | ␉return ret;␊ |
| 1593 | }␊ |
| 1594 | ␊ |
| 1595 | /*␊ |
| 1596 | * Suited for:␊ |
| 1597 | * - HP e-Vectra P2706T: 810E + ICH + PC87364␊ |
| 1598 | */␊ |
| 1599 | static int board_hp_p2706t(void)␊ |
| 1600 | {␊ |
| 1601 | ␉int ret;␊ |
| 1602 | ␉ret = pc8736x_gpio_set(PC87364_ID, 0x25, 1);␊ |
| 1603 | ␉if (!ret)␊ |
| 1604 | ␉␉ret = pc8736x_gpio_set(PC87364_ID, 0x26, 1);␊ |
| 1605 | ␉return ret;␊ |
| 1606 | }␊ |
| 1607 | ␊ |
| 1608 | /*␊ |
| 1609 | * Suited for:␊ |
| 1610 | * - Dell PowerEdge 1850: Intel PPGA604 + E7520 + ICH5R␊ |
| 1611 | * - ASRock P4i65GV: Intel Socket478 + 865GV + ICH5R␊ |
| 1612 | * - ASRock 775i65G: Intel LGA 775 + 865G + ICH5␊ |
| 1613 | * - MSI MS-6391 (845 Pro4): Intel Socket478 + 845 + ICH2␊ |
| 1614 | */␊ |
| 1615 | static int intel_ich_gpio23_raise(void)␊ |
| 1616 | {␊ |
| 1617 | ␉return intel_ich_gpio_set(23, 1);␊ |
| 1618 | }␊ |
| 1619 | ␊ |
| 1620 | /*␊ |
| 1621 | * Suited for:␊ |
| 1622 | * - GIGABYTE GA-6IEM: Intel Socket370 + i815 + ICH2␊ |
| 1623 | * - GIGABYTE GA-8IRML: Intel Socket478 + i845 + ICH2␊ |
| 1624 | */␊ |
| 1625 | static int intel_ich_gpio25_raise(void)␊ |
| 1626 | {␊ |
| 1627 | ␉return intel_ich_gpio_set(25, 1);␊ |
| 1628 | }␊ |
| 1629 | ␊ |
| 1630 | /*␊ |
| 1631 | * Suited for:␊ |
| 1632 | * - IBASE MB899: i945GM + ICH7␊ |
| 1633 | */␊ |
| 1634 | static int intel_ich_gpio26_raise(void)␊ |
| 1635 | {␊ |
| 1636 | ␉return intel_ich_gpio_set(26, 1);␊ |
| 1637 | }␊ |
| 1638 | ␊ |
| 1639 | /*␊ |
| 1640 | * Suited for:␊ |
| 1641 | * - P4SD-LA (HP OEM): i865 + ICH5␊ |
| 1642 | * - GIGABYTE GA-8IP775: 865P + ICH5␊ |
| 1643 | * - GIGABYTE GA-8PE667 Ultra 2: socket 478 + i845PE + ICH4␊ |
| 1644 | * - MSI MS-6788-40 (aka 848P Neo-V)␊ |
| 1645 | */␊ |
| 1646 | static int intel_ich_gpio32_raise(void)␊ |
| 1647 | {␊ |
| 1648 | ␉return intel_ich_gpio_set(32, 1);␊ |
| 1649 | }␊ |
| 1650 | ␊ |
| 1651 | /*␊ |
| 1652 | * Suited for:␊ |
| 1653 | * - AOpen i975Xa-YDG: i975X + ICH7 + W83627EHF␊ |
| 1654 | */␊ |
| 1655 | static int board_aopen_i975xa_ydg(void)␊ |
| 1656 | {␊ |
| 1657 | ␉int ret;␊ |
| 1658 | ␊ |
| 1659 | ␉/* Vendor BIOS ends up in LDN6... maybe the board enable is wrong,␊ |
| 1660 | ␉ * or perhaps it's not needed at all?␊ |
| 1661 | ␉ * The regs it tries to touch are 0xF0, 0xF1, 0xF2 which means if it␊ |
| 1662 | ␉ * were in the right LDN, it would have to be GPIO1 or GPIO3.␊ |
| 1663 | ␉ */␊ |
| 1664 | /*␊ |
| 1665 | ␉ret = winbond_gpio_set(0x2e, WINBOND_W83627EHF_ID, x, 0)␊ |
| 1666 | ␉if (!ret)␊ |
| 1667 | */␊ |
| 1668 | ␉␉ret = intel_ich_gpio_set(33, 1);␊ |
| 1669 | ␊ |
| 1670 | ␉return ret;␊ |
| 1671 | }␊ |
| 1672 | ␊ |
| 1673 | /*␊ |
| 1674 | * Suited for:␊ |
| 1675 | * - Acorp 6A815EPD: socket 370 + intel 815 + ICH2␊ |
| 1676 | */␊ |
| 1677 | static int board_acorp_6a815epd(void)␊ |
| 1678 | {␊ |
| 1679 | ␉int ret;␊ |
| 1680 | ␊ |
| 1681 | ␉/* Lower Blocks Lock -- pin 7 of PLCC32 */␊ |
| 1682 | ␉ret = intel_ich_gpio_set(22, 1);␊ |
| 1683 | ␉if (!ret) /* Top Block Lock -- pin 8 of PLCC32 */␊ |
| 1684 | ␉␉ret = intel_ich_gpio_set(23, 1);␊ |
| 1685 | ␊ |
| 1686 | ␉return ret;␊ |
| 1687 | }␊ |
| 1688 | ␊ |
| 1689 | /*␊ |
| 1690 | * Suited for:␊ |
| 1691 | * - Kontron 986LCD-M: Socket478 + 915GM + ICH7R␊ |
| 1692 | */␊ |
| 1693 | static int board_kontron_986lcd_m(void)␊ |
| 1694 | {␊ |
| 1695 | ␉int ret;␊ |
| 1696 | ␊ |
| 1697 | ␉ret = intel_ich_gpio_set(34, 1); /* #TBL */␊ |
| 1698 | ␉if (!ret)␊ |
| 1699 | ␉␉ret = intel_ich_gpio_set(35, 1); /* #WP */␊ |
| 1700 | ␊ |
| 1701 | ␉return ret;␊ |
| 1702 | }␊ |
| 1703 | ␊ |
| 1704 | /*␊ |
| 1705 | * Suited for:␊ |
| 1706 | * - Soyo SY-7VCA: Pro133A + VT82C686␊ |
| 1707 | */␊ |
| 1708 | static int via_apollo_gpo_set(int gpio, int raise)␊ |
| 1709 | {␊ |
| 1710 | ␉struct pci_dev *dev;␊ |
| 1711 | ␉uint32_t base, tmp;␊ |
| 1712 | ␊ |
| 1713 | ␉/* VT82C686 power management */␊ |
| 1714 | ␉dev = pci_dev_find(0x1106, 0x3057);␊ |
| 1715 | ␉if (!dev) {␊ |
| 1716 | ␉␉msg_perr("\nERROR: VT82C686 PM device not found.\n");␊ |
| 1717 | ␉␉return -1;␊ |
| 1718 | ␉}␊ |
| 1719 | ␊ |
| 1720 | ␉msg_pdbg("\nVIA Apollo ACPI: %sing GPIO%02d.\n",␊ |
| 1721 | ␉␉ raise ? "Rais" : "Dropp", gpio);␊ |
| 1722 | ␊ |
| 1723 | ␉/* Select GPO function on multiplexed pins. */␊ |
| 1724 | ␉tmp = pci_read_byte(dev, 0x54);␊ |
| 1725 | ␉switch (gpio) {␊ |
| 1726 | ␉case 0:␊ |
| 1727 | ␉␉tmp &= ~0x03;␊ |
| 1728 | ␉␉break;␊ |
| 1729 | ␉case 1:␊ |
| 1730 | ␉␉tmp |= 0x04;␊ |
| 1731 | ␉␉break;␊ |
| 1732 | ␉case 2:␊ |
| 1733 | ␉␉tmp |= 0x08;␊ |
| 1734 | ␉␉break;␊ |
| 1735 | ␉case 3:␊ |
| 1736 | ␉␉tmp |= 0x10;␊ |
| 1737 | ␉␉break;␊ |
| 1738 | ␉}␊ |
| 1739 | ␉pci_write_byte(dev, 0x54, tmp);␊ |
| 1740 | ␊ |
| 1741 | ␉/* PM IO base */␊ |
| 1742 | ␉base = pci_read_long(dev, 0x48) & 0x0000FF00;␊ |
| 1743 | ␊ |
| 1744 | ␉/* Drop GPO0 */␊ |
| 1745 | ␉tmp = INL(base + 0x4C);␊ |
| 1746 | ␉if (raise)␊ |
| 1747 | ␉␉tmp |= 1U << gpio;␊ |
| 1748 | ␉else␊ |
| 1749 | ␉␉tmp &= ~(1U << gpio);␊ |
| 1750 | ␉OUTL(tmp, base + 0x4C);␊ |
| 1751 | ␊ |
| 1752 | ␉return 0;␊ |
| 1753 | }␊ |
| 1754 | ␊ |
| 1755 | /*␊ |
| 1756 | * Suited for:␊ |
| 1757 | * - abit VT6X4: Pro133x + VT82C686A␊ |
| 1758 | * - abit VA6: Pro133x + VT82C686A␊ |
| 1759 | */␊ |
| 1760 | static int via_apollo_gpo4_lower(void)␊ |
| 1761 | {␊ |
| 1762 | ␉return via_apollo_gpo_set(4, 0);␊ |
| 1763 | }␊ |
| 1764 | ␊ |
| 1765 | /*␊ |
| 1766 | * Suited for:␊ |
| 1767 | * - Soyo SY-7VCA: Pro133A + VT82C686␊ |
| 1768 | */␊ |
| 1769 | static int via_apollo_gpo0_lower(void)␊ |
| 1770 | {␊ |
| 1771 | ␉return via_apollo_gpo_set(0, 0);␊ |
| 1772 | }␊ |
| 1773 | ␊ |
| 1774 | /*␊ |
| 1775 | * Enable some GPIO pin on SiS southbridge and enables SIO flash writes.␊ |
| 1776 | *␊ |
| 1777 | * Suited for:␊ |
| 1778 | * - MSI 651M-L: SiS651 / SiS962␊ |
| 1779 | * - GIGABYTE GA-8SIMLH␊ |
| 1780 | */␊ |
| 1781 | static int sis_gpio0_raise_and_w836xx_memw(void)␊ |
| 1782 | {␊ |
| 1783 | ␉struct pci_dev *dev;␊ |
| 1784 | ␉uint16_t base, temp;␊ |
| 1785 | ␊ |
| 1786 | ␉dev = pci_dev_find(0x1039, 0x0962);␊ |
| 1787 | ␉if (!dev) {␊ |
| 1788 | ␉␉msg_perr("Expected south bridge not found\n");␊ |
| 1789 | ␉␉return 1;␊ |
| 1790 | ␉}␊ |
| 1791 | ␊ |
| 1792 | ␉base = pci_read_word(dev, 0x74);␊ |
| 1793 | ␉temp = INW(base + 0x68);␊ |
| 1794 | ␉temp &= ~(1 << 0);␉␉/* Make pin output? */␊ |
| 1795 | ␉OUTW(temp, base + 0x68);␊ |
| 1796 | ␊ |
| 1797 | ␉temp = INW(base + 0x64);␊ |
| 1798 | ␉temp |= (1 << 0);␉␉/* Raise output? */␊ |
| 1799 | ␉OUTW(temp, base + 0x64);␊ |
| 1800 | ␊ |
| 1801 | ␉w836xx_memw_enable(0x2E);␊ |
| 1802 | ␊ |
| 1803 | ␉return 0;␊ |
| 1804 | }␊ |
| 1805 | ␊ |
| 1806 | /*␊ |
| 1807 | * Find the runtime registers of an SMSC Super I/O, after verifying its␊ |
| 1808 | * chip ID.␊ |
| 1809 | *␊ |
| 1810 | * Returns the base port of the runtime register block, or 0 on error.␊ |
| 1811 | */␊ |
| 1812 | static uint16_t smsc_find_runtime(uint16_t sio_port, uint16_t chip_id,␊ |
| 1813 | uint8_t logical_device)␊ |
| 1814 | {␊ |
| 1815 | ␉uint16_t rt_port = 0;␊ |
| 1816 | ␊ |
| 1817 | ␉/* Verify the chip ID. */␊ |
| 1818 | ␉OUTB(0x55, sio_port); /* Enable configuration. */␊ |
| 1819 | ␉if (sio_read(sio_port, 0x20) != chip_id) {␊ |
| 1820 | ␉␉msg_perr("\nERROR: SMSC Super I/O not found.\n");␊ |
| 1821 | ␉␉goto out;␊ |
| 1822 | ␉}␊ |
| 1823 | ␊ |
| 1824 | ␉/* If the runtime block is active, get its address. */␊ |
| 1825 | ␉sio_write(sio_port, 0x07, logical_device);␊ |
| 1826 | ␉if (sio_read(sio_port, 0x30) & 1) {␊ |
| 1827 | ␉␉rt_port = (sio_read(sio_port, 0x60) << 8)␊ |
| 1828 | ␉␉ | sio_read(sio_port, 0x61);␊ |
| 1829 | ␉}␊ |
| 1830 | ␊ |
| 1831 | ␉if (rt_port == 0) {␊ |
| 1832 | ␉␉msg_perr("\nERROR: "␊ |
| 1833 | ␉␉␉"Super I/O runtime interface not available.\n");␊ |
| 1834 | ␉}␊ |
| 1835 | out:␊ |
| 1836 | ␉OUTB(0xaa, sio_port); /* Disable configuration. */␊ |
| 1837 | ␉return rt_port;␊ |
| 1838 | }␊ |
| 1839 | ␊ |
| 1840 | /*␊ |
| 1841 | * Disable write protection on the Mitac 6513WU. WP# on the FWH is␊ |
| 1842 | * connected to GP30 on the Super I/O, and TBL# is always high.␊ |
| 1843 | */␊ |
| 1844 | static int board_mitac_6513wu(void)␊ |
| 1845 | {␊ |
| 1846 | ␉struct pci_dev *dev;␊ |
| 1847 | ␉uint16_t rt_port;␊ |
| 1848 | ␉uint8_t val;␊ |
| 1849 | ␊ |
| 1850 | ␉dev = pci_dev_find(0x8086, 0x2410);␉/* Intel 82801AA ISA bridge */␊ |
| 1851 | ␉if (!dev) {␊ |
| 1852 | ␉␉msg_perr("\nERROR: Intel 82801AA ISA bridge not found.\n");␊ |
| 1853 | ␉␉return -1;␊ |
| 1854 | ␉}␊ |
| 1855 | ␊ |
| 1856 | ␉rt_port = smsc_find_runtime(0x4e, 0x54 /* LPC47U33x */, 0xa);␊ |
| 1857 | ␉if (rt_port == 0)␊ |
| 1858 | ␉␉return -1;␊ |
| 1859 | ␊ |
| 1860 | ␉/* Configure the GPIO pin. */␊ |
| 1861 | ␉val = INB(rt_port + 0x33); /* GP30 config */␊ |
| 1862 | ␉val &= ~0x87; /* Output, non-inverted, GPIO, push/pull */␊ |
| 1863 | ␉OUTB(val, rt_port + 0x33);␊ |
| 1864 | ␊ |
| 1865 | ␉/* Disable write protection. */␊ |
| 1866 | ␉val = INB(rt_port + 0x4d); /* GP3 values */␊ |
| 1867 | ␉val |= 0x01; /* Set GP30 high. */␊ |
| 1868 | ␉OUTB(val, rt_port + 0x4d);␊ |
| 1869 | ␊ |
| 1870 | ␉return 0;␊ |
| 1871 | }␊ |
| 1872 | ␊ |
| 1873 | /*␊ |
| 1874 | * Suited for:␊ |
| 1875 | * - abit AV8: Socket939 + K8T800Pro + VT8237␊ |
| 1876 | */␊ |
| 1877 | static int board_abit_av8(void)␊ |
| 1878 | {␊ |
| 1879 | ␉uint8_t val;␊ |
| 1880 | ␊ |
| 1881 | ␉/* Raise GPO pins GP22 & GP23 */␊ |
| 1882 | ␉val = INB(0x404E);␊ |
| 1883 | ␉val |= 0xC0;␊ |
| 1884 | ␉OUTB(val, 0x404E);␊ |
| 1885 | ␊ |
| 1886 | ␉return 0;␊ |
| 1887 | }␊ |
| 1888 | ␊ |
| 1889 | /*␊ |
| 1890 | * Suited for:␊ |
| 1891 | * - ASUS A7V333: VIA KT333 + VT8233A + IT8703F␊ |
| 1892 | * - ASUS A7V8X: VIA KT400 + VT8235 + IT8703F␊ |
| 1893 | */␊ |
| 1894 | static int it8703f_gpio51_raise(void)␊ |
| 1895 | {␊ |
| 1896 | ␉uint16_t id, base;␊ |
| 1897 | ␉uint8_t tmp;␊ |
| 1898 | ␊ |
| 1899 | ␉/* Find the IT8703F. */␊ |
| 1900 | ␉w836xx_ext_enter(0x2E);␊ |
| 1901 | ␉id = (sio_read(0x2E, 0x20) << 8) | sio_read(0x2E, 0x21);␊ |
| 1902 | ␉w836xx_ext_leave(0x2E);␊ |
| 1903 | ␊ |
| 1904 | ␉if (id != 0x8701) {␊ |
| 1905 | ␉␉msg_perr("\nERROR: IT8703F Super I/O not found.\n");␊ |
| 1906 | ␉␉return -1;␊ |
| 1907 | ␉}␊ |
| 1908 | ␊ |
| 1909 | ␉/* Get the GP567 I/O base. */␊ |
| 1910 | ␉w836xx_ext_enter(0x2E);␊ |
| 1911 | ␉sio_write(0x2E, 0x07, 0x0C);␊ |
| 1912 | ␉base = (sio_read(0x2E, 0x60) << 8) | sio_read(0x2E, 0x61);␊ |
| 1913 | ␉w836xx_ext_leave(0x2E);␊ |
| 1914 | ␊ |
| 1915 | ␉if (!base) {␊ |
| 1916 | ␉␉msg_perr("\nERROR: Failed to read IT8703F Super I/O GPIO"␊ |
| 1917 | ␉␉␉" Base.\n");␊ |
| 1918 | ␉␉return -1;␊ |
| 1919 | ␉}␊ |
| 1920 | ␊ |
| 1921 | ␉/* Raise GP51. */␊ |
| 1922 | ␉tmp = INB(base);␊ |
| 1923 | ␉tmp |= 0x02;␊ |
| 1924 | ␉OUTB(tmp, base);␊ |
| 1925 | ␊ |
| 1926 | ␉return 0;␊ |
| 1927 | }␊ |
| 1928 | ␊ |
| 1929 | /*␊ |
| 1930 | * General routine for raising/dropping GPIO lines on the ITE IT87xx.␊ |
| 1931 | */␊ |
| 1932 | static int it87_gpio_set(unsigned int gpio, int raise)␊ |
| 1933 | {␊ |
| 1934 | ␉int allowed, sio;␊ |
| 1935 | ␉unsigned int port;␊ |
| 1936 | ␉uint16_t base, sioport;␊ |
| 1937 | ␉uint8_t tmp;␊ |
| 1938 | ␊ |
| 1939 | ␉/* IT87 GPIO configuration table */␊ |
| 1940 | ␉static const struct it87cfg {␊ |
| 1941 | ␉␉uint16_t id;␊ |
| 1942 | ␉␉uint8_t base_reg;␊ |
| 1943 | ␉␉uint32_t bank0;␊ |
| 1944 | ␉␉uint32_t bank1;␊ |
| 1945 | ␉␉uint32_t bank2;␊ |
| 1946 | ␉} it87_gpio_table[] = {␊ |
| 1947 | ␉␉{0x8712, 0x62, 0xCFF3FC00, 0x00FCFF3F, 0},␊ |
| 1948 | ␉␉{0x8718, 0x62, 0xCFF37C00, 0xF3FCDF3F, 0x0000000F},␊ |
| 1949 | ␉␉{0, 0, 0, 0, 0} /* end marker */␊ |
| 1950 | ␉};␊ |
| 1951 | ␉const struct it87cfg *cfg = NULL;␊ |
| 1952 | ␊ |
| 1953 | ␉/* Find the Super I/O in the probed list */␊ |
| 1954 | ␉for (sio = 0; sio < superio_count; sio++) {␊ |
| 1955 | ␉␉int i;␊ |
| 1956 | ␉␉if (superios[sio].vendor != SUPERIO_VENDOR_ITE)␊ |
| 1957 | ␉␉␉continue;␊ |
| 1958 | ␊ |
| 1959 | ␉␉/* Is this device in our list? */␊ |
| 1960 | ␉␉for (i = 0; it87_gpio_table[i].id; i++)␊ |
| 1961 | ␉␉␉if (superios[sio].model == it87_gpio_table[i].id) {␊ |
| 1962 | ␉␉␉␉cfg = &it87_gpio_table[i];␊ |
| 1963 | ␉␉␉␉goto found;␊ |
| 1964 | ␉␉␉}␊ |
| 1965 | ␉}␊ |
| 1966 | ␊ |
| 1967 | ␉if (cfg == NULL) {␊ |
| 1968 | ␉␉msg_perr("\nERROR: No IT87 Super I/O GPIO configuration "␊ |
| 1969 | ␉␉␉ "found.\n");␊ |
| 1970 | ␉␉return -1;␊ |
| 1971 | ␉}␊ |
| 1972 | ␊ |
| 1973 | found:␊ |
| 1974 | ␉/* Check whether the gpio is allowed. */␊ |
| 1975 | ␉if (gpio < 32)␊ |
| 1976 | ␉␉allowed = (cfg->bank0 >> gpio) & 0x01;␊ |
| 1977 | ␉else if (gpio < 64)␊ |
| 1978 | ␉␉allowed = (cfg->bank1 >> (gpio - 32)) & 0x01;␊ |
| 1979 | ␉else if (gpio < 96)␊ |
| 1980 | ␉␉allowed = (cfg->bank2 >> (gpio - 64)) & 0x01;␊ |
| 1981 | ␉else␊ |
| 1982 | ␉␉allowed = 0;␊ |
| 1983 | ␊ |
| 1984 | ␉if (!allowed) {␊ |
| 1985 | ␉␉msg_perr("\nERROR: IT%02X does not allow setting GPIO%02u.\n",␊ |
| 1986 | ␉␉␉ cfg->id, gpio);␊ |
| 1987 | ␉␉return -1;␊ |
| 1988 | ␉}␊ |
| 1989 | ␊ |
| 1990 | ␉/* Read the Simple I/O Base Address Register */␊ |
| 1991 | ␉sioport = superios[sio].port;␊ |
| 1992 | ␉enter_conf_mode_ite(sioport);␊ |
| 1993 | ␉sio_write(sioport, 0x07, 0x07);␊ |
| 1994 | ␉base = (sio_read(sioport, cfg->base_reg) << 8) |␊ |
| 1995 | ␉␉sio_read(sioport, cfg->base_reg + 1);␊ |
| 1996 | ␉exit_conf_mode_ite(sioport);␊ |
| 1997 | ␊ |
| 1998 | ␉if (!base) {␊ |
| 1999 | ␉␉msg_perr("\nERROR: Failed to read IT87 Super I/O GPIO Base.\n");␊ |
| 2000 | ␉␉return -1;␊ |
| 2001 | ␉}␊ |
| 2002 | ␊ |
| 2003 | ␉msg_pdbg("Using IT87 GPIO base 0x%04x\n", base);␊ |
| 2004 | ␊ |
| 2005 | ␉port = gpio / 10 - 1;␊ |
| 2006 | ␉gpio %= 10;␊ |
| 2007 | ␊ |
| 2008 | ␉/* set GPIO. */␊ |
| 2009 | ␉tmp = INB(base + port);␊ |
| 2010 | ␉if (raise)␊ |
| 2011 | ␉␉tmp |= 1 << gpio;␊ |
| 2012 | ␉else␊ |
| 2013 | ␉␉tmp &= ~(1 << gpio);␊ |
| 2014 | ␉OUTB(tmp, base + port);␊ |
| 2015 | ␊ |
| 2016 | ␉return 0;␊ |
| 2017 | }␊ |
| 2018 | ␊ |
| 2019 | /*␊ |
| 2020 | * Suited for:␊ |
| 2021 | * - ASUS A7N8X-VM/400: NVIDIA nForce2 IGP2 + IT8712F␊ |
| 2022 | */␊ |
| 2023 | static int it8712f_gpio12_raise(void)␊ |
| 2024 | {␊ |
| 2025 | ␉return it87_gpio_set(12, 1);␊ |
| 2026 | }␊ |
| 2027 | ␊ |
| 2028 | /*␊ |
| 2029 | * Suited for:␊ |
| 2030 | * - ASUS A7V600-X: VIA KT600 + VT8237 + IT8712F␊ |
| 2031 | * - ASUS A7V8X-X: VIA KT400 + VT8235 + IT8712F␊ |
| 2032 | */␊ |
| 2033 | static int it8712f_gpio31_raise(void)␊ |
| 2034 | {␊ |
| 2035 | ␉return it87_gpio_set(32, 1);␊ |
| 2036 | }␊ |
| 2037 | ␊ |
| 2038 | /*␊ |
| 2039 | * Suited for:␊ |
| 2040 | * - ASUS P5N-D: NVIDIA MCP51 + IT8718F␊ |
| 2041 | * - ASUS P5N-E SLI: NVIDIA MCP51 + IT8718F␊ |
| 2042 | */␊ |
| 2043 | static int it8718f_gpio63_raise(void)␊ |
| 2044 | {␊ |
| 2045 | ␉return it87_gpio_set(63, 1);␊ |
| 2046 | }␊ |
| 2047 | ␊ |
| 2048 | /*␊ |
| 2049 | * Suited for all boards with ambiguous DMI chassis information, which should be␊ |
| 2050 | * whitelisted because they are known to work:␊ |
| 2051 | * - MSC Q7 Tunnel Creek Module (Q7-TCTC)␊ |
| 2052 | */␊ |
| 2053 | static int p2_not_a_laptop(void)␊ |
| 2054 | {␊ |
| 2055 | ␉/* label this board as not a laptop */␊ |
| 2056 | ␉is_laptop = 0;␊ |
| 2057 | ␉msg_pdbg("Laptop detection overridden by P2 board enable.\n");␊ |
| 2058 | ␉return 0;␊ |
| 2059 | }␊ |
| 2060 | ␊ |
| 2061 | #endif␊ |
| 2062 | ␊ |
| 2063 | /*␊ |
| 2064 | * Below is the list of boards which need a special "board enable" code in␊ |
| 2065 | * flashrom before their ROM chip can be accessed/written to.␊ |
| 2066 | *␊ |
| 2067 | * NOTE: Please add boards that _don't_ need such enables or don't work yet␊ |
| 2068 | * to the respective tables in print.c. Thanks!␊ |
| 2069 | *␊ |
| 2070 | * We use 2 sets of IDs here, you're free to choose which is which. This␊ |
| 2071 | * is to provide a very high degree of certainty when matching a board on␊ |
| 2072 | * the basis of subsystem/card IDs. As not every vendor handles␊ |
| 2073 | * subsystem/card IDs in a sane manner.␊ |
| 2074 | *␊ |
| 2075 | * Keep the second set NULLed if it should be ignored. Keep the subsystem IDs␊ |
| 2076 | * NULLed if they don't identify the board fully and if you can't use DMI.␊ |
| 2077 | * But please take care to provide an as complete set of pci ids as possible;␊ |
| 2078 | * autodetection is the preferred behaviour and we would like to make sure that␊ |
| 2079 | * matches are unique.␊ |
| 2080 | *␊ |
| 2081 | * If PCI IDs are not sufficient for board matching, the match can be further␊ |
| 2082 | * constrained by a string that has to be present in the DMI database for␊ |
| 2083 | * the baseboard or the system entry. The pattern is matched by case sensitive␊ |
| 2084 | * substring match, unless it is anchored to the beginning (with a ^ in front)␊ |
| 2085 | * or the end (with a $ at the end). Both anchors may be specified at the␊ |
| 2086 | * same time to match the full field.␊ |
| 2087 | *␊ |
| 2088 | * When a board is matched through DMI, the first and second main PCI IDs␊ |
| 2089 | * and the first subsystem PCI ID have to match as well. If you specify the␊ |
| 2090 | * first subsystem ID as 0x0:0x0, the DMI matching code expects that the␊ |
| 2091 | * subsystem ID of that device is indeed zero.␊ |
| 2092 | *␊ |
| 2093 | * The coreboot ids are used two fold. When running with a coreboot firmware,␊ |
| 2094 | * the ids uniquely matches the coreboot board identification string. When a␊ |
| 2095 | * legacy bios is installed and when autodetection is not possible, these ids␊ |
| 2096 | * can be used to identify the board through the -p internal:mainboard=␊ |
| 2097 | * programmer parameter.␊ |
| 2098 | *␊ |
| 2099 | * When a board is identified through its coreboot ids (in both cases), the␊ |
| 2100 | * main pci ids are still required to match, as a safeguard.␊ |
| 2101 | */␊ |
| 2102 | ␊ |
| 2103 | /* Please keep this list alphabetically ordered by vendor/board name. */␊ |
| 2104 | const struct board_match board_matches[] = {␊ |
| 2105 | ␊ |
| 2106 | ␉/* first pci-id set [4], second pci-id set [4], dmi identifier, coreboot id [2], phase, vendor name, board name max_rom_... OK? flash enable */␊ |
| 2107 | #if defined(__i386__) || defined(__x86_64__)␊ |
| 2108 | ␉{0x10DE, 0x0547, 0x147B, 0x1C2F, 0x10DE, 0x0548, 0x147B, 0x1C2F, NULL, NULL, NULL, P3, "abit", "AN-M2", 0, NT, nvidia_mcp_gpio2_raise},␊ |
| 2109 | ␉{0x1106, 0x0282, 0x147B, 0x1415, 0x1106, 0x3227, 0x147B, 0x1415, "^AV8 ", NULL, NULL, P3, "abit", "AV8", 0, OK, board_abit_av8},␊ |
| 2110 | ␉{0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^i440BX-W977 (BM6)$", NULL, NULL, P3, "abit", "BM6", 0, OK, intel_piix4_gpo26_lower},␊ |
| 2111 | ␉{0x8086, 0x24d3, 0x147b, 0x1014, 0x8086, 0x2578, 0x147b, 0x1014, NULL, NULL, NULL, P3, "abit", "IC7", 0, NT, intel_ich_gpio23_raise},␊ |
| 2112 | ␉{0x8086, 0x2930, 0x147b, 0x1084, 0x11ab, 0x4364, 0x147b, 0x1084, NULL, NULL, NULL, P3, "abit", "IP35", 0, OK, intel_ich_gpio16_raise},␊ |
| 2113 | ␉{0x8086, 0x2930, 0x147b, 0x1083, 0x10ec, 0x8167, 0x147b, 0x1083, NULL, NULL, NULL, P3, "abit", "IP35 Pro", 0, OK, intel_ich_gpio16_raise},␊ |
| 2114 | ␉{0x10de, 0x0050, 0x147b, 0x1c1a, 0, 0, 0, 0, NULL, NULL, NULL, P3, "abit", "KN8 Ultra", 0, NT, nvidia_mcp_gpio2_lower},␊ |
| 2115 | ␉{0x10de, 0x01e0, 0x147b, 0x1c00, 0x10de, 0x0060, 0x147B, 0x1c00, NULL, NULL, NULL, P3, "abit", "NF7-S", 0, OK, nvidia_mcp_gpio8_raise},␊ |
| 2116 | ␉{0x10de, 0x02f0, 0x147b, 0x1c26, 0x10de, 0x0240, 0x10de, 0x0222, NULL, NULL, NULL, P3, "abit", "NF-M2 nView", 0, OK, nvidia_mcp_gpio4_lower},␊ |
| 2117 | ␉{0x1106, 0x0691, 0, 0, 0x1106, 0x3057, 0, 0, "(VA6)$", NULL, NULL, P3, "abit", "VA6", 0, OK, via_apollo_gpo4_lower},␊ |
| 2118 | ␉{0x1106, 0x0691, 0, 0, 0x1106, 0x3057, 0, 0, NULL, "abit", "vt6x4", P3, "abit", "VT6X4", 0, OK, via_apollo_gpo4_lower},␊ |
| 2119 | ␉{0x105a, 0x0d30, 0x105a, 0x4d33, 0x8086, 0x1130, 0x8086, 0, NULL, NULL, NULL, P3, "Acorp", "6A815EPD", 0, OK, board_acorp_6a815epd},␊ |
| 2120 | ␉{0x1022, 0x746B, 0, 0, 0, 0, 0, 0, NULL, "AGAMI", "ARUMA", P3, "agami", "Aruma", 0, OK, w83627hf_gpio24_raise_2e},␊ |
| 2121 | ␉{0x1106, 0x3177, 0x17F2, 0x3177, 0x1106, 0x3148, 0x17F2, 0x3148, NULL, NULL, NULL, P3, "Albatron", "PM266A Pro", 0, OK, w836xx_memw_enable_2e},␊ |
| 2122 | ␉{0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe61", P3, "Artec Group", "DBE61", 0, OK, board_artecgroup_dbe6x},␊ |
| 2123 | ␉{0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe62", P3, "Artec Group", "DBE62", 0, OK, board_artecgroup_dbe6x},␊ |
| 2124 | ␉{0x8086, 0x27b9, 0xa0a0, 0x0632, 0x8086, 0x27da, 0xa0a0, 0x0632, NULL, NULL, NULL, P3, "AOpen", "i945GMx-VFX", 0, OK, intel_ich_gpio38_raise},␊ |
| 2125 | ␉{0x8086, 0x277c, 0xa0a0, 0x060b, 0x8086, 0x27da, 0xa0a0, 0x060b, NULL, NULL, NULL, P3, "AOpen", "i975Xa-YDG", 0, OK, board_aopen_i975xa_ydg},␊ |
| 2126 | ␉{0x8086, 0x27b8, 0x1849, 0x27b8, 0x8086, 0x27da, 0x1849, 0x27da, "^ConRoeXFire-eSATA2", NULL, NULL, P3, "ASRock", "ConRoeXFire-eSATA2", 0, OK, intel_ich_gpio16_raise},␊ |
| 2127 | ␉{0x1039, 0x0741, 0x1849, 0x0741, 0x1039, 0x5513, 0x1849, 0x5513, "^K7S41 $", NULL, NULL, P3, "ASRock", "K7S41", 0, OK, w836xx_memw_enable_2e},␊ |
| 2128 | ␉{0x1039, 0x0741, 0x1849, 0x0741, 0x1039, 0x5513, 0x1849, 0x5513, "^K7S41GX$", NULL, NULL, P3, "ASRock", "K7S41GX", 0, OK, w836xx_memw_enable_2e},␊ |
| 2129 | ␉{0x8086, 0x24D4, 0x1849, 0x24D0, 0x8086, 0x24D5, 0x1849, 0x9739, NULL, NULL, NULL, P3, "ASRock", "P4i65GV", 0, OK, intel_ich_gpio23_raise},␊ |
| 2130 | ␉{0x8086, 0x2570, 0x1849, 0x2570, 0x8086, 0x24d3, 0x1849, 0x24d0, NULL, NULL, NULL, P3, "ASRock", "775i65G", 0, OK, intel_ich_gpio23_raise},␊ |
| 2131 | ␉{0x10DE, 0x0060, 0x1043, 0x80AD, 0x10DE, 0x01E0, 0x1043, 0x80C0, NULL, NULL, NULL, P3, "ASUS", "A7N8X-VM/400", 0, OK, it8712f_gpio12_raise},␊ |
| 2132 | ␉{0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3065, 0x1043, 0x80ED, NULL, NULL, NULL, P3, "ASUS", "A7V600-X", 0, OK, it8712f_gpio31_raise},␊ |
| 2133 | ␉{0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118, NULL, NULL, NULL, P3, "ASUS", "A7V8X-MX SE", 0, OK, w836xx_memw_enable_2e},␊ |
| 2134 | ␉{0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x808C, NULL, NULL, NULL, P3, "ASUS", "A7V8X", 0, OK, it8703f_gpio51_raise},␊ |
| 2135 | ␉{0x1106, 0x3099, 0x1043, 0x807F, 0x1106, 0x3147, 0x1043, 0x808C, NULL, NULL, NULL, P3, "ASUS", "A7V333", 0, OK, it8703f_gpio51_raise},␊ |
| 2136 | ␉{0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x80A1, NULL, NULL, NULL, P3, "ASUS", "A7V8X-X", 0, OK, it8712f_gpio31_raise},␊ |
| 2137 | ␉{0x1002, 0x4372, 0x103c, 0x2a26, 0x1002, 0x4377, 0x103c, 0x2a26, NULL, NULL, NULL, P3, "ASUS", "A8AE-LE", 0, OK, amd_sbxxx_gpio9_raise},␊ |
| 2138 | ␉{0x8086, 0x27A0, 0x1043, 0x1287, 0x8086, 0x27DF, 0x1043, 0x1287, "^A8J", NULL, NULL, P3, "ASUS", "A8Jm", 0, NT, intel_ich_gpio34_raise},␊ |
| 2139 | ␉{0x10DE, 0x0260, 0x103C, 0x2A34, 0x10DE, 0x0264, 0x103C, 0x2A34, "NODUSM3", NULL, NULL, P3, "ASUS", "A8M2N-LA (NodusM3-GL8E)", 0, OK, nvidia_mcp_gpio0_raise},␊ |
| 2140 | ␉{0x10DE, 0x0260, 0x103c, 0x2a3e, 0x10DE, 0x0264, 0x103c, 0x2a3e, "NAGAMI2L", NULL, NULL, P3, "ASUS", "A8N-LA (Nagami-GL8E)", 0, OK, nvidia_mcp_gpio0_raise},␊ |
| 2141 | ␉{0x10DE, 0x005E, 0x1043, 0x815A, 0x10DE, 0x0054, 0x1043, 0x815A, "^A8N-SLI DELUXE", NULL, NULL, P3, "ASUS", "A8N-SLI Deluxe", 0, NT, board_shuttle_fn25},␊ |
| 2142 | ␉{0x10de, 0x0264, 0x1043, 0x81bc, 0x10de, 0x02f0, 0x1043, 0x81cd, NULL, NULL, NULL, P3, "ASUS", "A8N-VM CSM", 0, OK, w83627ehf_gpio22_raise_2e},␊ |
| 2143 | ␉{0x10DE, 0x0264, 0x1043, 0x81C0, 0x10DE, 0x0260, 0x1043, 0x81C0, NULL, NULL, NULL, P3, "ASUS", "M2NBP-VM CSM", 0, OK, nvidia_mcp_gpio0_raise},␊ |
| 2144 | ␉{0x1106, 0x1336, 0x1043, 0x80ed, 0x1106, 0x3288, 0x1043, 0x8249, NULL, NULL, NULL, P3, "ASUS", "M2V-MX", 0, OK, via_vt823x_gpio5_raise},␊ |
| 2145 | ␉{0x8086, 0x24cc, 0, 0, 0x8086, 0x24c3, 0x1043, 0x1869, "^M6Ne$", NULL, NULL, P3, "ASUS", "M6Ne", 0, NT, intel_ich_gpio43_raise},␊ |
| 2146 | ␉{0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^P2B-N$", NULL, NULL, P3, "ASUS", "P2B-N", 0, OK, intel_piix4_gpo18_lower},␊ |
| 2147 | ␉{0x8086, 0x1A30, 0x1043, 0x8025, 0x8086, 0x244B, 0x104D, 0x80F0, NULL, NULL, NULL, P3, "ASUS", "P4B266-LM", 0, OK, intel_ich_gpio21_raise},␊ |
| 2148 | ␉{0x8086, 0x1a30, 0x1043, 0x8070, 0x8086, 0x244b, 0x1043, 0x8028, NULL, NULL, NULL, P3, "ASUS", "P4B266", 0, OK, intel_ich_gpio22_raise},␊ |
| 2149 | ␉{0x8086, 0x1A30, 0x1043, 0x8088, 0x8086, 0x24C3, 0x1043, 0x8089, NULL, NULL, NULL, P3, "ASUS", "P4B533-E", 0, NT, intel_ich_gpio22_raise},␊ |
| 2150 | ␉{0x8086, 0x2560, 0x103C, 0x2A00, 0x8086, 0x24C3, 0x103C, 0x2A01, "^Guppy", NULL, NULL, P3, "ASUS", "P4GV-LA (Guppy)", 0, OK, intel_ich_gpio21_raise},␊ |
| 2151 | ␉{0x8086, 0x24D3, 0x1043, 0x80A6, 0x8086, 0x2578, 0x1043, 0x80F6, NULL, NULL, NULL, P3, "ASUS", "P4C800-E Deluxe", 0, OK, intel_ich_gpio21_raise},␊ |
| 2152 | ␉{0x8086, 0x2570, 0x1043, 0x80F2, 0x8086, 0x24D5, 0x1043, 0x80F3, NULL, NULL, NULL, P3, "ASUS", "P4P800", 0, NT, intel_ich_gpio21_raise},␊ |
| 2153 | ␉{0x8086, 0x2570, 0x1043, 0x80F2, 0x8086, 0x24D3, 0x1043, 0x80A6, "^P4P800-E$", NULL, NULL, P3, "ASUS", "P4P800-E Deluxe", 0, OK, intel_ich_gpio21_raise},␊ |
| 2154 | ␉{0x8086, 0x2570, 0x1043, 0x80A5, 0x8086, 0x24d0, 0, 0, NULL, NULL, NULL, P3, "ASUS", "P4P800-VM", 0, OK, intel_ich_gpio21_raise},␊ |
| 2155 | ␉{0x1039, 0x0651, 0x1043, 0x8081, 0x1039, 0x0962, 0, 0, NULL, NULL, NULL, P3, "ASUS", "P4SC-E", 0, OK, it8707f_write_enable_2e},␊ |
| 2156 | ␉{0x8086, 0x2570, 0x1043, 0x80A5, 0x105A, 0x24D3, 0x1043, 0x80A6, NULL, NULL, NULL, P3, "ASUS", "P4SD-LA", 0, NT, intel_ich_gpio32_raise},␊ |
| 2157 | ␉{0x1039, 0x0661, 0x1043, 0x8113, 0x1039, 0x5513, 0x1043, 0x8087, NULL, NULL, NULL, P3, "ASUS", "P4S800-MX", 512, OK, w836xx_memw_enable_2e},␊ |
| 2158 | ␉{0x10B9, 0x1541, 0, 0, 0x10B9, 0x1533, 0, 0, "^P5A$", "asus", "p5a", P3, "ASUS", "P5A", 0, OK, board_asus_p5a},␊ |
| 2159 | ␉{0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x814e, "^P5GD1 PRO$", NULL, NULL, P3, "ASUS", "P5GD1 Pro", 0, OK, intel_ich_gpio21_raise},␊ |
| 2160 | ␉{0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x814e, "^P5GD1-VM$", NULL, NULL, P3, "ASUS", "P5GD1-VM/S", 0, OK, intel_ich_gpio21_raise},␊ |
| 2161 | ␉{0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x814e, NULL, NULL, NULL, P3, "ASUS", "P5GD1(-VM)", 0, NT, intel_ich_gpio21_raise},␊ |
| 2162 | ␉{0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x813d, "^P5GD2-Premium$", NULL, NULL, P3, "ASUS", "P5GD2 Premium", 0, OK, intel_ich_gpio21_raise},␊ |
| 2163 | ␉{0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x813d, "^P5GDC-V$", NULL, NULL, P3, "ASUS", "P5GDC-V Deluxe", 0, OK, intel_ich_gpio21_raise},␊ |
| 2164 | ␉{0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x813d, "^P5GDC$", NULL, NULL, P3, "ASUS", "P5GDC Deluxe", 0, OK, intel_ich_gpio21_raise},␊ |
| 2165 | ␉{0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x813d, NULL, NULL, NULL, P3, "ASUS", "P5GD2/C variants", 0, NT, intel_ich_gpio21_raise},␊ |
| 2166 | ␉{0x8086, 0x27b8, 0x103c, 0x2a22, 0x8086, 0x2770, 0x103c, 0x2a22, "^LITHIUM$", NULL, NULL, P3, "ASUS", "P5LP-LE (Lithium-UL8E)",0, OK, intel_ich_gpio34_raise},␊ |
| 2167 | ␉{0x8086, 0x27b8, 0x1043, 0x2a22, 0x8086, 0x2770, 0x1043, 0x2a22, "^P5LP-LE$", NULL, NULL, P3, "ASUS", "P5LP-LE (Epson OEM)", 0, OK, intel_ich_gpio34_raise},␊ |
| 2168 | ␉{0x8086, 0x27da, 0x1043, 0x8179, 0x8086, 0x27b8, 0x1043, 0x8179, "^P5LD2$", NULL, NULL, P3, "ASUS", "P5LD2", 0, NT, intel_ich_gpio16_raise},␊ |
| 2169 | ␉{0x10DE, 0x0030, 0x1043, 0x818a, 0x8086, 0x100E, 0x1043, 0x80EE, NULL, NULL, NULL, P3, "ASUS", "P5ND2-SLI Deluxe", 0, OK, nvidia_mcp_gpio10_raise},␊ |
| 2170 | ␉{0x10DE, 0x0260, 0x1043, 0x81BC, 0x10DE, 0x026C, 0x1043, 0x829E, "^P5N-D$", NULL, NULL, P3, "ASUS", "P5N-D", 0, OK, it8718f_gpio63_raise},␊ |
| 2171 | ␉{0x10DE, 0x0260, 0x1043, 0x81BC, 0x10DE, 0x026C, 0x1043, 0x8249, "^P5N-E SLI$",NULL, NULL, P3, "ASUS", "P5N-E SLI", 0, NT, it8718f_gpio63_raise},␊ |
| 2172 | ␉{0x8086, 0x24dd, 0x1043, 0x80a6, 0x8086, 0x2570, 0x1043, 0x8157, NULL, NULL, NULL, P3, "ASUS", "P5PE-VM", 0, OK, intel_ich_gpio21_raise},␊ |
| 2173 | ␉{0x10b7, 0x9055, 0x1028, 0x0082, 0x8086, 0x7190, 0, 0, NULL, NULL, NULL, P3, "Dell", "OptiPlex GX1", 0, OK, intel_piix4_gpo30_lower},␊ |
| 2174 | ␉{0x8086, 0x3590, 0x1028, 0x016c, 0x1000, 0x0030, 0x1028, 0x016c, NULL, NULL, NULL, P3, "Dell", "PowerEdge 1850", 0, OK, intel_ich_gpio23_raise},␊ |
| 2175 | ␉{0x10de, 0x03ea, 0x1019, 0x2602, 0x10de, 0x03e0, 0x1019, 0x2602, NULL, NULL, NULL, P3, "Elitegroup", "GeForce6100SM-M", 0, OK, board_ecs_geforce6100sm_m},␊ |
| 2176 | ␉{0x1106, 0x3038, 0x1019, 0x0996, 0x1106, 0x3177, 0x1019, 0x0996, NULL, NULL, NULL, P3, "Elitegroup", "K7VTA3", 256, OK, NULL},␊ |
| 2177 | ␉{0x1106, 0x3177, 0x1106, 0x3177, 0x1106, 0x3059, 0x1695, 0x3005, NULL, NULL, NULL, P3, "EPoX", "EP-8K5A2", 0, OK, w836xx_memw_enable_2e},␊ |
| 2178 | ␉{0x10DE, 0x005E, 0x1695, 0x1010, 0x10DE, 0x0050, 0x1695, 0x1010, "8NPA7I", NULL, NULL, P3, "EPoX", "EP-8NPA7I", 0, OK, nvidia_mcp_gpio4_raise},␊ |
| 2179 | ␉{0x10DE, 0x005E, 0x1695, 0x1010, 0x10DE, 0x0050, 0x1695, 0x1010, "9NPA7I", NULL, NULL, P3, "EPoX", "EP-9NPA7I", 0, OK, nvidia_mcp_gpio4_raise},␊ |
| 2180 | ␉{0x10EC, 0x8139, 0x1695, 0x9001, 0x11C1, 0x5811, 0x1695, 0x9015, NULL, NULL, NULL, P3, "EPoX", "EP-8RDA3+", 0, OK, nvidia_mcp_gpio31_raise},␊ |
| 2181 | ␉{0x8086, 0x7110, 0, 0, 0x8086, 0x7190, 0, 0, NULL, "epox", "ep-bx3", P3, "EPoX", "EP-BX3", 0, NT, intel_piix4_gpo22_raise},␊ |
| 2182 | ␉{0x10de, 0x02f0, 0x105b, 0x0d01, 0x10de, 0x0264, 0x105b, 0x0d01, NULL, NULL, NULL, P3, "Foxconn", "6150K8MD-8EKRSH", 0, NT, nvidia_mcp_gpio2_raise},␊ |
| 2183 | ␉{0x8086, 0x2443, 0x8086, 0x2442, 0x8086, 0x1130, 0x8086, 0x1130, "^6IEM ", NULL, NULL, P3, "GIGABYTE", "GA-6IEM", 0, NT, intel_ich_gpio25_raise},␊ |
| 2184 | ␉{0x1106, 0x0686, 0x1106, 0x0686, 0x1106, 0x3058, 0x1458, 0xa000, NULL, NULL, NULL, P3, "GIGABYTE", "GA-7ZM", 512, OK, NULL},␊ |
| 2185 | ␉{0x8086, 0x2570, 0x1458, 0x2570, 0x8086, 0x24d0, 0, 0, "^8IP775/-G$",NULL, NULL, P3, "GIGABYTE", "GA-8IP775", 0, OK, intel_ich_gpio32_raise},␊ |
| 2186 | ␉{0x8086, 0x244b, 0x8086, 0x2442, 0x8086, 0x2445, 0x1458, 0xa002, NULL, NULL, NULL, P3, "GIGABYTE", "GA-8IRML", 0, OK, intel_ich_gpio25_raise},␊ |
| 2187 | ␉{0x8086, 0x24c3, 0x1458, 0x24c2, 0x8086, 0x24cd, 0x1458, 0x5004, NULL, NULL, NULL, P3, "GIGABYTE", "GA-8PE667 Ultra 2", 0, OK, intel_ich_gpio32_raise},␊ |
| 2188 | ␉{0x1039, 0x0651, 0x1039, 0x0651, 0x1039, 0x7002, 0x1458, 0x5004, "^GA-8SIMLH$",NULL, NULL, P3, "GIGABYTE", "GA-8SIMLH", 0, OK, sis_gpio0_raise_and_w836xx_memw},␊ |
| 2189 | ␉{0x10DE, 0x02F1, 0x1458, 0x5000, 0x10DE, 0x0261, 0x1458, 0x5001, NULL, NULL, NULL, P3, "GIGABYTE", "GA-K8N51GMF", 0, OK, nvidia_mcp_gpio3b_raise},␊ |
| 2190 | ␉{0x10DE, 0x026C, 0x1458, 0xA102, 0x10DE, 0x0260, 0x1458, 0x5001, NULL, NULL, NULL, P3, "GIGABYTE", "GA-K8N51GMF-9", 0, OK, nvidia_mcp_gpio3b_raise},␊ |
| 2191 | ␉{0x10de, 0x00e4, 0x1458, 0x0c11, 0x10de, 0x00e0, 0x1458, 0x0c11, NULL, NULL, NULL, P3, "GIGABYTE", "GA-K8NS Pro-939", 0, NT, nvidia_mcp_gpio0a_raise},␊ |
| 2192 | ␉{0x10DE, 0x0050, 0x1458, 0x0C11, 0x10DE, 0x005e, 0x1458, 0x5000, NULL, NULL, NULL, P3, "GIGABYTE", "GA-K8N-SLI", 0, OK, nvidia_mcp_gpio21_raise},␊ |
| 2193 | ␉{0x8086, 0x2415, 0x103c, 0x1250, 0x10b7, 0x9200, 0x103c, 0x1247, NULL, NULL, NULL, P3, "HP", "e-Vectra P2706T", 0, OK, board_hp_p2706t},␊ |
| 2194 | ␉{0x1166, 0x0223, 0x103c, 0x320d, 0x14e4, 0x1678, 0x103c, 0x703e, NULL, "hp", "dl145_g3", P3, "HP", "ProLiant DL145 G3", 0, OK, board_hp_dl145_g3_enable},␊ |
| 2195 | ␉{0x1166, 0x0223, 0x103c, 0x320d, 0x14e4, 0x1648, 0x103c, 0x310f, NULL, "hp", "dl165_g6", P3, "HP", "ProLiant DL165 G6", 0, OK, board_hp_dl165_g6_enable},␊ |
| 2196 | ␉{0x8086, 0x2580, 0x103c, 0x2a08, 0x8086, 0x2640, 0x103c, 0x2a0a, NULL, NULL, NULL, P3, "HP", "Puffer2-UL8E", 0, OK, intel_ich_gpio18_raise},␊ |
| 2197 | ␉{0x8086, 0x2415, 0x103c, 0x1249, 0x10b7, 0x9200, 0x103c, 0x1246, NULL, NULL, NULL, P3, "HP", "Vectra VL400", 0, OK, board_hp_vl400},␊ |
| 2198 | ␉{0x8086, 0x1a30, 0x103c, 0x1a30, 0x8086, 0x2443, 0x103c, 0x2440, "^VL420$", NULL, NULL, P3, "HP", "Vectra VL420 SFF", 0, OK, intel_ich_gpio22_raise},␊ |
| 2199 | ␉{0x10de, 0x0369, 0x103c, 0x12fe, 0x10de, 0x0364, 0x103c, 0x12fe, NULL, "hp", "xw9400", P3, "HP", "xw9400", 0, OK, nvidia_mcp_gpio5_raise},␊ |
| 2200 | ␉{0x8086, 0x27A0, 0, 0, 0x8086, 0x27B9, 0, 0, NULL, "ibase", "mb899", P3, "IBASE", "MB899", 0, OK, intel_ich_gpio26_raise},␊ |
| 2201 | ␉{0x1166, 0x0205, 0x1014, 0x0347, 0x1002, 0x515E, 0x1014, 0x0325, NULL, NULL, NULL, P3, "IBM", "x3455", 0, OK, board_ibm_x3455},␊ |
| 2202 | ␉{0x1039, 0x5513, 0x8086, 0xd61f, 0x1039, 0x6330, 0x8086, 0xd61f, NULL, NULL, NULL, P3, "Intel", "D201GLY", 0, OK, wbsio_check_for_spi},␊ |
| 2203 | ␉{0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^SE440BX-2$", NULL, NULL, P3, "Intel", "SE440BX-2", 0, NT, intel_piix4_gpo27_lower},␊ |
| 2204 | ␉{0x1022, 0x7468, 0, 0, 0, 0, 0, 0, NULL, "iwill", "dk8_htx", P3, "IWILL", "DK8-HTX", 0, OK, w83627hf_gpio24_raise_2e},␊ |
| 2205 | ␉{0x8086, 0x27A0, 0x8086, 0x27a0, 0x8086, 0x27b8, 0x8086, 0x27b8, NULL, "kontron", "986lcd-m", P3, "Kontron", "986LCD-M", 0, OK, board_kontron_986lcd_m},␊ |
| 2206 | ␉{0x8086, 0x2411, 0x8086, 0x2411, 0x8086, 0x7125, 0x0e11, 0xb165, NULL, NULL, NULL, P3, "Mitac", "6513WU", 0, OK, board_mitac_6513wu},␊ |
| 2207 | ␉{0x8086, 0x8186, 0x8086, 0x8186, 0x8086, 0x8800, 0x0000, 0x0000, "^MSC Vertriebs GmbH$", NULL, NULL, P2, "MSC", "Q7-TCTC", 0, OK, p2_not_a_laptop},␊ |
| 2208 | ␉{0x10DE, 0x005E, 0x1462, 0x7125, 0x10DE, 0x0052, 0x1462, 0x7125, NULL, NULL, NULL, P3, "MSI", "K8N Neo4-F", 0, OK, nvidia_mcp_gpio2_raise}, /* TODO: Should probably be K8N Neo4 Platinum, see http://www.coreboot.org/pipermail/flashrom/2010-August/004362.html. */␊ |
| 2209 | ␉{0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^MS-6163 (i440BX)$", NULL, NULL, P3, "MSI", "MS-6163 (MS-6163 Pro)", 0, OK, intel_piix4_gpo14_raise},␊ |
| 2210 | ␉{0x1039, 0x0745, 0, 0, 0x1039, 0x0018, 0, 0, "^MS-6561", NULL, NULL, P3, "MSI", "MS-6561 (745 Ultra)", 0, OK, w836xx_memw_enable_2e},␊ |
| 2211 | ␉{0x8086, 0x2560, 0x1462, 0x5770, 0x8086, 0x2562, 0x1462, 0x5778, NULL, NULL, NULL, P3, "MSI", "MS-6577 (Xenon)", 0, OK, w83627hf_gpio25_raise_2e},␊ |
| 2212 | ␉{0x13f6, 0x0111, 0x1462, 0x5900, 0x1106, 0x3177, 0x1106, 0, NULL, NULL, NULL, P3, "MSI", "MS-6590 (KT4 Ultra)", 0, OK, board_msi_kt4v},␊ |
| 2213 | ␉{0x1106, 0x3149, 0x1462, 0x7094, 0x10ec, 0x8167, 0x1462, 0x094c, NULL, NULL, NULL, P3, "MSI", "MS-6702E (K8T Neo2-F)", 0, OK, w83627thf_gpio44_raise_2e},␊ |
| 2214 | ␉{0x1106, 0x0571, 0x1462, 0x7120, 0x1106, 0x3065, 0x1462, 0x7120, NULL, NULL, NULL, P3, "MSI", "MS-6712 (KT4V)", 0, OK, board_msi_kt4v},␊ |
| 2215 | ␉{0x1106, 0x3148, 0 , 0 , 0x1106, 0x3177, 0 , 0 , NULL, "msi", "ms6787", P3, "MSI", "MS-6787 (P4MAM-V/P4MAM-L)", 0, OK, w836xx_memw_enable_2e},␊ |
| 2216 | ␉{0x8086, 0x24d3, 0x1462, 0x7880, 0x8086, 0x2570, 0, 0, NULL,␉ NULL, NULL, P3, "MSI", "MS-6788-040 (848P NeoV)", 0, OK, intel_ich_gpio32_raise},␊ |
| 2217 | ␉{0x1039, 0x7012, 0x1462, 0x0050, 0x1039, 0x6325, 0x1462, 0x0058, NULL, NULL, NULL, P3, "MSI", "MS-7005 (651M-L)", 0, OK, sis_gpio0_raise_and_w836xx_memw},␊ |
| 2218 | ␉{0x10DE, 0x00E0, 0x1462, 0x0250, 0x10DE, 0x00E1, 0x1462, 0x0250, NULL, NULL, NULL, P3, "MSI", "MS-7025 (K8N Neo2 Platinum)", 0, OK, nvidia_mcp_gpio0c_raise},␊ |
| 2219 | ␉{0x8086, 0x2658, 0x1462, 0x7046, 0x1106, 0x3044, 0x1462, 0x046d, NULL, NULL, NULL, P3, "MSI", "MS-7046", 0, OK, intel_ich_gpio19_raise},␊ |
| 2220 | ␉{0x8086, 0x244b, 0x1462, 0x3910, 0x8086, 0x2442, 0x1462, 0x3910, NULL, NULL, NULL, P3, "MSI", "MS-6391 (845 Pro4)", 0, OK, intel_ich_gpio23_raise},␊ |
| 2221 | ␉{0x1106, 0x3149, 0x1462, 0x7061, 0x1106, 0x3227, 0, 0, NULL, NULL, NULL, P3, "MSI", "MS-7061 (KM4M-V/KM4AM-V)", 0, OK, w836xx_memw_enable_2e},␊ |
| 2222 | ␉{0x10DE, 0x005E, 0x1462, 0x7135, 0x10DE, 0x0050, 0x1462, 0x7135, NULL, "msi", "k8n-neo3", P3, "MSI", "MS-7135 (K8N Neo3)", 0, OK, w83627thf_gpio44_raise_4e},␊ |
| 2223 | ␉{0x10DE, 0x0270, 0x1462, 0x7207, 0x10DE, 0x0264, 0x1462, 0x7207, NULL, NULL, NULL, P3, "MSI", "MS-7207 (K8NGM2-L)", 0, NT, nvidia_mcp_gpio2_raise},␊ |
| 2224 | ␉{0x1011, 0x0019, 0xaa55, 0xaa55, 0x8086, 0x7190, 0, 0, NULL, NULL, NULL, P3, "Nokia", "IP530", 0, OK, fdc37b787_gpio50_raise_3f0},␊ |
| 2225 | ␉{0x8086, 0x24d3, 0x144d, 0xb025, 0x8086, 0x1050, 0x144d, 0xb025, NULL, NULL, NULL, P3, "Samsung", "Polaris 32", 0, OK, intel_ich_gpio21_raise},␊ |
| 2226 | ␉{0x1106, 0x3099, 0, 0, 0x1106, 0x3074, 0, 0, NULL, "shuttle", "ak31", P3, "Shuttle", "AK31", 0, OK, w836xx_memw_enable_2e},␊ |
| 2227 | ␉{0x1106, 0x3104, 0x1297, 0xa238, 0x1106, 0x3059, 0x1297, 0xc063, NULL, NULL, NULL, P3, "Shuttle", "AK38N", 256, OK, NULL},␊ |
| 2228 | ␉{0x10DE, 0x0050, 0x1297, 0x5036, 0x1412, 0x1724, 0x1297, 0x5036, NULL, NULL, NULL, P3, "Shuttle", "FN25", 0, OK, board_shuttle_fn25},␊ |
| 2229 | ␉{0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x3058, 0x15DD, 0x7609, NULL, NULL, NULL, P3, "Soyo", "SY-7VCA", 0, OK, via_apollo_gpo0_lower},␊ |
| 2230 | ␉{0x10de, 0x0364, 0x108e, 0x6676, 0x10de, 0x0369, 0x108e, 0x6676, "^Sun Ultra 40 M2", NULL, NULL, P3, "Sun", "Ultra 40 M2", 0, OK, board_sun_ultra_40_m2},␊ |
| 2231 | ␉{0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x0596, 0x1106, 0, NULL, NULL, NULL, P3, "Tekram", "P6Pro-A5", 256, OK, NULL},␊ |
| 2232 | ␉{0x1106, 0x3123, 0x1106, 0x3123, 0x1106, 0x3059, 0x1106, 0x4161, NULL, NULL, NULL, P3, "Termtek", "TK-3370 (Rev:2.5B)", 0, OK, w836xx_memw_enable_4e},␊ |
| 2233 | ␉{0x8086, 0x1076, 0x8086, 0x1176, 0x1106, 0x3059, 0x10f1, 0x2498, NULL, NULL, NULL, P3, "Tyan", "S2498 (Tomcat K7M)", 0, OK, w836xx_memw_enable_2e},␊ |
| 2234 | ␉{0x1106, 0x0259, 0x1106, 0xAA07, 0x1106, 0x3227, 0x1106, 0xAA07, NULL, NULL, NULL, P3, "VIA", "EPIA EK", 0, NT, via_vt823x_gpio9_raise},␊ |
| 2235 | ␉{0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01, NULL, NULL, NULL, P3, "VIA", "EPIA M/MII/...", 0, OK, via_vt823x_gpio15_raise},␊ |
| 2236 | ␉{0x1106, 0x0259, 0x1106, 0x3227, 0x1106, 0x3065, 0x1106, 0x3149, NULL, NULL, NULL, P3, "VIA", "EPIA-N/NL", 0, OK, via_vt823x_gpio9_raise},␊ |
| 2237 | #endif␊ |
| 2238 | ␉{ 0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL, NULL, P3, NULL, NULL, 0, NT, NULL}, /* end marker */␊ |
| 2239 | };␊ |
| 2240 | ␊ |
| 2241 | /*␊ |
| 2242 | * Match boards on coreboot table gathered vendor and part name.␊ |
| 2243 | * Require main PCI IDs to match too as extra safety.␊ |
| 2244 | */␊ |
| 2245 | static const struct board_match *board_match_cbname(const char *vendor,␊ |
| 2246 | ␉␉␉␉␉␉ const char *part)␊ |
| 2247 | {␊ |
| 2248 | ␉const struct board_match *board = board_matches;␊ |
| 2249 | ␉const struct board_match *partmatch = NULL;␊ |
| 2250 | ␊ |
| 2251 | ␉for (; board->vendor_name; board++) {␊ |
| 2252 | ␉␉if (vendor && (!board->lb_vendor␊ |
| 2253 | ␉␉␉ || strcasecmp(board->lb_vendor, vendor)))␊ |
| 2254 | ␉␉␉continue;␊ |
| 2255 | ␊ |
| 2256 | ␉␉if (!board->lb_part || strcasecmp(board->lb_part, part))␊ |
| 2257 | ␉␉␉continue;␊ |
| 2258 | ␊ |
| 2259 | ␉␉if (!pci_dev_find(board->first_vendor, board->first_device))␊ |
| 2260 | ␉␉␉continue;␊ |
| 2261 | ␊ |
| 2262 | ␉␉if (board->second_vendor &&␊ |
| 2263 | ␉␉ !pci_dev_find(board->second_vendor, board->second_device))␊ |
| 2264 | ␉␉␉continue;␊ |
| 2265 | ␊ |
| 2266 | ␉␉if (vendor)␊ |
| 2267 | ␉␉␉return board;␊ |
| 2268 | ␊ |
| 2269 | ␉␉if (partmatch) {␊ |
| 2270 | ␉␉␉/* a second entry has a matching part name */␊ |
| 2271 | ␉␉␉msg_pinfo("AMBIGUOUS BOARD NAME: %s\n", part);␊ |
| 2272 | ␉␉␉msg_pinfo("At least vendors '%s' and '%s' match.\n",␊ |
| 2273 | ␉␉␉␉ partmatch->lb_vendor, board->lb_vendor);␊ |
| 2274 | ␉␉␉msg_perr("Please use the full -p internal:mainboard="␊ |
| 2275 | ␉␉␉␉ "vendor:part syntax.\n");␊ |
| 2276 | ␉␉␉return NULL;␊ |
| 2277 | ␉␉}␊ |
| 2278 | ␉␉partmatch = board;␊ |
| 2279 | ␉}␊ |
| 2280 | ␊ |
| 2281 | ␉if (partmatch)␊ |
| 2282 | ␉␉return partmatch;␊ |
| 2283 | ␊ |
| 2284 | ␉if (!partvendor_from_cbtable) {␊ |
| 2285 | ␉␉/* Only warn if the mainboard type was not gathered from the␊ |
| 2286 | ␉␉ * coreboot table. If it was, the coreboot implementor is␊ |
| 2287 | ␉␉ * expected to fix flashrom, too.␊ |
| 2288 | ␉␉ */␊ |
| 2289 | ␉␉msg_perr("\nUnknown vendor:board from -p internal:mainboard="␊ |
| 2290 | ␉␉␉ " programmer parameter:\n%s:%s\n\n",␊ |
| 2291 | ␉␉␉ vendor, part);␊ |
| 2292 | ␉}␊ |
| 2293 | ␉return NULL;␊ |
| 2294 | }␊ |
| 2295 | ␊ |
| 2296 | /*␊ |
| 2297 | * Match boards on PCI IDs and subsystem IDs.␊ |
| 2298 | * Second set of IDs can be either main+subsystem IDs, main IDs or no IDs.␊ |
| 2299 | */␊ |
| 2300 | const static struct board_match *board_match_pci_ids(enum board_match_phase phase)␊ |
| 2301 | {␊ |
| 2302 | ␉const struct board_match *board = board_matches;␊ |
| 2303 | ␊ |
| 2304 | ␉for (; board->vendor_name; board++) {␊ |
| 2305 | ␉␉if ((!board->first_card_vendor || !board->first_card_device) &&␊ |
| 2306 | ␉␉ !board->dmi_pattern)␊ |
| 2307 | ␉␉␉continue;␊ |
| 2308 | ␉␉if (board->phase != phase)␊ |
| 2309 | ␉␉␉continue;␊ |
| 2310 | ␊ |
| 2311 | ␉␉if (!pci_card_find(board->first_vendor, board->first_device,␊ |
| 2312 | ␉␉␉␉ board->first_card_vendor,␊ |
| 2313 | ␉␉␉␉ board->first_card_device))␊ |
| 2314 | ␉␉␉continue;␊ |
| 2315 | ␊ |
| 2316 | ␉␉if (board->second_vendor) {␊ |
| 2317 | ␉␉␉if (board->second_card_vendor) {␊ |
| 2318 | ␉␉␉␉if (!pci_card_find(board->second_vendor,␊ |
| 2319 | ␉␉␉␉␉␉ board->second_device,␊ |
| 2320 | ␉␉␉␉␉␉ board->second_card_vendor,␊ |
| 2321 | ␉␉␉␉␉␉ board->second_card_device))␊ |
| 2322 | ␉␉␉␉␉continue;␊ |
| 2323 | ␉␉␉} else {␊ |
| 2324 | ␉␉␉␉if (!pci_dev_find(board->second_vendor,␊ |
| 2325 | ␉␉␉␉␉␉ board->second_device))␊ |
| 2326 | ␉␉␉␉␉continue;␊ |
| 2327 | ␉␉␉}␊ |
| 2328 | ␉␉}␊ |
| 2329 | ␊ |
| 2330 | ␉␉if (board->dmi_pattern) {␊ |
| 2331 | ␉␉␉if (!has_dmi_support) {␊ |
| 2332 | ␉␉␉␉msg_perr("WARNING: Can't autodetect %s %s,"␊ |
| 2333 | ␉␉␉␉␉ " DMI info unavailable.\n",␊ |
| 2334 | ␉␉␉␉␉ board->vendor_name, board->board_name);␊ |
| 2335 | ␉␉␉␉continue;␊ |
| 2336 | ␉␉␉} else {␊ |
| 2337 | ␉␉␉␉if (!dmi_match(board->dmi_pattern))␊ |
| 2338 | ␉␉␉␉␉continue;␊ |
| 2339 | ␉␉␉}␊ |
| 2340 | ␉␉}␊ |
| 2341 | ␊ |
| 2342 | ␉␉return board;␊ |
| 2343 | ␉}␊ |
| 2344 | ␊ |
| 2345 | ␉return NULL;␊ |
| 2346 | }␊ |
| 2347 | ␊ |
| 2348 | static int unsafe_board_handler(const struct board_match *board)␊ |
| 2349 | {␊ |
| 2350 | ␉if (!board)␊ |
| 2351 | ␉␉return 1;␊ |
| 2352 | ␊ |
| 2353 | ␉if (board->status == OK)␊ |
| 2354 | ␉␉return 0;␊ |
| 2355 | ␊ |
| 2356 | ␉if (!force_boardenable) {␊ |
| 2357 | ␉␉msg_pinfo("WARNING: Your mainboard is %s %s, but the mainboard-specific\n"␊ |
| 2358 | ␉␉␉ "code has not been tested, and thus will not be executed by default.\n"␊ |
| 2359 | ␉␉␉ "Depending on your hardware environment, erasing, writing or even probing\n"␊ |
| 2360 | ␉␉␉ "can fail without running the board specific code.\n\n"␊ |
| 2361 | ␉␉␉ "Please see the man page (section PROGRAMMER SPECIFIC INFO, subsection\n"␊ |
| 2362 | ␉␉␉ "\"internal programmer\") for details.\n",␊ |
| 2363 | ␉␉␉ board->vendor_name, board->board_name);␊ |
| 2364 | ␉␉return 1;␊ |
| 2365 | ␉}␊ |
| 2366 | ␉msg_pinfo("NOTE: Running an untested board enable procedure.\n"␊ |
| 2367 | ␉␉ "Please report success/failure to flashrom@flashrom.org\n"␊ |
| 2368 | ␉␉ "with your board name and SUCCESS or FAILURE in the subject.\n");␊ |
| 2369 | ␉return 0;␊ |
| 2370 | }␊ |
| 2371 | ␊ |
| 2372 | /* FIXME: Should this be identical to board_flash_enable? */␊ |
| 2373 | static int board_handle_phase(enum board_match_phase phase)␊ |
| 2374 | {␊ |
| 2375 | ␉const struct board_match *board = NULL;␊ |
| 2376 | ␊ |
| 2377 | ␉board = board_match_pci_ids(phase);␊ |
| 2378 | ␊ |
| 2379 | ␉if (unsafe_board_handler(board))␊ |
| 2380 | ␉␉board = NULL;␊ |
| 2381 | ␊ |
| 2382 | ␉if (!board)␊ |
| 2383 | ␉␉return 0;␊ |
| 2384 | ␊ |
| 2385 | ␉if (!board->enable) {␊ |
| 2386 | ␉␉/* Not sure if there is a valid case for this. */␊ |
| 2387 | ␉␉msg_perr("Board match found, but nothing to do?\n");␊ |
| 2388 | ␉␉return 0;␊ |
| 2389 | ␉}␊ |
| 2390 | ␊ |
| 2391 | ␉return board->enable();␊ |
| 2392 | }␊ |
| 2393 | ␊ |
| 2394 | void board_handle_before_superio(void)␊ |
| 2395 | {␊ |
| 2396 | ␉board_handle_phase(P1);␊ |
| 2397 | }␊ |
| 2398 | ␊ |
| 2399 | void board_handle_before_laptop(void)␊ |
| 2400 | {␊ |
| 2401 | ␉board_handle_phase(P2);␊ |
| 2402 | }␊ |
| 2403 | ␊ |
| 2404 | int board_flash_enable(const char *vendor, const char *part)␊ |
| 2405 | {␊ |
| 2406 | ␉const struct board_match *board = NULL;␊ |
| 2407 | ␉int ret = 0;␊ |
| 2408 | ␊ |
| 2409 | ␉if (part)␊ |
| 2410 | ␉␉board = board_match_cbname(vendor, part);␊ |
| 2411 | ␊ |
| 2412 | ␉if (!board)␊ |
| 2413 | ␉␉board = board_match_pci_ids(P3);␊ |
| 2414 | ␊ |
| 2415 | ␉if (unsafe_board_handler(board))␊ |
| 2416 | ␉␉board = NULL;␊ |
| 2417 | ␊ |
| 2418 | ␉if (board) {␊ |
| 2419 | ␉␉if (board->max_rom_decode_parallel)␊ |
| 2420 | ␉␉␉max_rom_decode.parallel =␊ |
| 2421 | ␉␉␉␉board->max_rom_decode_parallel * 1024;␊ |
| 2422 | ␊ |
| 2423 | ␉␉if (board->enable != NULL) {␊ |
| 2424 | ␉␉␉msg_pinfo("Disabling flash write protection for "␊ |
| 2425 | ␉␉␉␉ "board \"%s %s\"... ", board->vendor_name,␊ |
| 2426 | ␉␉␉␉ board->board_name);␊ |
| 2427 | ␊ |
| 2428 | ␉␉␉ret = board->enable();␊ |
| 2429 | ␉␉␉if (ret)␊ |
| 2430 | ␉␉␉␉msg_pinfo("FAILED!\n");␊ |
| 2431 | ␉␉␉else␊ |
| 2432 | ␉␉␉␉msg_pinfo("OK.\n");␊ |
| 2433 | ␉␉}␊ |
| 2434 | ␉}␊ |
| 2435 | ␊ |
| 2436 | ␉return ret;␊ |
| 2437 | }␊ |
| 2438 | |
