| 1 | /*␊ |
| 2 | * This file is part of the flashrom project.␊ |
| 3 | *␊ |
| 4 | * Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>␊ |
| 5 | *␊ |
| 6 | * This program is free software; you can redistribute it and/or modify␊ |
| 7 | * it under the terms of the GNU General Public License as published by␊ |
| 8 | * the Free Software Foundation; either version 2 of the License, or␊ |
| 9 | * (at your option) any later version.␊ |
| 10 | *␊ |
| 11 | * This program is distributed in the hope that it will be useful,␊ |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of␊ |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the␊ |
| 14 | * GNU General Public License for more details.␊ |
| 15 | *␊ |
| 16 | * You should have received a copy of the GNU General Public License␊ |
| 17 | * along with this program; if not, write to the Free Software␊ |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA␊ |
| 19 | */␊ |
| 20 | ␊ |
| 21 | #if defined(__i386__) || defined(__x86_64__)␊ |
| 22 | ␊ |
| 23 | #include <stdlib.h>␊ |
| 24 | #include <string.h>␊ |
| 25 | #include "flash.h"␊ |
| 26 | #include "programmer.h"␊ |
| 27 | ␊ |
| 28 | #define BIOS_ROM_ADDR␉␉0x90␊ |
| 29 | #define BIOS_ROM_DATA␉␉0x94␊ |
| 30 | ␊ |
| 31 | #define REG_FLASH_ACCESS␉0x58␊ |
| 32 | ␊ |
| 33 | #define PCI_VENDOR_ID_HPT␉0x1103␊ |
| 34 | ␊ |
| 35 | const struct pcidev_status ata_hpt[] = {␊ |
| 36 | ␉{0x1103, 0x0004, NT, "Highpoint", "HPT366/368/370/370A/372/372N"},␊ |
| 37 | ␉{0x1103, 0x0005, NT, "Highpoint", "HPT372A/372N"},␊ |
| 38 | ␉{0x1103, 0x0006, NT, "Highpoint", "HPT302/302N"},␊ |
| 39 | ␊ |
| 40 | ␉{},␊ |
| 41 | };␊ |
| 42 | ␊ |
| 43 | static void atahpt_chip_writeb(const struct flashctx *flash, uint8_t val,␊ |
| 44 | ␉␉␉ chipaddr addr);␊ |
| 45 | static uint8_t atahpt_chip_readb(const struct flashctx *flash,␊ |
| 46 | ␉␉␉␉ const chipaddr addr);␊ |
| 47 | static const struct par_programmer par_programmer_atahpt = {␊ |
| 48 | ␉␉.chip_readb␉␉= atahpt_chip_readb,␊ |
| 49 | ␉␉.chip_readw␉␉= fallback_chip_readw,␊ |
| 50 | ␉␉.chip_readl␉␉= fallback_chip_readl,␊ |
| 51 | ␉␉.chip_readn␉␉= fallback_chip_readn,␊ |
| 52 | ␉␉.chip_writeb␉␉= atahpt_chip_writeb,␊ |
| 53 | ␉␉.chip_writew␉␉= fallback_chip_writew,␊ |
| 54 | ␉␉.chip_writel␉␉= fallback_chip_writel,␊ |
| 55 | ␉␉.chip_writen␉␉= fallback_chip_writen,␊ |
| 56 | };␊ |
| 57 | ␊ |
| 58 | static int atahpt_shutdown(void *data)␊ |
| 59 | {␊ |
| 60 | ␉/* Flash access is disabled automatically by PCI restore. */␊ |
| 61 | ␉pci_cleanup(pacc);␊ |
| 62 | ␉release_io_perms();␊ |
| 63 | ␉return 0;␊ |
| 64 | }␊ |
| 65 | ␊ |
| 66 | int atahpt_init(void)␊ |
| 67 | {␊ |
| 68 | ␉uint32_t reg32;␊ |
| 69 | ␊ |
| 70 | ␉get_io_perms();␊ |
| 71 | ␊ |
| 72 | ␉io_base_addr = pcidev_init(PCI_BASE_ADDRESS_4, ata_hpt);␊ |
| 73 | ␊ |
| 74 | ␉/* Enable flash access. */␊ |
| 75 | ␉reg32 = pci_read_long(pcidev_dev, REG_FLASH_ACCESS);␊ |
| 76 | ␉reg32 |= (1 << 24);␊ |
| 77 | ␉rpci_write_long(pcidev_dev, REG_FLASH_ACCESS, reg32);␊ |
| 78 | ␊ |
| 79 | ␉if (register_shutdown(atahpt_shutdown, NULL))␊ |
| 80 | ␉␉return 1;␊ |
| 81 | ␊ |
| 82 | ␉register_par_programmer(&par_programmer_atahpt, BUS_PARALLEL);␊ |
| 83 | ␊ |
| 84 | ␉return 0;␊ |
| 85 | }␊ |
| 86 | ␊ |
| 87 | static void atahpt_chip_writeb(const struct flashctx *flash, uint8_t val,␊ |
| 88 | ␉␉␉ chipaddr addr)␊ |
| 89 | {␊ |
| 90 | ␉OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR);␊ |
| 91 | ␉OUTB(val, io_base_addr + BIOS_ROM_DATA);␊ |
| 92 | }␊ |
| 93 | ␊ |
| 94 | static uint8_t atahpt_chip_readb(const struct flashctx *flash,␊ |
| 95 | ␉␉␉␉ const chipaddr addr)␊ |
| 96 | {␊ |
| 97 | ␉OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR);␊ |
| 98 | ␉return INB(io_base_addr + BIOS_ROM_DATA);␊ |
| 99 | }␊ |
| 100 | ␊ |
| 101 | #else␊ |
| 102 | #error PCI port I/O access is not supported on this architecture yet.␊ |
| 103 | #endif␊ |
| 104 | |
